350 results about "Daisy chain" patented technology

A calibration unit comprises a first port which is arranged for being connected to a measurement device; a calibration module comprising at least three different calibration standards for calibrating the measurement device; and a switching module configured to connect the first port with one of the at least three different calibration standards of the calibration module. A daisy chain port is arranged for being connected to a further calibration unit, to an external power meter, or to a device-under-test, DUT. The first port is connectable to the daisy chain port. An internal power meter is arranged within a housing of the calibration unit. The first port is connectable to the internal power meter; or an internal impedance tuner. The first port is connectable to the internal impedance tuner.

The invention discloses a time synchronization method of a system-on-chip, the system-on-chip and a vehicle. The time synchronization method of the system on chip comprises the following steps: determining daisy chain data transmission delay between a first hardware domain and a second hardware domain; determining a system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay; calibrating the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter; determining a timestamp of the second subsystem based on first subsystem time information sent from the first hardware domain; wherein the first subsystem time information comprises a timestamp of the first subsystem and clock information of a first daisy chain counter; updating the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem; by adopting the method and the device, the time synchronization between the subsystems of the system on chip can be realized.

The invention discloses a vehicle-mounted video transmission hybrid topology network, and relates to the technical field of vehicle-mounted video communication. The vehicle-mounted video transmission hybrid topology network comprises a plurality of transmission nodes, each transmission node comprises at least one input port and at least one output port, and the plurality of transmission nodes form a hybrid network of a tree topology structure and a daisy chain topology structure; wherein the tree topology structure in the hybrid network comprises a root node and a plurality of subordinate sub-nodes, the daisy chain topology structure is a sub-branch of the tree topology structure, and the hybrid network comprises a main link and a standby link which are used for signal transmission. Through innovative designs such as hybrid topology, dynamic bandwidth allocation, data retransmission, redundant channels, routing address query and the like, high bandwidth, low delay and high reliability in the field of vehicle-mounted video transmission are realized.

The invention relates to the technical field of integrated circuits, and provides a self-adaptive frequency modulation and voltage regulation chip control circuit and method, the circuit comprises a time sequence monitoring module which comprises a critical path replication sub-module and a daisy chain delay sub-module which are connected, and the critical path replication sub-module is used for simulating an actual critical data path in a chip; the daisy chain delay sub-module is used for applying a configurable delay amount on a time sequence to the output data signal; the time sequence performance after different time points is simulated; the first trigger is used for transmitting data signals; the sampling trigger module is used for sampling the data signal output by the time sequence monitoring module; the comparison logic module is used for generating a multi-bit time sequence margin indication code according to a comparison result; the time sequence margin indication code is used for adaptively adjusting the working frequency or the working voltage of the chip. According to the invention, through accurate monitoring and self-adaptive adjustment of a chip time sequence, all design margins can be utilized, and the energy utilization efficiency is improved, so that extreme low power consumption is realized.

The invention discloses a device and a method for testing the service life of a welding spot under a thermal-electric-vibration coupling load. The device comprises a thermal cycle device, a vibration device, a computer, a data acquisition instrument and a direct-current power supply. The thermal circulation device is fixed above a vibration table of the vibration device, threaded holes are formed in the vibration table, a circuit board can be fixed on the vibration table through screws, and thermal vibration coupling loading is achieved; a stable power supply is provided for welding spots on a circuit board through a direct-current power supply, so that heat-electricity-vibration coupling loading is realized; the welding spots are connected through the daisy chain, the resistance value of the welding spots is obtained through the data acquisition instrument, the computer is used for monitoring the resistance value, and an alarm value can be set, so that the service life of the welding spots is tested.

A semiconductor device includes: a first semiconductor structure including a first semiconductor substrate, one or more first conductive patterns, a plurality of first conductive plugs, and a first bonding pad; a second semiconductor structure including a second semiconductor substrate, a plurality of second conductive patterns, one or more second conductive plugs, and a second bonding pad; and two through electrodes penetrating the second semiconductor substrate and respectively connected to two second conductive patterns positioned at opposite ends of the plurality of second conductive patterns, wherein the second bonding pad is bonded to the first bonding pad so that the plurality of second conductive patterns, the one or more second conductive plugs, the second bonding pad, the first bonding pad, the plurality of first conductive plugs, and the one or more first conductive patterns form a daisy chain.

The electroencephalograph system comprises an MCU (Microprogrammed Control Unit), an acquisition unit and a buffer, the acquisition unit comprises a plurality of acquisition chips, and the plurality of acquisition chips are connected in series in a daisy chain mode through serial interfaces; the acquisition chip at the first stage is connected with the MCU unit through a serial interface; in this way, application of multiple channels is achieved, and the device can be suitable for collection of electroencephalogram signals with different functions; and the buffer can increase the driving capability of driving the DI N pin of the lower-level acquisition chip by the DOUT pin of the upper-level acquisition chip, so that the reliability of data transmission is improved.

The invention discloses an LVDS (Low Voltage Differential Signaling) type daisy chain communication method based on effective signal detection, which relates to the technical field of communication, and comprises the following steps: S1, setting acquisition nodes, and connecting all the acquisition nodes in series by using a differential LVDS link to form a daisy chain topological structure in a grading manner; s2, keeping the transceivers in the daisy chain topological structure in a sleep mode and keeping real-time detection; s3, when a high pulse signal is detected, waking up the LVDS module to receive data; and S4, after confirming that the parameters take effect, generating a response packet, returning the response packet to the computer end, returning to a dormant state, and forming a communication transmission energy-saving closed loop. According to the invention, through a mechanism of event triggering and local node participation, the system is awakened when a high-pulse effective signal is detected, so that the power consumption overhead caused by that all nodes are always active in a traditional communication architecture is avoided; the method has the advantages of greatly reducing the average power consumption of daisy chain data communication, improving the overall response rate of the system and reducing the confirmation time delay.

A portable article lifter, separator, and compressor capable moving a variety of articles. The core components are a frame, a motor, a power source, and a set of interchangeable end effectors suitable for moving different types of articles. This device is used to lift an article, separate multiple articles from each other, and compress one or more articles. Multiple devices can operate collaboratively to move a large and / or heavy article via daisy chaining the devices using synchronization modules. A transmission between the motor and the end effector controls the speed and the torque of the end effector. The device further provides an ON / Off module, a frame base, a handle, a level, wheels and rollers, and a work light.

Systems and methods for autonomous extraction of volatile minerals from extraterrestrial regolith are disclosed. A rover tows a mineral-collection wagon that mechanically prepares surface regolith and positions a detachable collector shield over a target area. When lowered, the shield rim seals against the regolith to define a localized, low-leakage environment. A radiant heating element raises the regolith to vaporization temperature; released species migrate to the shield's inner surface, which is cryogenically or ambiently cooled to condense solids as a removable film. After a heating / collection cycle, the shield is decoupled for retrieval and processing while the wagon immediately accepts a replacement shield, enabling continuous, modular operation. Embodiments support guided alignment, power coupling, optional daisy-chained wagons, and reciprocating or continuous motion to increase throughput on lunar or similar vacuum surfaces.

The invention provides a parallel daisy chain FPGA configuration method and device. The parallel daisy chain FPGA configuration method comprises the steps that FPGA chips in a board card are connected according to a parallel daisy chain structure, and the FPGA chip serving as a master chip and the FPGA chip serving as a slave chip are determined; the master chip and the slave chips control the configuration process through state machines of the master chip and the slave chips and parallel daisy chain starting signals in received code streams, so that an FPGA chip of the master chip serves as a master control end, and code streams with different configurations can be accurately configured to the master chip or sent to the corresponding slave chips in a parallel daisy chain. And the configuration function sending of the FPGA chip in the parallel daisy chain is realized.

The present disclosure relates to an apparatus using a chipset-based storage architecture. The memory architecture includes: a plurality of accelerator memory devices on a package substrate; a front-end chip on the package substrate and configured to perform communication with a host device; and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a portion of the plurality of accelerator memory devices, and coupled to each other in a daisy chain scheme.

A system having, for example, data lines. In a case of any device that loses power, to keep communications, the data lines may be disconnected from, for instance, a physical layer transceiver, and at the same time, the lines may be connected to other lines to bypass the powered-off device. FETs and reed switches may be used for connection, disconnection and bypass functions.

A battery system according to an embodiment of the present invention may include a plurality of battery management systems (BMSs) connected in a daisy chain manner. Here, each of the BMSs may include: a control unit; and a photo relay that transmits a control signal for identifier (ID) allocation, which is input from a signal input terminal, to the control unit in an optical transmission manner. In addition, when the control unit receives the control signal from the photo relay, the control unit may allocate its own ID according to a predefined ID allocation protocol, and transmit the control signal to a signal input terminal of a next BMS through a signal output terminal.

Comprising a modular display device of a plurality of display devices, comprising: a communication interface; and a plurality of driver integrated circuits (ICs), in which a first driver IC of the plurality of driver ICs is configured to transmit a first signal to a second driver IC adjacent to the first driver IC based on receiving a first signal transmitted by an external device through the communication interface, the first driver IC and the second driver IC are configured such that the first signal is sequentially transmitted to the remaining driver ICs of the plurality of driver ICs connected in a daisy chain manner, and each of the first driver IC and the second driver IC is configured to transmit a second signal transmitted by the external device to a first other display device of the plurality of display devices connected to the display device.

The invention provides a daisy chain configuration method for stacked chips, which comprises the following steps of: stacking a plurality of packaged bare chips, defining any bare chip in the plurality of bare chips as a master chip, and defining the rest bare chips as slave chips; a configuration file transmission interface and a pulse signal transmission interface which are connected with each other are arranged between the master chip and the slave chips as well as between the adjacent slave chips, and after configuration of the master chip is completed, effective pulse signals are periodically sent to the slave chips, and configuration files of the slave chips are sent to the slave chips during the period of the effective pulse signals; the slave chips connected with the master chip are configured after receiving the configuration file, and after any slave chip is configured, the configured slave chip is communicated with the pulse signal transmission interface between the adjacent slave chip, and effective pulse signals sent by the master chip and the configuration file sent by the master chip are transmitted to the next slave chip.

Provided is a display module including a communication interface; and a plurality of driver integrated circuits (ICs), wherein a first driver IC among the plurality of driver ICs is configured to: based on obtaining a driving signal from an external device through the communication interface, provide the driving signal to a second driver IC adjacent to the first driver IC so that the driving signal is sequentially provided to remaining driver ICs among the plurality of driver ICs, and provide, to a second display module among the plurality of display modules, the driving signal based on module connection information including whether the second display module is connected to any one display module among the plurality of display modules by a daisy chain method.

A semiconductor structure may include a first die including: an internal circuit; a first connection pad configured to transmit an electrical signal or power between the internal circuit and an outside of the first die; and dummy patterns electrically insulated from the internal circuit. The semiconductor structure may further include a redistribution layer including: a first redistribution pad electrically connected to the first connection pad; bonding patterns electrically connected to at least one of the dummy patterns; a first testing line connected to one of the bonding patterns, and a second testing line connected to another one of the bonding patterns, wherein the first die is on the redistribution layer, wherein at least one of the dummy patterns and at least two of the bonding patterns form a daisy chain, and wherein the first testing line and the second testing line are respective ends of the daisy chain.

The application provides a parallel battery pack dual-mode adaptive equalization method based on a power daisy chain. The equalization method is applied to an equalization circuit, the equalization circuit comprises an equalization branch and N battery branches, the equalization branch is connected with the battery branches, the N battery branches are connected in parallel, and N is an integer greater than 1. The equalization method comprises the following steps: acquiring the charging and discharging direction, the total current value, the real-time current value of each battery branch and the real-time SOC value of each battery branch, and calculating the average current value and the average SOC value; determining the current difference compensation value of each battery branch according to the charging and discharging direction, the average current value and the real-time current value, determining the SOC difference compensation value of each battery branch according to the charging and discharging direction, the average SOC value and the real-time SOC value; based on the current difference compensation value and the SOC difference compensation value, the total compensation value of each battery branch is calculated; and based on the total compensation value of each battery branch, the equalization branch is controlled to work, so as to equalize the working current of the N battery branches and improve the stability of the working of each battery pack.

The invention discloses a chip testing method and device, a medium and a program product, and relates to the field of chip testing. The chip testing method comprises the steps of generating a to-be-analyzed RBM based on a chip hardware module, a target trigger of the chip hardware module and a target mark field matched with the target trigger; segmenting the to-be-analyzed RBM according to the hierarchical structure associated information corresponding to the target trigger to obtain each chip hardware module code segment; and according to each chip hardware module code segment, creating a system full-module index table, and carrying out code testing based on the system full-module index table and a daisy chain technology. According to the technical scheme provided by the embodiment of the invention, the position of the required analysis module in the RBM and the corresponding code line number can be accurately identified, and the debugging processing efficiency is greatly improved.

A digital communication system comprises a master device and a plurality of slave devices. The master and slave devices are, in operation, communicatively coupled over a communication bus and also coupled together in a daisy-chain configuration using a separate line. A daisy-chain input of a subsequent device is coupled to a daisy-chain output of a previous device in the daisy-chain configuration. Any slave device propagates an interrupt value at their daisy-chain input to their daisy-chain output. In a case of a local interrupt event, a slave device changes its daisy-chain output from an operating value to the interrupt value. The master device, responsive to detecting a change of its daisy-chain input into the interrupt value, triggers a sequential polling of all the slave devices, from the last one to the first one, for feedback collection using the communication bus.

The present disclosure relates to a serial communication network 400 comprising: a plurality of network nodes (402) comprising a primary node (404) and one or more secondary nodes (406a-406d), the plurality of network nodes (402) connected in a daisy chain configuration and configured to communicate according to a first wired communication protocol for serial communication, the first wired communication protocol is an open system protocol; wherein at least one of the network nodes (402) is configured to act as a bridge node (420), and wherein the bridge node (420) comprises communication circuitry configured to: allow communication coupling with the network node (402) and with an external device, receive a first message from the network node (402) according to the first wired communication protocol, and transmit the first message to the external device, and embedding data from the first message into a second message configured according to a second wired communication protocol; and / or receiving a second message configured according to the second wired communication protocol from the external device, and embedding data from the second message into a first message configured according to the first wired communication protocol, the second wired communication protocol being different from the first wired communication protocol.

This application relates to a daisy chain clock distribution system and discloses a circuit (100a) comprising a first power converter (108a) having a first voltage input (110a) and a first output (116a or 117a). The circuit (100a) further comprises a second power converter (108b) having a second voltage input (110b) coupled to the first voltage input (110a), a clock input (112b), and a second output (116b or 117b). A phase shifter (118b) is coupled between the first output (116a or 117a) and the clock input (112b) of the second power converter (108b).

A communication system for an industrial process includes multiple slave modules connected in series with a master controller. The master controller stores a communication schedule that defines an ordered sequence of messages and identifiers associated with each message. The master controller transmits messages downstream through the slave modules to a terminal one of the slave modules. The terminal slave module generates a return message that is transmitted upstream to the master controller. Each slave module receives each downstream message, identifies based on the message identifier whether the message is associated with response information from the slave module, and inserts the response information into corresponding upstream messages.

The application discloses a network security device N+1 cluster hot backup system and method based on a chain type physical cascade, which comprises N main devices and at least one public backup machine, and each device is connected into a daisy chain topology through a special cascade interface. Each device is internally integrated with an encryption module and a physical switching matrix composed of multiple mechanical latching type optical switches. The system defines three modes of service processing, fault source bypass and transparent relay: when a device suddenly fails or is powered off, the optical switch automatically maintains the redirected optical path by relying on the mechanical latching characteristics, and physically bypasses the local port traffic to the cascade channel; after detecting the cascade signal, the downstream normal node directly establishes a straight-through transparent optical path by using the internal optical switch matrix, so that the fault traffic is relayed at the physical layer. The application realizes "physical layer complete unloading" of fault traffic, realizes zero computing power consumption for intermediate nodes, has a forwarding delay of less than 1 mu s, effectively eliminates the performance avalanche problem of a high computing power cluster, and has high availability of power failure self-healing.

The present invention provides a travel detection chip and a key system applying the travel detection chip. The travel detection chip drives a light-emitting diode to emit light, and the light is partially blocked by a light-shielding sheet and then irradiates on a photodiode or a phototransistor. The chip drives the photodiode or the phototransistor and converts the intensity of the light irradiating thereon into a digital value, thereby characterizing the travel of the light-shielding sheet. The travel detection chip communicates with a main control chip through a serial interface and supports expansion and use in the form of a daisy chain. The above features enable the travel detection chip to be efficiently applied to a key detection system, develop a highly efficient and reliable key detection system, and enable arbitrary adjustment of the trigger point of the key.

Embodiments of this application provide a radio frequency apparatus and a control signal transmission method. A specific solution is as follows: A radio frequency transceiver includes a primary control interface, and the primary control interface includes a first clock port and a first data port. Each radio frequency front-end module in at least one radio frequency front-end module includes a secondary control interface, and the secondary control interface includes a second clock port and a second data port. The first clock port is coupled to the second clock port of the at least one radio frequency front-end module through a control bus based on a daisy chain of a linear topology structure, and the first data port is coupled to the second data port of the at least one radio frequency front-end module through the control bus based on a daisy chain of a ring topology structure.

A speaker system comprises a main unit and passive units connected by control voltage signal, reference voltage signal and audio signal connections to form a daisy chain. The main unit generates a control voltage through the control voltage signal connection; a reference voltage through the reference voltage signal connection; and an audio signal through the audio signal connection. The system further comprises a voltage regulation unit between passive units on the reference voltage signal connection; each voltage regulation unit providing a local reference voltage to each passive unit, wherein the local reference voltages to the passive units gradually increase or decrease between subsequent passive units along the daisy chain. Each passive unit comprises: a speaker; a comparator unit for comparing the control voltage to first and second voltage thresholds from the local reference voltage to generate an audio enable signal enabling the speaker unit to play the audio signal.

The invention discloses a multiphase power supply and a control circuit thereof, the multiphase power supply comprises a loop control module and a plurality of logic control modules which are connected to form a daisy chain architecture, and the plurality of logic control modules adopt a time division multiplexing mode to sequentially respond to jump edges of output signals of the loop control module to generate switching control signals of the phases, and time sequence information is transmitted between adjacent logic control modules through phase transmission signals, so that accurate staggered conduction of each phase switch is realized. According to the multi-phase power supply, phase dislocation control among a plurality of power level circuits can be realized only by adopting one control loop, the circuit structure is simple, and circuit design simplification and circuit cost reduction are facilitated.

[Problem] To provide an identification information setting system capable of efficiently setting identification information while reducing cost. [Solution] An identification information setting system 100 includes a wire harness 30. The wire harness 30 is such that a first connector 12 of a BMU 10 and respective second connectors 22 of a plurality of BMS 20 (20-1 to 20-7) are connected in a daisy chain, a portion where the Bit of the ID information is to be set to "0" connects ID terminal pins 12a, 12b, 12c and ID terminal pins 22a, 22b, 22c, and a portion where the ID information is to be set to "1" connects the ID terminal pins 12a, 12b, 12c and PASS terminal pins 22x, 22y, 22z.