3results about How to "Increase memory capacity" patented technology

This application provides a data transmission method, a network interface card (NIC) for a data receiving end, an electronic device, and a storage medium. The data transmission method is applied to the NIC of the data receiving end. The NIC writes data to the host memory of the data receiving end via a bus. The data transmission method includes: if the bus bandwidth resources required for the NIC to write the target data to the host memory exceed the bus bandwidth resources available to the NIC, then writing a portion of the target data to the NIC's NIC buffer; the NIC buffer includes a first memory buffer configured for the NIC based on its on-chip memory and a second memory buffer configured for the NIC based on its onboard memory; the data sending end sends the target data to the data receiving end via remote direct memory access; and a portion of the data is written from the NIC buffer to the host memory. The solution of this application can better avoid data packet loss problems when facing sudden traffic surges.

The utility model relates to the technical field of storage chips, and provides a memory module which comprises at least two main control chips and a dual in-line memory module (DIMM), each main control chip is connected with the DIMM through a first double data rate (DDR) controller interface, and each main control chip is connected with the DIMM through a second DDR controller interface. The CXL interface of one of the at least two main control chips is connected with external equipment through an MCIO connector, and the CXL interface is an MCIO interface. The memory module interacts with the outside through the MCIO interface of one of the at least two main control chips, so that the memory capacity of the memory module is improved.

The utility model relates to the technical field of storage chips, and provides a memory module which comprises a first main control chip, a second main control chip, a first DIMM and a second DIMM, the first main control chip is connected with the first DIMM through a first DDR controller interface, and a CXL interface of the first main control chip is connected with external equipment through a first PCIE interface; the first main control chip is connected with a first DIMM through a first DDR controller interface, the second main control chip is connected with a second DIMM through a second DDR controller interface, a CXL interface of the second main control chip is connected with external equipment through a second PCIE interface, the CXL interface of the first main control chip is a CEM interface, and the CXL interface of the second main control chip is an MCIO interface. According to the memory module, the memory capacity of the memory module is improved.