24 results about "Non-volatile random-access memory" patented technology

Systems and methods include an Information Handling System (IHS) that is adapted to collect boot telemetry in a secure manner. Boot code of the IHS is executed to initiate a boot sequence that includes the generation of boot telemetry. The boot telemetry is collected in a partition of an NVRAM (Non-Volatile Random-Access Memory) of the IHS. When the capacity of the partition of the NVRAM reaches a threshold, the boot telemetry is transmitted from the NVRAM to a security device of an SoC (System-on-Chip) of the IHS for encryption of the boot telemetry. The encrypted boot telemetry is stored in an SSD (Solid-State Drive) of the IHS.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Systems and methods include an Information Handling System (IHS) that is adapted to provide diagnostic boot cycles. Once an IHS is powered, a boot sequence is initiated. During or after booting of the IHS, a request is detected for a diagnostic boot cycle by a requestor, such as by the operating system of the IHS. When a diagnostic boot cycle has been requested, an EC (Embedded Controller) of the IHS is booted in a diagnostic mode to perform a diagnostic test on one or more hardware components of the IHS. The results of the diagnostic test are stored to the NVRAM (Non-Volatile Random-Access Memory) that stores the boot code and that is accessible to the requestor of the diagnostic test once the IHS has been rebooted to a non-diagnostic mode.

Systems and methods for flushing an operation log journal to both ephemeral storage and persistent storage during a shutdown sequence of a virtual storage system to minimize data-loss scenarios are provided. According to one embodiment, the shutdown or reboot scenarios that result in loss of data are minimized by using persistent storage as a backup to ephemeral storage when the scenario results in rehosting of virtual storage system. For example, responsive to an event indicative of an imminent shutdown or reboot of the virtual storage system, vNVRAM memory may be flushed to both ephemeral storage and persistent storage (e.g., a boot disk). In this manner, when the virtual storage system is rehosted after an unplanned shutdown or reboot resulting from an unrecoverable host error (other than an unrecoverable hardware failure), the operation log journal may be recovered from persistent storage to facilitate vNVRAM replay and avoid data loss.

A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.

Systems and methods include an Information Handling System (IHS) that is adapted to provide diagnostic boot cycles. Once an IHS is powered, a boot sequence is initiated. During or after booting of the IHS, a request is detected for a diagnostic boot cycle by a requestor, such as by the operating system of the IHS. When a diagnostic boot cycle has been requested, an EC (Embedded Controller) of the IHS is booted in a diagnostic mode to perform a diagnostic test on one or more hardware components of the IHS. The results of the diagnostic test are stored to the NVRAM (Non-Volatile Random-Access Memory) that stores the boot code and that is accessible to the requestor of the diagnostic test once the IHS has been rebooted to a non-diagnostic mode.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

A reconfigurable inference platform implemented in a system-in-package configuration is provided. The system in the reconfigurable inference platform includes a processor chip, a first memory chip storing a set of executable models for inference engines, and a second memory chip storing weights for a selected executable model. The processor chip has a running processor core, an accelerator core, and a processor-memory interface exposed on a chip-to-chip bonding surface. The first memory chip is, for example, a three-dimensional NAND flash memory. The second memory chip can include a non-volatile random access memory, such as a phase change memory. A direct vertical connection structure, such as a via-to-via connection structure, is provided between the processor chip and the second memory chip.

The present invention provides methods and apparatus for an exclusive-OR (XOR) engine in a random access memory (RAM) device for accelerating cryptographic operations in a processor. For example, an integrated circuit memory device enclosed within a single integrated circuit package may include an XOR engine coupled to memory cells in the RAM device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., a system on a chip (SoC) or a central processing unit (CPU)) may have cryptographic logic that performs cryptographic operations using an XOR operation, which is performed by the XOR engine in the RAM device using data in the RAM device.

A system and method(s) to perform operations for storing gaming data in a non-volatile random-access memory (NVRAM) of a gaming machine and detecting, after the storing, an unrecoverable fault of the gaming machine. The operations further include determining, in response to detecting the unrecoverable fault, that criteria is satisfied for authorization of a partial deletion of the gaming data from the NVRAM. The operations further include determining, in response to determining that the criteria is satisfied, a first portion of the gaming data to retain on the NVRAM, and deleting, after determining the first portion of the gaming data to retain, a second portion of the gaming data without deleting the first portion of the gaming data. The operations can further include booting a game of the gaming machine to a default operational state using at least some of the first portion of the gaming data.

A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.

A processor that executes an inline deduplication pipeline identifies any data segment which is created from data received with a write request from a client, and which is unique relative to data segments stored by the inline deduplication pipeline. The processor logs any segment reference of any data segment which is identified as unique, and any data received from the client and yet to be anchored into any data segment, into persistent memory, which has a lower write latency than any non-volatile random-access memory device that is external to the persistent memory. A hardware accelerator, which has a lower compression latency than the processor, compresses any data segment identified as unique, and stores any compressed data segments into the persistent memory. The client is enabled to provide additional data by the processor acknowledging to the client that the data received from the client is stable in the persistent memory.

An image processing apparatus performs control in such a manner that first processing for storing at least a part of a setting value group receives as a target for import as an operation setting which is retained in a non-volatile random access memory (NVRAM) and second processing for, after the first processing, storing, by overwrite, setting values of a setting item in such a way as to satisfy a security policy, as a part of the operation setting which is retained in the NVRAM are performed as a series of processing operations in import processing.

An indication that power loss protection (PLP) for a non-volatile random access memory (NVRAM) portion of a storage device has failed is received from the storage device. The storage device is marked to indicate the storage device has a PLP failure. A write path to store data at the storage device is modified to avoid storing the data in the NVRAM portion of the storage device that has the PLP failure.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Systems and methods include an Information Handling System (IHS) that is adapted to collect boot telemetry in a secure manner. Boot code of the IHS is executed to initiate a boot sequence that includes the generation of boot telemetry. The boot telemetry is collected in a partition of an NVRAM (Non-Volatile Random-Access Memory) of the IHS. When the capacity of the partition of the NVRAM reaches a threshold, the boot telemetry is transmitted from the NVRAM to a security device of an SoC (System-on-Chip) of the IHS for encryption of the boot telemetry. The encrypted boot telemetry is stored in an SSD (Solid-State Drive) of the IHS.

A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.

Systems and methods for performing journal swapping are provided. In one example, the backing storage used for virtual non-volatile random access memory (vNVRAM) is dynamically switched based on the high-availability (HA) state of an HA pair of nodes of a virtual storage system. By default, in-memory logging may be used for write journaling when the HA pair is operating in a normal HA state. When the HA pair is in an HA degraded state, the write journaling may be performed to local ephemeral storage. This allows the file system of the virtual storage system to run in a more performant configuration most of the time (e.g., during which HA is enabled and healthy). At the same time, the file system has the ability to swap to a less performant but more resilient configuration during planned events (e.g., scheduled maintenance and throughput scaling) in which HA is in a degraded state.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

An indication that power loss protection (PLP) for a non-volatile random access memory (NVRAM) portion of a storage device has failed is received from the storage device. The storage device is marked to indicate the storage device has a PLP failure. A write path to store data at the storage device is modified to avoid storing the data in the NVRAM portion of the storage device that has the PLP failure.

According to a method, a computer-implemented method includes: calibrating a given page in a block using a first calibration scheme (606) by calculating a first number of independent read voltage offset values ​​for the given page. An attempt is made to read the calibrated given page (608), and in response to determining that an error correction code failure occurred during the attempt to read the calibrated given page, the given page in the block is recalibrated using a second calibration scheme (612). The second calibration scheme is configured to calculate a second number of independent read voltage offset values ​​for the given page. An attempt is also made to read the recalibrated given page (614). In response to determining that an error correction code failure did indeed occur during the attempt to read the recalibrated given page, one or more instructions (618) are sent for relocating data stored in the given page.

Systems and methods for performing journal swapping are provided. In one example, the backing storage used for virtual non-volatile random access memory (vNVRAM) is dynamically switched based on the high-availability (HA) state of an HA pair of nodes of a virtual storage system. By default, in-memory logging may be used for write journaling when the HA pair is operating in a normal HA state. When the HA pair is in an HA degraded state, the write journaling may be performed to local ephemeral storage. This allows the file system of the virtual storage system to run in a more performant configuration most of the time (e.g., during which HA is enabled and healthy). At the same time, the file system has the ability to swap to a less performant but more resilient configuration during planned events (e.g., scheduled maintenance and throughput scaling) in which HA is in a degraded state.

A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.