826 results about "Dynamic random-access memory" patented technology

The invention relates to a ZNS SSD-based B + tree index construction method for dynamic placement of cold and hot data. A persistent memory PM, a dynamic random access memory DRAM and a ZNS SSD hard disk are included. The persistent memory PM and the dynamic random access memory DRAM are directly connected with a CPU memory bus and have the capability of being accessed by the CPU according to bytes; internal nodes of the B + tree are stored in a dynamic random access memory (DRAM), and the internal nodes only store index information used for positioning leaf nodes; the pseudo leaf nodes of the B + tree are stored in a persistent memory PM, and only the key index information of the leaf nodes is stored in the pseudo leaf nodes; leaf nodes really storing the key value pairs in the B + tree are divided into hot leaf nodes and cold leaf nodes according to the data access frequency, the hot leaf nodes are stored in a persistent memory PM, and the cold leaf nodes are stored in a ZNS SSD. According to the method, the leaf nodes are quickly positioned by using the DRAM, so that the query time is shortened; hot leaf nodes are stored in the PM, and the real-time service read-write requirement is met; and hot data is stored in a high-speed DRAM and PM, so that the random read-write delay is reduced, and the performance is excellent in scenes such as big data analysis and the like.

The invention provides a method for model training, a host and a storage device. The method includes instructing, by a host device, a graphics processing unit (GPU) to load first intermediate data of a current layer of the model from a dynamic random access memory (DRAM) of a storage device into a memory of the GPU, where the current layer is a layer of the model that is performing computations; and based on the space capacity of the DRAM, notifying, by the host device, the storage device to pre-fetch second intermediate data of the layer to be calculated of the model from the NAND of the storage device to the DRAM of the storage device, the first intermediate data for the current layer is used by the GPU in back propagation of the model to perform computations for the current layer.

The invention relates to the technical field of database management, and discloses a hybrid memory index management method and device, equipment and a medium. Receiving an access request, providing a target index node from the cache when the access request is hit, and reading the target index node from the nonvolatile storage medium when the access request is not hit; writing branch nodes into a high-bandwidth memory cache according to node types, writing leaf nodes into a dynamic random access memory cache, and registering information; when the cache of the high-bandwidth memory meets a first trigger condition, migrating the branch node to the cache of the dynamic random access memory and updating information; and when the cache of the dynamic random access memory meets a second trigger condition, migrating the branch node to the high-bandwidth memory cache, replacing the node and updating the information. According to the method, the node residence position is dynamically adjusted by distinguishing the node types and combining the cache performance, and the index node mapping table is synchronously updated, so that the index request processing performance and the storage resource utilization efficiency are improved.

The invention relates to memory error correction, in particular to an ECC check single-bit error correction system in a DDR (Double Data Rate), which comprises a DRAM (Dynamic Random Access Memory) scanner, periodically performs address read traversal operation on a DDR particle DRAM, timely finds a single-bit error of data in the DDR particle DRAM by inquiring an ECC check state in a DDR controller DDRC, and performs correction processing on the single-bit error, so that the error correction efficiency is improved. The error is prevented from being evolved into an uncorrectable multi-bit error; the DDR controller DDRC is used for converting the AXI interface signal into a corresponding DFI interface signal, outputting the DFI interface signal to a DDR physical layer DDR PHY, carrying out ECC verification on read-write data, and storing an ECC verification result to a register, so that a DRAM scanner inquires an ECC verification state; according to the technical scheme, the defects that in the prior art, the processing speed is low, data errors are not found in time, and more CPU resources are occupied can be effectively overcome.

The invention provides a hierarchical memory and hierarchical storage method and system based on an NVM, and the method comprises the steps: S1, recognizing the access characteristics of memory pages, classifying the memory pages into persistent cold pages, memory access cold pages, persistent hot pages and memory access hot pages, and carrying out the initialization partitioning of the storage space of the NVM based on the classification; s2, dynamically adjusting the distribution of the memory pages between a dynamic random access memory (DRAM) and a non-volatile memory (NVM) by tracking the access heat and persistence heat of the memory pages; and S3, the persistent hot page is persisted to the NVM in the background. According to the method, a hierarchical memory system and a hierarchical storage system are combined, a new migration judgment standard is introduced, and the corresponding page is intelligently migrated to the NVM or the DRAM by predicting whether the page needs to be subjected to persistence operation frequently and predicting the access heat of the page, so that the overhead of the system in the persistence operation and access process is reduced.

The invention discloses a DRAM (Dynamic Random Access Memory) repair method, test equipment, a storage medium and a computer program product, relates to the technical field of memory repair, and discloses the DRAM repair method, which can find and locate potential fault points in the DRAM in real time by dynamically acquiring an error unit address of the DRAM to provide an accurate target for subsequent repair work. And judging whether the error unit is really damaged or not by performing a repeated read-write test on the error unit. According to the invention, when the number of errors reported by the error unit reaches the preset number of times, it is judged that the error unit is damaged, misjudgment caused by a single test error is avoided, meanwhile, invalid or excessive tests on the damaged unit are prevented, and the test time and resources are saved. And finally, through a remapping technology, the service life of the chip is prolonged, the system shutdown risk caused by chip faults is reduced, and the stability of the DRAM is improved.

An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.

The invention relates to the technical field of integrated circuit chips, and discloses a hardware accelerator for realizing attention weighted summation, which comprises a control module, a dynamic random access memory, a ping-pong static random access memory, a data buffer, an input first-in first-out queue module, an output first-in first-out queue module, a processing unit array, an exp module, an adder tree module and a log2 module, according to the hardware accelerator, by designing a special circuit structure, efficient parallel computing can be achieved, memory access delay is reduced, and therefore the computing speed of attention weighted summation is increased.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention discloses a knowledge-driven and data-driven magnaporthe oryzae AVR (Automatic Voltage Regulation) gene RNA (Ribonucleic Acid) secondary structure generator, which is characterized in that an on-chip memory of an ARM (Advanced RISC Machines) chip and an external DRAM (Dynamic Random Access Memory) chip are adopted for respectively storing RNA original data and intermediate results; an FPGA chip is adopted to realize mapping from an RNA sequence to a knowledge graph, and features such as base pairing are fused through LUT; a multi-core AI chip is adopted, an encoder-decoder network is executed in parallel, and knowledge and data are fused to generate a secondary structure; and the VAE-GAN network is executed in a streamlined manner through an AI chip, the quality of the generated structure is evaluated and iteratively optimized, and an accurate RNA secondary structure is generated. The invention further discloses a knowledge-driven and data-driven fused magnaporthe oryzae AVR gene RNA secondary structure prediction method, RNA physicochemical characteristics are utilized, deep learning, transfer learning and knowledge distillation technologies are combined, and the prediction accuracy and operation efficiency are improved.

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

A DRAM is provided including a block with a 3D array of memory cells. The block includes a set of planes stacked along a first axis, including a subset of stacked planes. Each plane of the subset includes a 2D array of memory cells organized in rows and columns. The block has multiple sub-blocks arranged along the second axis with each sub-block containing one column of memory cells of each plane. The DRAM has a plurality of bit lines extending along the first axis in one of the sub-blocks and connected to one memory cell in each plane and includes a plurality of global bit lines connected to the bit lines in each sub-block. Bit line selector transistors of the DRAM connect bit lines to global bit lines and bit line pre-charge transistors of the DRAM connect bit lines to charging lines to charge the bit line.

A memory, a dynamic random access memory, and an electronic device are provided. The memory may be a 3D memory, and includes: a substrate; a plurality of memory cell columns distributed in a first direction perpendicular to the substrate, wherein each memory cell column includes a plurality of memory cell stacked in the first direction; each memory cell includes a transistor and a capacitor; the transistor comprises a semiconductor layer and a gate, and the semiconductor layer includes a first semiconductor layer and a cylindrical second semiconductor layer arranged on the sidewall of the first semiconductor layer. Other structures of the transistor and capacitor have the same definition as those in the description.

The invention belongs to the field of computer system structures and artificial intelligence accelerators, and discloses a software and hardware collaborative heterogeneous storage computing accelerator oriented to full-chip DLRM reasoning. A control domain composed of a static random access memory and an embedded dynamic random access memory, an on-chip storage domain, an in-memory computing domain and an on-chip computing domain are integrated in the same chip, an embedded table is compressed by introducing a hierarchical clustering quantization frame, and a dynamic storage management strategy of access frequency perception is combined. The embedded access path is shortened, and the bandwidth requirement is reduced. According to the method, the reasoning process of the whole set of DLRM can be independently completed, and the memory access overhead in a traditional terminal SoC is remarkably reduced by reducing cross-domain data migration between the calculation unit and the storage unit, so that the model reasoning performance and energy efficiency are improved.

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

The present disclosure provides a three-dimensional DRAM array structure including L layers, M rows, and N columns of DRAM cell structures, each DRAM cell structure including first and second gate transistors having a tubular channel, disposed in a vertical direction and electrically connected in parallel, and a storage capacitor of a tubular structure disposed between the first and second gate transistors in the vertical direction, an inner electrode of the second transistor is connected to the first source / drain of the first and second gate-all-around transistors, and an outer electrode is connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively, and the M rows of DRAM unit structures are divided into M / s row groups.

The invention discloses a storage module, a storage system and an electronic system. The storage module comprises a CXL controller and N heterogeneous dual in-line memory modules, wherein N is greater than 1; the CXL controller comprises a memory driving module, and the memory driving module is connected with N heterogeneous dual in-line memory modules through memory interfaces; the heterogeneous dual in-line memory module comprises a dual in-line interface, a dynamic random access memory, a control unit and a nonvolatile memory; the dynamic random access memory is connected with the memory interface through a dual in-line interface and is used for storing an access command; the control unit is connected with the dual in-line interface, the dynamic random access memory and the nonvolatile memory; the control unit controls data transfer between the dynamic random access memory and the nonvolatile memory according to the access command. The invention provides a scheme capable of realizing both capacity expansion and universal standard interface adaptation.

Disclosed are methods, systems, and apparatuses for semiconductor memory devices (e.g., dynamic random access memory (DRAM)) that include a command / address inversion (CAI) input signal indicating whether command / address inputs to the memory devices are inverted. The CAI input signal may be generated by a memory controller, a registering clock driver (RCD), or other component coupled to the memory devices, and the component may generate the CAI input signal differently for the different memory devices to which the component is coupled. As described herein, the component may dynamically generate the CAI input signal based on the values of the command / address inputs so as to reduce power consumption by the memory devices while retaining signal integrity.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

The invention discloses a vertically-stacked 2T0C DRAM (Dynamic Random Access Memory) unit based on an oxide semiconductor ring gate transistor and a preparation method of the vertically-stacked 2T0C DRAM unit. According to the 2T0C DRAM unit, a first metal interconnection layer, a read transistor layer, a second metal interconnection layer, an isolation layer, a write transistor layer and a third metal interconnection layer are sequentially stacked on a substrate from bottom to top, a read transistor and a write transistor are oxide semiconductor transistors of a vertical ring gate structure, and the two transistors are vertically stacked. Compared with a planar transistor, the DRAM unit has more excellent electrical performance, the working voltage and the characteristic size of the DRAM unit are effectively reduced, and the integration density is improved. By adopting the ring gate structure, the gate control capability can be effectively improved, the same charging current as that of a planar transistor can be realized under a relatively low power supply voltage, and the charge leakage in a holding state is reduced, so that the DRAM gives consideration to both ultra-fast writing and ultra-long data holding time. And meanwhile, the vertically stacked structure reduces the area overhead of the DRAM unit and reduces the wiring difficulty.

The invention discloses a memory access method and electronic equipment, and relates to the technical field of data processing, since a target memory space and a local memory of a processor are used as parallel memory spaces to support the processor, the processor can directly write data into or read data into the target memory space, and the data access efficiency is improved. The solid state disk can directly respond to the memory access request to access the target memory space, so that the data of the processor can be written or read in the solid state disk; compared with the mode that the data needs to be transferred from the local memory of the processor to the dynamic random access memory and then the data of the processor is written into or read from the solid state disk, the time delay for the processor to write into or read from the solid state disk is shorter, and the efficiency is higher. The technical problem of how to reduce the time delay and improve the memory access efficiency is solved, and the technical effects that the time delay of memory access is shorter and the efficiency is higher are achieved.

According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input / output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.SPL

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention provides a three-dimensional DRAM array structure and a semiconductor device including the same. The three-dimensional DRAM array structure comprises L layers, M rows and N columns of DRAM unit structures, each DRAM unit structure comprises a first gate transistor and a second gate transistor which are provided with tubular channels, are sequentially arranged in the vertical direction and are electrically connected in parallel, and a storage capacitor which is provided with a tubular structure, is arranged between the first gate transistor and the second gate transistor in the vertical direction and is electrically connected in parallel with the first gate transistor and the second gate transistor. The inner electrodes are connected to the first source / drain electrodes of the first and second gate-all-around transistors, and the outer electrodes are connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively.

The invention discloses an aging test system and method for a high-speed dynamic random access memory, and the system comprises a test board which is used for bearing at least one to-be-tested memory chip; the controller is used for generating and outputting a test excitation signal conforming to a corresponding memory technical standard; the power management module is used for providing adjustable power supply voltage for the memory chip to be tested according to the control instruction; the communication interface is used for realizing data interaction between the controller and an upper computer and reading configuration information of the memory chip to be tested; wherein a test parameter template library associated with various memory technical standards and product specifications is preset in the controller, and corresponding test parameter templates are automatically matched and loaded according to chip configuration information read by the communication interface so as to adapt to memory chips with different standards. According to the invention, a single hardware platform can be used for universally and adaptively testing various high-speed dynamic random access memories, and the testing efficiency and the equipment utilization rate are remarkably improved.

A dynamic random access memory (DRAM) array has a first portion configured as a data array and a second portion configured as a reference array. The DRAM array includes read bit lines which include a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array. Read circuitry includes a plurality of sensing circuits, each sensing circuit coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines. The plurality of sensing circuits is configured to provide a corresponding bit of an output read value.

A memory controller includes a first storage circuit which stores trained center eyes for a dual data rate (DDR) interface, each trained center eye including a corresponding trained delay value, and a second storage circuit which stores boundary points for the DDR interface. The memory controller includes test circuitry which halts normal operation and uses a corresponding trained delay value of a trained center eye for a first bit lane of the DDR interface as a starting delay value in performing a search for a first boundary point of a data eye margin by repeatedly adjusting a delay between a data signal (DQS) of the first bit lane and a corresponding data strobe signal (DQS) and performing a test with each adjusted delay. The test circuity stores the first boundary point in the second storage circuit, restores the delay back to the corresponding trained delay value, and resumes normal operation.