484 results about "Dynamic random-access memory" patented technology

The invention relates to the technical field of database management, and discloses a hybrid memory index management method and device, equipment and a medium. Receiving an access request, providing a target index node from the cache when the access request is hit, and reading the target index node from the nonvolatile storage medium when the access request is not hit; writing branch nodes into a high-bandwidth memory cache according to node types, writing leaf nodes into a dynamic random access memory cache, and registering information; when the cache of the high-bandwidth memory meets a first trigger condition, migrating the branch node to the cache of the dynamic random access memory and updating information; and when the cache of the dynamic random access memory meets a second trigger condition, migrating the branch node to the high-bandwidth memory cache, replacing the node and updating the information. According to the method, the node residence position is dynamically adjusted by distinguishing the node types and combining the cache performance, and the index node mapping table is synchronously updated, so that the index request processing performance and the storage resource utilization efficiency are improved.

The invention provides a hierarchical memory and hierarchical storage method and system based on an NVM, and the method comprises the steps: S1, recognizing the access characteristics of memory pages, classifying the memory pages into persistent cold pages, memory access cold pages, persistent hot pages and memory access hot pages, and carrying out the initialization partitioning of the storage space of the NVM based on the classification; s2, dynamically adjusting the distribution of the memory pages between a dynamic random access memory (DRAM) and a non-volatile memory (NVM) by tracking the access heat and persistence heat of the memory pages; and S3, the persistent hot page is persisted to the NVM in the background. According to the method, a hierarchical memory system and a hierarchical storage system are combined, a new migration judgment standard is introduced, and the corresponding page is intelligently migrated to the NVM or the DRAM by predicting whether the page needs to be subjected to persistence operation frequently and predicting the access heat of the page, so that the overhead of the system in the persistence operation and access process is reduced.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention belongs to the field of computer system structures and artificial intelligence accelerators, and discloses a software and hardware collaborative heterogeneous storage computing accelerator oriented to full-chip DLRM reasoning. A control domain composed of a static random access memory and an embedded dynamic random access memory, an on-chip storage domain, an in-memory computing domain and an on-chip computing domain are integrated in the same chip, an embedded table is compressed by introducing a hierarchical clustering quantization frame, and a dynamic storage management strategy of access frequency perception is combined. The embedded access path is shortened, and the bandwidth requirement is reduced. According to the method, the reasoning process of the whole set of DLRM can be independently completed, and the memory access overhead in a traditional terminal SoC is remarkably reduced by reducing cross-domain data migration between the calculation unit and the storage unit, so that the model reasoning performance and energy efficiency are improved.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention discloses an aging test system and method for a high-speed dynamic random access memory, and the system comprises a test board which is used for bearing at least one to-be-tested memory chip; the controller is used for generating and outputting a test excitation signal conforming to a corresponding memory technical standard; the power management module is used for providing adjustable power supply voltage for the memory chip to be tested according to the control instruction; the communication interface is used for realizing data interaction between the controller and an upper computer and reading configuration information of the memory chip to be tested; wherein a test parameter template library associated with various memory technical standards and product specifications is preset in the controller, and corresponding test parameter templates are automatically matched and loaded according to chip configuration information read by the communication interface so as to adapt to memory chips with different standards. According to the invention, a single hardware platform can be used for universally and adaptively testing various high-speed dynamic random access memories, and the testing efficiency and the equipment utilization rate are remarkably improved.

A memory controller includes a first storage circuit which stores trained center eyes for a dual data rate (DDR) interface, each trained center eye including a corresponding trained delay value, and a second storage circuit which stores boundary points for the DDR interface. The memory controller includes test circuitry which halts normal operation and uses a corresponding trained delay value of a trained center eye for a first bit lane of the DDR interface as a starting delay value in performing a search for a first boundary point of a data eye margin by repeatedly adjusting a delay between a data signal (DQS) of the first bit lane and a corresponding data strobe signal (DQS) and performing a test with each adjusted delay. The test circuity stores the first boundary point in the second storage circuit, restores the delay back to the corresponding trained delay value, and resumes normal operation.

A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.

The invention relates to the technical field of semiconductor storage, and provides a dynamic random access memory cell, an array and a preparation method thereof. The dynamic random access memory cell comprises a substrate, a dielectric layer, a first electrode layer, M second electrode layers and M isolation layers, the dielectric layer is located between the first electrode layer and the second electrode layer; the dielectric layer is formed by alternately stacking anti-ferroelectric material layers and morphotropic phase boundary ferroelectric material layers; the anti-ferroelectric material layer is used for conducting conversion under the voltage between the first electrode layer and the second electrode layer and providing a nonlinear current-voltage characteristic, so that the storage unit is conducted when the voltage is higher than a first threshold voltage and is turned off when the voltage is lower than a second threshold voltage; the first threshold voltage is greater than the second threshold voltage; the morphotropic phase boundary ferroelectric material layer is used for responding to an electric field to establish a reversible polarization state so as to store data when the anti-ferroelectric material layer is conducted. The invention is used for realizing a self-gating function in a transistor-free gating architecture so as to improve the storage density.

The invention discloses a semiconductor device and a preparation method thereof, and a three-dimensional dynamic random access memory. The semiconductor device comprises a substrate; the stacking structure is arranged on the substrate and comprises a supporting structure and storage units stacked in the first direction; the storage unit comprises a cylindrical first electrode extending along a second direction, the first electrode comprises a first end and a second end along the second direction, the first end is a blind opening, the second end is provided with an opening, the second end is connected with a supporting structure, the supporting structure comprises a first part surrounding a part of the outer surface of the first electrode, the first direction is intersected with the substrate, and the second direction is parallel to the substrate; a first dielectric layer and a second electrode layer, the first dielectric layer covering at least a portion of an inner surface of the first electrode, at least a portion of an outer surface between the first end and the second end, and at least a portion of a surface of the support structure; the second electrode layer covers the first dielectric layer.

The present techniques include vertical cell dynamic random access memory (DRAM) arrays with improved bit line and storage node contact resistivity and self-alignment, and methods of making such arrays. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that a plurality of bit lines intersect source / drain regions of the plurality of channels and a plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes where the bit lines, the storage node contacts, or both are formed of metallized material.

The invention provides a semiconductor stacking structure and a preparation method thereof, a high-bandwidth memory and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor stacked structure comprises a plurality of stacked semiconductor structures, each semiconductor structure comprises a storage unit layer and a bonding layer, the bonding layer is arranged on the surface, facing the adjacent semiconductor structure, of the storage unit layer, and the bonding layer is coupled to the storage unit layer. Wherein two adjacent semiconductor structures are in bonding connection through a bonding layer. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

The invention provides a method for manufacturing a three-dimensional DRAM (Dynamic Random Access Memory) array structure. The method comprises the steps that a plurality of stacked sub-arrays and a plurality of second isolation layers are sequentially formed on a circuit substrate, the step of forming the stacked sub-arrays comprises the substeps that first isolation layers and stacked layers are alternately stacked, and each stacked layer comprises a first conductive layer, a sacrificial layer and a second conductive layer; bit line holes penetrating through the first isolation layer and the lamination layer are formed, and the area of each bit line hole in the lamination layer is larger than that in the first isolation layer; forming a gate dielectric layer, a semiconductor material layer and an isolation medium in each bit line hole; forming a hole penetrating through the isolation medium, and filling the hole with a first conductive material; forming a common electrode groove which extends along the first horizontal direction and penetrates through the first isolation layer and the lamination layer; removing the sacrificial layer and a part of gate dielectric layer corresponding to the sacrificial layer in the common electrode groove; and conformally forming a capacitor dielectric layer on the inner surface of each common electrode groove, and filling the residual space of the common electrode groove with a second conductive material.

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor structure comprises a plurality of transistors arranged at intervals, a dielectric layer, a first connection structure and a conductive layer. The dielectric layer is arranged on one side of the well structures of the plurality of transistors, and a part of the dielectric layer extends between two adjacent transistors. The first connecting structure is arranged on the dielectric layer, is close to one side, far away from the transistor, of the dielectric layer, and is connected with a well structure of the transistor. The conductive layer is arranged on one side of the dielectric layer away from the transistor. The first connection structure is connected with the conductive layer. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

Systems and methods for multi-source hidden-state fusion on edge devices. A processing system executes a state-space model, accesses a vector database in dynamic random-access memory, and maintains model state in on-chip static random-access memory. The system processes document chunks to form hidden states and computes a key for each chunk. Tuples pairing each key with a hidden state are stored in the database. For a received query, the system computes a query key and retrieves tuples by nearest-neighbor search using the stored keys and the query key. A fusion function computes a fused hidden state across the retrieved hidden states. The fused hidden state is loaded as the initialization state. The model processes the query tokens from that state and generates answer tokens as a function of the fused state and the query tokens.

A data processing method includes obtaining an instruction that carries a target virtual address and a target process identification; querying a mapping table based on the target virtual address and the target process identification, where the mapping table includes a correspondence between at least one virtual address, at least one process identification, and at least one physical address; and if a first physical address corresponding to the target virtual address and the target process identification exists in the mapping table, and the first physical address is included in a physical address range corresponding to the storage class memory, prefetching, to the dynamic random access memory, data of a target memory page corresponding to the first physical address.

The present disclosure relates to the technical field of microelectronics, and in particular to a capacitor-less dynamic random access memory structure and a manufacturing method therefor. The structure comprises: a low-leakage transistor and a vertical complementary field effect transistor, wherein a drain of the low-leakage transistor is connected to a common gate of the vertical complementary field effect transistor; and drains of P-type and N-type transistors of the vertical complementary field effect transistor are connected to each other, a source of the P-type transistor is connected to a power supply end, and a source of the N-type transistor is connected to a ground wire.

Methods of forming DRAM bit lines to improve line edge roughness (LER) and reduce resistance are described. The methods include the steps of implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size, the second grain size being smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and the amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors arranged in a honeycomb pattern to maximize available capacitor footprint on top of the memory array. Bit lines may partially intersect bottom source / drain regions of two adjacent rows of the vertical transistors, where the rows may be offset based on the honeycomb pattern. The word line may have a varying width that increases as the word line surrounds the gate region of the transistor and decreases between adjacent transistors. The transistor stages may each be individually and incrementally formed, first completing the bottom source / drain region and the bit line, then the gate region and the word line, and finally the top source / drain region and the capacitor.

The invention discloses a three-dimensional dynamic random access memory and a manufacturing method thereof, relates to the technical field of memories, and aims to improve the storage density of the dynamic random access memory. The three-dimensional dynamic random access memory comprises a plurality of memory units distributed in a three-dimensional array, and a medium structure used for separating different memory units. Each storage unit comprises a transistor and a capacitor. The source electrode and the drain electrode are arranged on the two sides of the channel layer in the length direction respectively and cover the inner wall of the notch. The gate dielectric layer is located between the gate and the channel layer, between the gate and the source and between the gate and the drain. The capacitor comprises a first electrode and a second electrode which are distributed at an interval, and a dielectric layer located between the first electrode and the second electrode. One of a source electrode and a drain electrode included in the transistor is shared with the first electrode of the capacitor, and the other one is integrally continuous with the source electrode or the drain electrode located on the same side in the other transistors located on the same column in the first direction.

The invention relates to a configuration method and device of a dynamic random access memory, electronic equipment and a storage medium. The method comprises the following steps: controlling the dynamic random access memory to perform one initialization operation in a first initialization operation or a second initialization operation; wherein the first initialization operation is used for initializing a dynamic random access memory in a default connection mode, and the second initialization operation is used for initializing a dynamic random access memory in an exchange connection mode; judging whether the initialization operation is successful or not; and under the condition that the initialization operation is not successful, controlling the dynamic random access memory to perform the other initialization operation in the first initialization operation or the second initialization operation. Through the technical scheme provided by the invention, the dynamic random access memory is automatically configured through the initialization operation adaptive to the current hardware connection mode of the dynamic random access memory, and the technical problem that software is relatively inconvenient to manually configure for each integrated product is solved.

A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. Each DRAM cell unit includes a respective transistor, a respective capacitor and a respective bridge structure. Each bridge structure is configured to electrically couple the respective transistor to the respective capacitor. Each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate.

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor structure includes a memory array and a recess. The storage array comprises a bit line, a transistor and a capacitor unit which are arranged in a stacked mode, the transistor is located between the bit line and the capacitor unit, and the transistor is connected with the bit line and the capacitor unit. The groove penetrates through the memory array along the stacking direction, and the bit line is exposed out of the groove. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

A solid state device (SSD) includes two data storage controllers, each connected to a corresponding set of NAND chips. The SSD includes a Universal Serial Bus (USB)-C socket for receiving a USB-C plug in one of two mating orientations. One lane of the USB-C socket is connected to the first data storage controller. The second lane is connected to the second data storage controller. The two lanes are used for concurrent communications with a host, with lane communication protocols depending upon the mating orientation. In a first mating orientation, the first lane communication protocol may be USB 10 Gbps and the second lane communication protocol may be USB 2.0. In the second mating orientation, the protocols are reversed. The host thereby has concurrent access to both sets of NAND chips. Similar features are described for use with volatile memory devices such as dynamic random access memory (DRAM) devices.