68 results about "Dynamic random-access memory" patented technology

A solid state device (SSD) includes two data storage controllers, each connected to a corresponding set of NAND chips. The SSD includes a Universal Serial Bus (USB)-C socket for receiving a USB-C plug in one of two mating orientations. One lane of the USB-C socket is connected to the first data storage controller. The second lane is connected to the second data storage controller. The two lanes are used for concurrent communications with a host, with lane communication protocols depending upon the mating orientation. In a first mating orientation, the first lane communication protocol may be USB 10 Gbps and the second lane communication protocol may be USB 2.0. In the second mating orientation, the protocols are reversed. The host thereby has concurrent access to both sets of NAND chips. Similar features are described for use with volatile memory devices such as dynamic random access memory (DRAM) devices.

Apparatuses, systems, and techniques are to transfer data based, at least in part, on a computational graph. In at least one embodiment, a processor causes a compiler to generate instructions to prefetch one or more data values from dynamic random access memory (DRAM) into an in-processor cache based, at least in part, on a computational graph.

A memory controller for a dynamic random-access memory (DRAM) is disclosed. The memory controller includes control circuitry that is configured to transmit, via a command / address (CA) interface, a command to place the DRAM into a mode that causes the DRAM to perform a self-refresh operation. The memory controller is configured to receive address information recorded by the DRAM while operating in a test-during-self-refresh mode. The address information identifies memory cells internally read and evaluated for an error by the DRAM during the self-refresh operation.

A stacked die device includes a first master dynamic random access memory (DRAM) die having a first command interface to receive first commands and a first data interface to transfer first data. A second master DRAM die is stacked with the first master DRAM die and includes a second command interface to receive second commands that are independent of the first commands, and a second data interface to transfer second data that is independent of the first data. The first and second master DRAM die form respective portions of first and second memory channels. A third DRAM die is stacked with the first and second master DRAM die and includes a first selectively-enabled data input / output (I / O) circuit coupled to the first master DRAM die. A fourth DRAM die is stacked with the other die, and includes a second selectively-enabled data input / output (I / O) circuit coupled to the second master DRAM die.

According to various embodiments, an electronic device for performing data mapping by performing an operation of a CNN model with low power comprises: a communication interface; a processor; and a memory including a dynamic random access memory (DRAM) in which multiple full multipliers for, when executed by the processor, causing the processor to perform multi-operations enabling simultaneously performing multiple operations, while performing at least one operation related to the CNN model, and a control bit and a 2:1 selector for deactivating a second multiplier that is not required for an operation other than multiple first multipliers required for the operation are stored, wherein the at least one operation comprises the operations of: in a case where at least one input data is acquired from an external electronic device through the communication interface, when a kernel size of the at least one input data is determined to have a value greater than or equal to a preset threshold size value, automatically dividing the kernel size of the at least one input data according to a set size; when the kernel size of the at least one input data has a value smaller than or equal to the threshold size value or is automatically divided, inputting the at least one input data to at least one stage pre-stored in the memory; determining the number of the first multipliers required for a multiplication-accumulation (MAC) operation of the at least one input data in the stage, and when the number of the first multipliers is determined to be equal to or less than the number of the full multipliers, driving the control bit and the 2:1 selector to deactivate the second multiplier; and receiving a global buffer including multiple weight values from each of multiple sub-processors through the communication interface, and inputting and mapping the at least one input data to the first multipliers.

A dynamic random access memory (DRAM) device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh period. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh period, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh period. Transmit circuitry transmits the value to the memory controller.

An example operation includes one or more of receiving a request for access to data stored within a chip stack that comprises a plurality of dynamic random-access memory (DRAM) chips which are communicably coupled to a substrate, and a NOT AND (NAND) flash memory chip which is communicably coupled to the plurality of DRAM chips, and accessing the data within the chip stack based on the plurality of DRAM chips and the NAND flash memory chip within the chip stack.

This invention proposes a large-scale language model inference system and method. The large-scale language model inference system includes a first computing unit. The first computing unit is used to set a model file to be inferred and select an inference framework for inferring the large-scale language model based on the model file. The first computing unit detects hardware performance information of multiple dynamic random access memories (DRAMs) and multiple video random access memories (VRAMs) and obtains multiple model loading parameters. The first computing unit allocates model data of the large-scale language model to at least one of the DRAMs and VRAMs based on the hardware performance information and the multiple model loading parameters. The first computing unit operates at least one of the DRAMs and VRAMs to perform inference operations on the large-scale language model based on at least one inference output filtering parameter.

This application is directed to accessing data in a memory system of an electronic system. The memory system a storage-side DRAM and one or more memory channels. The memory system receives a memory access request for target data stored in the memory system, and the memory access request includes a target virtual address of the target data. In response to the memory access request, the memory system searches a page table of the storage-side dynamic random-access memory (DRAM) for a target physical address mapped to the target virtual address of the target data. The page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses of the storage-side DRAM. Based on a search result, the memory system extracts the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address.

This invention discloses a dynamic random access memory (DRAM) and its manufacturing method, relating to the field of memory technology, to reduce the parasitic capacitance of memory cells. The DRAM includes a substrate and a plurality of memory cells. Each memory cell includes a first transistor and a second transistor disposed along the thickness direction of the substrate, with the second transistor located on the first transistor. The first transistor includes a first stacked structure, a first channel layer, a first gate dielectric layer, and a first gate. The first channel layer covers a second isolation layer and the inner wall of a first opening, the first gate dielectric layer is located on the first channel layer, and the first gate is located within a first via formed by the first gate dielectric layer. The second transistor includes a second stacked structure, a second channel layer, a second gate dielectric layer, and a second gate. The second channel layer covers a third conductive layer and the inner wall of a second opening, the second gate dielectric layer is located on the second channel layer, and the second gate is located at least within a second via formed by the second gate dielectric layer.

The present disclosure provides a method for model training, a host, and a storage apparatus. The method may include instructing, by a host apparatus to a graphics processing unit (GPU), to load first intermediate data of a current layer of a model from a dynamic random access memory (DRAM) of a storage apparatus into a memory of the GPU, wherein the current layer is a layer of the model for which computation is being performed; and notifying, the host apparatus to the storage apparatus, to prefetch second intermediate data of a layer of the model to be computed from NAND of the storage apparatus into the DRAM of the storage apparatus based on a space capacity of the DRAM, wherein the first intermediate data of the current layer is used by the GPU in backward propagation of the model to perform the computation for the current layer.

Memory device architectures including integrated static random access memory based tag circuitry and dynamic random access memory cells are discussed related to improving density and device performance Such memory device architectures include vertically aligned dynamic random access memory cells and memory tag circuitry aligned and implemented within the same monolithic integrated circuit die or on stacked interconnected monolithic integrated circuit dies.

A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.

Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. The multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

A solid state device (SSD) includes two data storage controllers, each connected to a corresponding set of NAND chips. A first controller controls data transference between a first set of NAND chips and a host via a pair of full-duplex Tx / Rx lanes of a Universal Serial Bus (USB)-C connector. A second controller controls concurrent data transference between a second set of NAND chips and the host via a half-duplex D+ / D− lane of the USB-C connector. In this manner, 20 Gigabits-per-second (Gbps) communications may be achieved using USB 3.2 Gen 2×2 while another 480 Megabits-per-second (Mbps) communication may be achieved using USB 2.0. The host may be configured to present the two sets of NAND chips to the user as two separate memory spaces, designated as separate drives. Similar features are described for use with volatile memory such as dynamic random access memory (DRAM) devices.

A high bandwidth memory is provided. The high bandwidth memory includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.

The application provides a multi-core chip, an attention processing method and an electronic device. The chip includes a plurality of core particles packaged together, each core particle including a dynamic random access memory, a static random access memory and a computing engine. The computing engine is used to identify the identity of the core particle in the outer loop and load the corresponding local query matrix block. In the inner loop, the key matrix block and the value matrix block in the target core particle are loaded, the attention calculation is performed, and the local calculation result is accumulated to obtain the global result. After the end of the inner loop, the global result is written back to the dynamic random access memory. The application realizes the expansion of attention calculation from a single core particle to a multi-core chip level, aggregates hardware resources of multiple core particles, and improves the calculation efficiency of the attention mechanism in a long context scenario and the utilization rate of chip hardware resources.

This invention proposes a distributed computing system and a distributed computing method. The distributed computing system includes a first computing device and a second computing device. The second computing device is connected to the first computing device via a cable. The distributed computing module calculates the buffer size required by the model to determine a memory usage strategy. The distributed computing module splits the model to generate multiple sub-models. The distributed computing module allocates the multiple sub-models to multiple display memories of the first and second computing devices according to the memory usage strategy, and selectively uses at least one of the multiple dynamic random access memories of the first and second computing devices to distribute the model training.

Provided is a storage device, memory processor, and an operating method thereof. More specifically, provided is an operating method of a storage device including acquiring quality of service (QoS) information, obtaining a read request or write request for data in the NVM from a host, and allocating a logical-to-physical (L2P) slot of a plurality of L2P slots including L2P mapping information corresponding to the data to at least one namespace among a plurality of namespaces of a dynamic random-access memory (DRAM) based on the QoS information.

A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

The present disclosure relates to a semiconductor structure for a 3D DRAM comprising one 1T1C memory cell architecture and vertical bit lines. The semiconductor structure comprises a stack of semiconductor layers and dielectric layers alternatingly arranged along a first axis. Further, a first and second pillar of memory cells arranged displaced along a second axis and extending along the first axis through the stack. Each memory cell comprises a part of one of the semiconductor layers, and one transistor structure and one capacitor with a semiconductor channel and a metal gate that at least partly surrounds the semiconductor channel. The metal gates of memory cells in the same pillar are isolated from each other, and metal gates of memory cells that comprise parts of the same semiconductor layer form an integral metal structure.

Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). An example DRAM device may include a plurality of pillars extending from a base of a substrate, a gate formed around the plurality of pillars, and a buried bitline formed within the base, wherein an upper surface of the buried bitline is recessed below an upper surface of the base. The DRAM device may further include a bottom source / drain formed beneath the plurality of pillars, and a contact formed in the bottom source / drain, between the plurality of pillars.

This technology includes a vertical-cell dynamic random access memory (DRAM) array with improved resistivity and self-alignment of bit lines and storage node contacts, and a method for fabricating such an array. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending vertically, substantially orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. Furthermore, the array includes a configuration in which the bit lines, storage node contacts, or both are formed from a metallized material.

Embodiments disclosed herein include ultra high bandwidth memory (HBM) with backend transistors. In an example, a memory structure includes a package substrate. A base die is coupled to the package substrate and a memory die stack is coupled to the base die, or a memory die stack is coupled to the package substrate. Each memory die in the die stack includes one transistor one capacitor (1T1C) backend dynamic random access memory (DRAM).

This invention provides a hafnium-based MPB high-k capacitor based on island-shaped metal layers, its fabrication method, and a dynamic random access memory (DRAM). The method includes: providing a substrate; sequentially forming a lower electrode and a first hafnium-based MPB layer on the substrate; forming a discontinuous island-shaped metal structure on the first hafnium-based MPB layer; sequentially forming a second hafnium-based MPB layer and an upper electrode on the island-shaped metal structure; and performing rapid thermal annealing to crystallize the hafnium-based MPB material in the first and second hafnium-based MPB layers. By forming island-shaped metal layers to constitute a five-layer superlattice composite dielectric structure, active control of the MPB dielectric performance is achieved. This not only suppresses charged defects such as mobile oxygen vacancies in the MPB dielectric but also suppresses random phase transitions in the MPB dielectric caused by temperature or electric field changes, improving material parameter consistency, thereby stabilizing the dielectric response and improving temperature / bias stability. This solves the problem of how to fabricate reliable storage capacitors with high-k dielectric properties.

Provided in the present invention is a capacitor-less non-volatile dynamic memory, comprising: a first transistor and a second transistor, wherein the first transistor is a vertical channel transistor, and the second transistor is a ferroelectric transistor; and the second transistor is located above the first transistor. In the 2T0C non-volatile dynamic memory provided in the present invention, one of the transistors is a ferroelectric transistor, such that the non-volatile dynamic random access memory obtained by introducing a ferroelectric material can solve the problems of storage density and energy consumption of a current dynamic random access memory, and can realize high-density and high-efficiency storage. In addition, in the manufacturing process for the other vertical channel transistor, a gate surrounding a channel is formed by means of metal induction, so that the gate control capability is stronger. The present invention realizes wafer-level three-dimensional integration, and has a higher integration density and lower costs compared with conventional semiconductor processes, thereby achieving wide application prospects.

The embodiment of the present disclosure provides a processor and a manufacturing method thereof, wherein the processor comprises: a first semiconductor structure, the first semiconductor structure comprising a core, a first-level cache, and a second-level cache; a second semiconductor structure, the second semiconductor structure comprising a third-level cache to an Nth-level cache; different levels of caches in the third-level cache to the Nth-level cache comprise different parts of a dynamic random access memory; wherein N is a positive integer greater than three; and a bonding layer, the bonding layer being located between the first semiconductor structure and the second semiconductor structure and used for electrically connecting the first semiconductor structure and the second semiconductor structure.

The present disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips. The semiconductor structure comprises a plurality of channel structures and a plurality of word lines. The plurality of channel structures are arranged in multiple rows and multiple columns, wherein the plurality of channel structures in one row of channel structures are arranged at intervals along a first direction, and the multiple rows of channel structures are arranged at intervals along a second direction. The word lines extend along the first direction, the plurality of word lines are arranged at intervals along the second direction, and each word line is coupled with one row of channel structures, and at least part of the word lines extend into the channel structures. The plurality of word lines comprise a first word line, a second word line and a third word line, the second word line is located between the first word line and the third word line, the first word line and the third word line are coupled with two adjacent channel structures in the same column of channel structures respectively, and the second word line is coupled with another column of channel structures. The above semiconductor structure is applied in a dynamic random access memory to realize data reading and writing operations.

The application discloses a dynamic random storage array and a control method thereof, and belongs to the technical field of microelectronics and integrated circuits, and comprises a plurality of storage units, each of which comprises a first transistor, a second transistor, a word line, a bit line and a ground wire, wherein the gate of the first transistor is connected with the word line, the source / drain electrode of the first transistor is connected with the bit line, the gate of the second transistor is connected with the drain / source electrode of the first transistor, the gate of the second transistor serves as a storage node and stores charge information, the source / drain electrode of the second transistor and the source / drain electrode of the first transistor are connected with the same bit line, the drain / source electrode of the second transistor is connected with the ground wire, and the word line and the bit line are used for controlling the writing and reading of data of the storage node, wherein the second transistor is a depletion transistor. According to the application, the depletion transistor is in an on state when the gate voltage is zero, so that the current in the bit line is small when data is written, and the power consumption of the writing operation is reduced.