Eureka-AI is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Eureka AI

179results about How to "Improve system reliability" patented technology

Handling of hard errors in a cache of a data processing apparatus

A data processing apparatus and method are provided for handling hard errors. The data processing apparatus comprises processing circuitry for performing data processing operations, and cache storage having a plurality of cache records for storing data values for access by the processing circuitry when performing the data processing operations. A cache record error storage having at least one error record, and a hard error storage having at least one hard error record, are provided for keeping track of errors detected when accessing cache records of the cache storage. In particular, when an error is first detected for a particular cache record, one of the error records in the cache record error storage is allocated to store a cache record identifier for that cache record, and an associated count value is set to a first value. Further, if an error is detected when accessing a cache record, a correction operation is performed in respect of that currently accessed cache record, and access to that currently accessed cache record is then re-performed. Each time an error is detected for subsequent accesses to that cache record, the count value is incremented, and each time an error is not detected when that cache record is accessed, the count value is decremented. If the count value reaches a predetermined threshold value, then the cache record identifier is moved from the cache record error storage to an error record of the hard error storage. Any cache record whose cache record identifier is stored in the hard error storage is logically excluded from the plurality of cache records of the cache storage for the purposes of subsequent operation of the cache storage. Such an approach provides a hardware mechanism that automatically identifies and corrects hard and soft errors, but only masks from further use those cache records affected by hard errors.

Transmission of urgent messages in telemetry system

A radio transmission system including many radio transmitters using frequency hopping carriers to intermittently transmit very short messages indicative of status of stimuli associated with the transmitters. The transmitters transmit transmissions independently of a receiver receiving the transmissions and independent of each other. In operation, radio transmitters transmit messages at varying frequencies at time intervals that can be varied as well. The frequency and time intervals are varied according to patterns that can be determined individually for each transmitter. A receiver holds data indicative of the future transmission frequency and time for each transmitter and updates the data based on the time and the content of the received messages. In addition, a simple method is provided to generate a very large number of orthogonal frequency-time hopping sequences that are individual for each transmitter and based on the transmitter ID. The problem of transmission of urgent messages is solved by transmitting urgent transmissions at transmission opportunities having precise time and frequencies that, advantageously, are in relations with the routine transmissions. The problem of power-up synchronization in such system is solved by rapidly transmitting, at transmission opportunities, a sequence of synchronization transmissions that carry information about the time and the frequency of a future routine transmission.

Suspension type six-degree-of-freedom micro-gravity environment simulating system

The invention discloses a suspension type six-degree-of-freedom micro-gravity environment simulating system. The suspension type six-degree-of-freedom micro-gravity environment simulating system comprises a simulation spacecraft, a space three-dimensional driving follow-up unit, an attitude follow-up and fixing unit, a buffering and sensor mounting unit and a control unit. The space three-dimensional driving follow-up unit follows the position motion of the spacecraft and compensates for the gravity borne by the spacecraft. The attitude follow-up and fixing unit can follow the attitude adjusting motion of the spacecraft and can keep the existing attitude of the spacecraft after the attitude of the spacecraft is adjusted. The buffering and sensor mounting unit comprises a buffering module and a sensor mounting measurement module. By means of the buffering module, the gravity compensation precision is improved for the system based on the property that force on a spring cannot change instantly. The sensor mounting measurement module comprises a wireless tilt angle sensor and a tension sensor, and closed-loop control over the system is achieved. The control unit controls motion of a servo motor according to the measurement results of the sensors, and follows motion of the spacecraft actively.

Online detection fault-tolerance system of FPGA (Field programmable Gate Array) digital sequential circuit of SRAM (Static Random Access Memory) type and method

The invention discloses an online detection fault-tolerance system of an FPGA (Field programmable Gate Array) digital sequential circuit of an SRAM (Static Random Access Memory) type and a method. The method comprises the following steps of: respectively dividing the sequential circuit for detection and fault-tolerance into combinational logics and sequential logics; respectively carrying out triplication redundancy and majority voting to the combinational logics and the sequential logics to cover failures and obtain a redundant sequential circuit, dividing the redundant sequential circuit in the physical structure into three independent dynamic reconstruction regions and a static region and macro-processing the communication between the dynamic reconstruction regions and the static region with a bus; and respectively physically restraining the three redundant combinational logics to the three independent dynamic reconstruction regions and physically restraining the three redundant sequential logics to the static region. Compared with the prior art, the invention combines two-stage redundancy and reconfiguration technologies, not only can improve the system reliability, but also can reduce implementation resources and decrease the power consumption of a designed circuit.
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products