617 results about "Control store" patented technology

Providing scalable and reliable container-based storage services, including: deploying a containerized storage controller on a first node among of plurality of nodes operable to support execution of the containerized storage controller; associating a dataset stored in backing storage accessible by the first node with one or more virtualized volumes presented by the containerized storage controller; and providing, by the containerized storage controller to one or more client hosts, a set of storage services for the one or more virtualized volumes.

A memory apparatus includes a memory device, a memory controller and a memory physical layer interface. The memory physical layer interface comprises a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit. The tap reset circuit generates a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset a DFE taps of the multi-tap DFE receiver during the gap interval between the read bursts. The tap reset circuit resets the plurality of DFE taps using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval. The tap reset circuit resets the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval. The second predetermined interval is greater than the first predetermined interval.

The invention relates to the technical field of digital storage, and provides a method and a system for recovering long-term storage failure of a mobile terminal, through the design of a built-in independent power supply, a startup disk can still supply power continuously when the mobile terminal is in a power-off state, and the limitation of traditional OTG (On-The-Go) equipment is broken through. The read-write state of the data block of the flash memory chip is automatically monitored through the storage controller, and a health report is generated in real time; and when the early warning data block is detected, a bidirectional communication protocol is triggered. In a data backup link, a boot disk adopts a hierarchical check mechanism to generate CRC codes for each data block for centralized storage, and meanwhile, an overall SHA-256 code is calculated and double-end synchronization is performed. And in the recovery stage, the backup integrity is ensured through SHA-256 code comparison, then the data accuracy is verified block by block through CRC codes, and finally, the backup file is automatically migrated to the nonvolatile partition. The seamless closed loop from fault detection to data recovery is realized aiming at the system guidance problem after long-term storage of the equipment.

The invention relates to the technical field of microelectronics, and discloses a three-dimensional stacked near-memory computing architecture, a chip and a data access method. The memory device comprises at least one computing chip layer and at least one memory chip layer which are stacked along a first direction, a plurality of vertical interconnection channels extending along the first direction; the memory chip layer comprises a plurality of memory banks; the computing chip layer comprises a plurality of computing cluster units; the computing cluster unit comprises at least one storage controller; and the storage controller is connected with at least one of the plurality of storage banks through the vertical interconnection channel and is used for managing data in the correspondingly connected storage banks. The problems that in a three-dimensional stacking computing architecture, storage access delay is high, and the bandwidth expansion capacity is limited are solved.

An operating method of a storage controller includes, storing data and a source type of the data in a cache memory, when a cache hit occurs, determining a source type of data corresponding to the cache hit and updating a hit count corresponding to the determined source type among a plurality of hit counts, determining a source type with a dominant hit rate among a plurality of source types based on the plurality of hit counts, operating in a first mode when a result of the determining indicates that the source type with the dominant hit rate is a first type, and operating in a second mode when the result of the determining indicates that the source type with the dominant hit rate is a second type.

This application is directed to resource management in a storage system that includes a non-volatile memory and a collection of resources having one or more processing cores. The storage system allocates a first subset of resources to process queues of I / O access operations requested by a host device. The first subset of resources includes a storage controller corresponding to a subset of processing cores. The storage system obtains a first request for adjusting resource allocation of the storage device, and the first request includes a target performance requirement for processing the queues of I / O access operations. The storage system determines that the target performance requirement can be satisfied by allocation of at least a target subset of resources. In response to the first request and based on the target subset of resources, a second subset of resources is allocated for processing the one or more queues of I / O access operations.

A storage device includes a memory device and a memory controller to control the memory device by communicating with the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel and each of the plurality of memory chips includes a transmission driver and an adaptive body bias generator. A target memory chip selected by the memory controller, among the plurality of memory chips, includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver in a write mode in which the target memory chip receives a write data from the memory controller and applies a second body bias in a read mode in which the target memory chip transmits a read data to the memory controller.

Apparatuses and techniques for reporting multiple events associated with mitigating usage-based disturbance are described. In an example aspect, a memory device can report to a memory controller various events associated with mitigating usage-based disturbance. This includes notifying the memory controller of events associated with a first event category and alerting the memory controller of events associated with a second event category. For events associated with the first event category, there can be a smaller risk of an alert condition occurring if the memory controller does not take action. For events associated with the second event category, there can be a larger risk of an alert condition occurring if the memory controller does not take action. By reporting these multiple events by category, the memory device empowers the memory controller to take appropriate action and efficiently manage available resources for mitigating usage-based-disturbance.

A storage device includes a memory device that includes a plurality of memory cells, and a memory controller that controls the memory device. The memory device includes a memory cell array that includes the plurality of memory cells, a control logic circuit that writes data to the memory cell array or reads data from the memory cell array in response to a command received from the memory controller, and a page buffer that stores sensing data sensed from the plurality of memory cells. The control logic circuit includes an error detecting circuit that detects an error of first data stored in first memory cells of the memory cell array, and the control logic circuit writes the first data to second memory cells of the memory cell array, based on an error comparison result obtained by comparing the error of the first data with a preset value.

A technique for recovering data following a failure of a first availability zone (AZ) of a cloud-based system includes creating a plurality of temporary instances in a second AZ of the cloud-based system. The technique further includes copying, by the plurality of temporary instances, recovery data from multiple cloud-based snapshots to a plurality of local volumes of the second AZ such that the temporary instances of the plurality of temporary instances copy respective portions of the recovery data in parallel. The technique still further attaching the plurality of local volumes to a storage-controller instance running in the second AZ.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.

Based on the WAF (Write Amplification Factor) value, the efficiency of writing data to non-volatile memory is improved, extending the lifespan of the non-volatile memory. [Solution] The image forming apparatus includes an image forming unit, a non-volatile memory (flash memory) for storing data, a memory controller for controlling the writing of data to the non-volatile memory, a storage device (SSD) including a storage unit that holds size information of the first data written to the non-volatile memory by the memory controller, and a main controller that outputs the second data to be written to the non-volatile memory to the memory controller. The main controller suspends the writing of the second data to the non-volatile memory if the size of the second data to be written to the non-volatile memory is less than or equal to a preset minimum size, and writes the two or more suspended second data to the non-volatile memory as a single second data if the combined size exceeds the minimum size.

A storage controller (for example, a storage control unit 123) can execute log creation processing of, when a write request is processed and control information or cache data is updated, adding a header to the updated data to create an update log and storing the update log in a log buffer. In the log creation processing when first-type control information (normal control information) is updated, the storage controller adds a log header to each piece of updated first-type control information to create an update log (normal log 132), and in the log creation processing when second-type control information (cache directory) is updated, the storage controller creates one consolidated log (consolidated log 137) as an update log related to a plurality of pieces of second-type control information.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

To provide a system, method and device for managing error corrections for a data storage system.SOLUTION: A data storage system 400 includes a data storage device 410 comprising at least one memory 412 and a memory controller including at least one first error correction code (ECC) decoder 414. The memory controller reads data from the at least one memory, executes an ECC test on the read-out data using the at least one first ECC decoder, and transmits the read-out data to an external device having at least one second ECC decoder for decoding the read-out data in response to a determination that the read-out data has not passed the ECC test. The external device 420 is located external of the data storage device. A second ECC decoder 422 has an ECC function stronger than the first ECC decoder.SELECTED DRAWING: Figure 4

In some embodiments, a storage device includes a printed circuit board, a memory device coupled to the printed circuit board, a storage controller which controls the memory device and is coupled to the printed circuit board, an active interposer including a logic element coupled to the printed circuit board, a sensor disposed inside the active interposer and configured to sense an impact and provide a sensor signal of the impact to the storage controller, and a strain gauge disposed inside the active interposer and configured to measure a physical strain and provide a signal about the physical strain to the storage controller.

According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

Examples of the present application provide memory systems, methods of operating thereof, and storage mediums. An example memory system includes at least one memory device and a memory controller; the memory controller is coupled with both a host and the memory device and includes a write buffer and a control section coupled with the write buffer; the control section is configured to: in response to upcoming execution of an erase event of a block in the memory device, configure a portion of an idle storage space of the memory controller as a newly-added storage space of the write buffer; write data received from the host to the newly-added storage space of the write buffer in response to execution of the erase event; and release the newly-added storage space of the write buffer in response to completion of the erase event.

A storage controller, a client system, and a method of operating a storage controller are disclosed. The client system includes a client host device and a client storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control read and write operations to the storage memory, and a homomorphic encryption and decryption accelerator configured to: based on receiving a read request from the client host device, perform homomorphic encryption on first plaintext data read from the storage memory to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client host device through the host interface; and based on receiving a write request from the client host device, perform homomorphic decryption on second homomorphic ciphertext data received through the host interface to generate second plaintext data, and write the second plaintext data into the storage memory.

A command including information associated with a relocation of data from a first storage device to a second storage device of multiple storage devices of a storage system is transmitted. The command causes the first storage device to relocate the data to the second storage device while bypassing a storage controller.

A memory system includes a storage controller, a memory, a first level filter and a second level filter. The storage controller configured to receive a first stage result. The memory configured to perform in-memory computing to the first stage result, to generate a second stage result. The first level filter configured to filter the second stage result to generate a third stage result. The second level filter configured to filter the third stage result to generate a fourth stage result. When a quantity of data results in the third stage result is larger than a predetermined threshold quantity, the memory system outputs the fourth stage result, and when the quantity of the data results in the third stage result is smaller than or equal to the predetermined threshold quantity, the memory system outputs the third stage result.

This ensures that the command bus is used efficiently while ensuring that refresh or precharge commands are issued at the appropriate time. [Solution] In memory systems 100 and 100a, the memory controller issues a command to the semiconductor memory device that includes an extended flag field F3 and a bank address field F2, which specify whether to precharge one, all, or two banks belonging to different bank groups, and the relative processing timing of the second bank to the first bank in the case of two banks. In the case of two banks, the semiconductor memory device precharges the first bank determined by the bank address field, and precharges the second bank, whose bank address is obtained by inverting the inverting target bit in the bank address field, at the relative processing timing.

In some aspects, a memory system is provided. The memory system may include a memory device and a memory controller. The memory device may include one or more dies each including a plurality of planes. Each of the plurality of planes may include a subset of pages to form a striping group in the one or more dies, and one word line of multiple word lines may be coupled to R strings in each plane to form R pages. The striping group may form J stripes. A ratio of J to R can be a value greater than 1 and less than 2. The memory controller may be coupled with the memory device and configured to receive data portions corresponding to the J stripes; generate J parity data portions based on the data portions; and control the memory device to store the J parity data portions.

Provided are a computer program product, system, and method for aggregating input / output operation features extracted from storage devices to form a machine learning vector to check for malware. Feature extraction functions are generated for the storage devices, indicating I / O operation features for the storage devices to gather. The feature extraction functions are communicated to the storage devices. The feature extraction functions transmitted to the storage devices cause the storage devices to gather information on I / O operation features, identified in the feature extraction functions, from the storage devices and transmit the information on the I / O operation features to the storage controller. The information on the I / O operation features are received from the storage devices. Information based on the received information on the I / O operation features are inputted into a machine learning model to output indication whether data in the storage devices contains malware.

The invention provides a working frequency adjusting method, a data processing system and electronic equipment, and relates to the technical field of electronics. The working frequency adjustment method comprises the following steps: monitoring the state of a task queue; the task queue is tasks needing to be distributed to a storage controller for execution; under the condition that the state of the task queue is monitored to be a full-writing state, monitoring that the task queue is in a first duration from the full-writing state until the task is sent to the storage controller; and if the first duration is greater than a first preset threshold value, sending a first frequency modulation request representing improvement of the working frequency of the storage controller.

A data storage device includes: a memory device including a plurality of first storage areas and a plurality of second storage areas, each of which stores a primary index corresponding to a primary key provided from a host and a primary value corresponding to the primary index, and a memory controller for controlling the memory device. The memory controller is configured to generate, according to a request from the host, the primary index including the primary key and address information of a target second storage area in which a primary value corresponding to the primary key is stored, among the plurality of second storage areas, generate, according to an additional request from the host, a secondary key corresponding to a secondary value including a portion of the primary value, and generate a secondary index including the secondary key and the address information of the target second storage area.

A storage system includes a storage device and a host device. The storage device includes a non-volatile memory device configured to store data and a storage controller configured to control the non-volatile memory device to isolate and store the data by grouping storage spaces of the non-volatile memory device into a plurality of isolated storage spaces. The host device includes a file system configured to generate and manage a plurality of file allocation instances corresponding to a plurality of file allocation system calls from an application program by allocating, with respect to each of the plurality of file allocation system calls, a logical address range and an isolated identifier of a plurality of isolated identifiers corresponding to the plurality of isolated storage spaces.

Examples of systems and methods described herein provide for erasing an encrypted key used for data access to a non-volatile memory device. A memory controller may generate an encrypted key for data access to non-volatile memory devices; and, to provide security of data stored on the non-volatile memory devices, the memory controller may store the encrypted key in a local cache of the memory controller. The encrypted key may be erased responsive to losing power or powering down of memory controller. Advantageously, the data stored at the non-volatile memory device may not be accessed when the memory controller (or a computing device implementing the memory controller) loses power. Accordingly, if a malicious actor were to physically remove (or steal) a computing device implementing the memory controller (e.g., a laptop computer), in an attempt to acquire the data, the data stored on the non-volatile memory devices could not be accessed.