791 results about "Control store" patented technology

The present disclosure relates to the field of chips. Provided are a computing chiplet and an electronic device. The computing chiplet is arranged on a first plane and is connected to a storage chiplet on a second plane, wherein storage arrays of the storage chiplet are connected to storage controllers of the computing chiplet, the number of transmission channels between each pair of connected storage controllers and storage arrays is greater than a first threshold value, and the connection direction of the storage controllers and the storage arrays intersects the first plane. The increase in the number of transmission channels can improve the memory access bandwidth, and arranging the computing chiplet and the storage chiplet on different planes can shorten a signal transmission path between the computing chiplet and the storage chiplet, thereby reducing power consumption. Using an optimized routing system to complete the communication between computing engines and the storage controllers of the computing chiplet reduces the number of specification types of routing channels, thereby reducing the design complexity of the routing system. The routing system can be arranged on the computing chiplet in a distributed manner, reducing the area overhead of the computing chiplet.

The invention discloses a debugging method, electronic equipment and a readable storage medium, in the method, after a storage controller receives an instruction reading notification sent by a host, a to-be-executed submission instruction is read from a submission queue; in the process of executing the submission instruction, if an error is detected, determining error basic information and error detail information; adding the error basic information into a core control field in the completion instruction, and adding the error detail information into an error detail field of the completion instruction according to an invalid byte identifier, an error subtype code and a context parameter form; and putting the completion instruction into a completion queue, and sending a command reading notification to the host, so that the host positions an error reason in combination with the error basic information and the error detail information. According to the method, the completion instruction is optimized, so that the completion instruction can carry not only the error basic information but also the error detail information, the host can quickly position specific error reasons, manual error analysis is avoided, the positioning efficiency is improved, and the debugging efficiency is accelerated.

Providing scalable and reliable container-based storage services, including: deploying a containerized storage controller on a first node among of plurality of nodes operable to support execution of the containerized storage controller; associating a dataset stored in backing storage accessible by the first node with one or more virtualized volumes presented by the containerized storage controller; and providing, by the containerized storage controller to one or more client hosts, a set of storage services for the one or more virtualized volumes.

A memory apparatus includes a memory device, a memory controller and a memory physical layer interface. The memory physical layer interface comprises a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit. The tap reset circuit generates a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset a DFE taps of the multi-tap DFE receiver during the gap interval between the read bursts. The tap reset circuit resets the plurality of DFE taps using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval. The tap reset circuit resets the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval. The second predetermined interval is greater than the first predetermined interval.

A computer-implemented method, computer program product, and computer system for managing computational storage operations. The computer-implemented method includes receiving a computational storage operation at a storage controller and inspecting the computation storage operation to determine a type of operation. The computer-implemented method further includes leveraging metadata of the storage controller to identify possible offload locations on storage devices for handling the computational storage operation of the determined type. The computer-implemented method further includes inspecting a register of storage devices maintained with the computational capabilities of the storage devices to determine which of the identified storage devices can support the computational storage operation to obtain candidate storage devices. The computer-implemented method further includes comparing the candidate storage devices using an estimated computational storage latency metric to select a storage device for handling the computational storage operation.

The invention discloses a cache controller for multi-control storage, a control method, a system and a server, is applied to the technical field of storage hardware, and aims to solve the problems of wiring complexity, cost reduction, cache utilization rate improvement and write-in delay of multi-control storage in related technologies. The cache controller comprises a switch supporting multi-host information sharing, a cache module connected with the switch and a central processing unit, the switch is provided with at least two first external bus interfaces used for being connected with storage controller nodes, and the central processing unit is connected with the cache module and the central processing unit. The division module is used for dividing a corresponding cache region for the storage controller node in the cache module under the condition that the switch detects that the storage controller node is accessed to the switch; the switch is used for acquiring the cache data sent by the storage controller node and writing the cache data into a cache region corresponding to the storage controller node in the cache module; the wiring complexity, the wiring cost and the writing delay can be reduced, and the cache utilization rate is improved.

The invention relates to the technical field of digital storage, and provides a method and a system for recovering long-term storage failure of a mobile terminal, through the design of a built-in independent power supply, a startup disk can still supply power continuously when the mobile terminal is in a power-off state, and the limitation of traditional OTG (On-The-Go) equipment is broken through. The read-write state of the data block of the flash memory chip is automatically monitored through the storage controller, and a health report is generated in real time; and when the early warning data block is detected, a bidirectional communication protocol is triggered. In a data backup link, a boot disk adopts a hierarchical check mechanism to generate CRC codes for each data block for centralized storage, and meanwhile, an overall SHA-256 code is calculated and double-end synchronization is performed. And in the recovery stage, the backup integrity is ensured through SHA-256 code comparison, then the data accuracy is verified block by block through CRC codes, and finally, the backup file is automatically migrated to the nonvolatile partition. The seamless closed loop from fault detection to data recovery is realized aiming at the system guidance problem after long-term storage of the equipment.

The invention relates to the technical field of microelectronics, and discloses a three-dimensional stacked near-memory computing architecture, a chip and a data access method. The memory device comprises at least one computing chip layer and at least one memory chip layer which are stacked along a first direction, a plurality of vertical interconnection channels extending along the first direction; the memory chip layer comprises a plurality of memory banks; the computing chip layer comprises a plurality of computing cluster units; the computing cluster unit comprises at least one storage controller; and the storage controller is connected with at least one of the plurality of storage banks through the vertical interconnection channel and is used for managing data in the correspondingly connected storage banks. The problems that in a three-dimensional stacking computing architecture, storage access delay is high, and the bandwidth expansion capacity is limited are solved.

An operating method of a storage controller includes, storing data and a source type of the data in a cache memory, when a cache hit occurs, determining a source type of data corresponding to the cache hit and updating a hit count corresponding to the determined source type among a plurality of hit counts, determining a source type with a dominant hit rate among a plurality of source types based on the plurality of hit counts, operating in a first mode when a result of the determining indicates that the source type with the dominant hit rate is a first type, and operating in a second mode when the result of the determining indicates that the source type with the dominant hit rate is a second type.

A method, computer program product, and computer system for managing a quorum device for a storage system having network of storage controllers of storage clusters. includes: using a first storage controller as a volume-based quorum device 201 for a second storage controller, wherein the first storage controller is aware of being treated as a quorum device; taking snapshots of cluster state metadata 206 at known points and saving as quorum volumes; and recovering the storage cluster from the cluster state metadata in the event of a failure 207. The method may also include selecting recovery points for taking snapshots depending on the type of cluster state metadata, it may also include integrating storage-centric actions into a control flow of the quorum device. The method may create safeguarded copies of the metadata, and may store multiple copies for point-in-time recovery.

In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.

This application is directed to resource management in a storage system that includes a non-volatile memory and a collection of resources having one or more processing cores. The storage system allocates a first subset of resources to process queues of I / O access operations requested by a host device. The first subset of resources includes a storage controller corresponding to a subset of processing cores. The storage system obtains a first request for adjusting resource allocation of the storage device, and the first request includes a target performance requirement for processing the queues of I / O access operations. The storage system determines that the target performance requirement can be satisfied by allocation of at least a target subset of resources. In response to the first request and based on the target subset of resources, a second subset of resources is allocated for processing the one or more queues of I / O access operations.

A storage device includes one or more ports that form an electrical connection with an external device, one or more physical functions including physical resources, and exposed through the one or more ports to communicate with the external device, a storage controller that controls an operation of the storage device, and communicates with the external device through the one or more ports and the one or more physical functions, nonvolatile memories controlled by the storage controller, and a first buffer memory controlled by the storage controller. When the storage device is accessed by the external device, the first buffer memory is used by the one or more ports and the one or more physical functions to temporarily store data for the external device.

A memory system includes a memory device including banks each including a plurality of rows, and configured to select, within a selected bank of the banks, at least one row from the plurality of rows based on a target address; and a row-hammer tracking module configured to: select the selected bank based on a pattern of accesses to each of the banks, and select the target address according to an access number for each of a plurality of groups of the rows within the selected bank.

A storage device includes a storage array with multiple planes organized as plane groups, where the planes of a plane group receive and process commands in parallel. The storage device includes a storage controller that receives a command from a host controller. In response to receipt of the command the storage controller provides ready information for all planes to the host controller. The multiple planes can optionally have independent multiplane read operation (IMPRO). Each plane group can have a first plane and a second plane, and the storage controller can optionally read data from the first plane of a plane group in response to a virtual ready signal for the first plane, before the second plane of the plane group is ready.

A storage device includes a memory device and a memory controller to control the memory device by communicating with the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel and each of the plurality of memory chips includes a transmission driver and an adaptive body bias generator. A target memory chip selected by the memory controller, among the plurality of memory chips, includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver in a write mode in which the target memory chip receives a write data from the memory controller and applies a second body bias in a read mode in which the target memory chip transmits a read data to the memory controller.

Apparatuses and techniques for reporting multiple events associated with mitigating usage-based disturbance are described. In an example aspect, a memory device can report to a memory controller various events associated with mitigating usage-based disturbance. This includes notifying the memory controller of events associated with a first event category and alerting the memory controller of events associated with a second event category. For events associated with the first event category, there can be a smaller risk of an alert condition occurring if the memory controller does not take action. For events associated with the second event category, there can be a larger risk of an alert condition occurring if the memory controller does not take action. By reporting these multiple events by category, the memory device empowers the memory controller to take appropriate action and efficiently manage available resources for mitigating usage-based-disturbance.

Methods, systems, and apparatus for management of program operations in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The peripheral circuit obtains a first temperature, and in response to determining that the first temperature is at or above a predetermined threshold, apply a first program voltage pulse with a first pulse width to a specified word line coupling memory cells of the memory cell array. The peripheral circuit obtains obtain a second temperature, and in response to determining that the second temperature is below the predetermined threshold, apply a second program voltage pulse with a second pulse width to the specified word line, where the second pulse width is larger than the first pulse width.

A server system includes a chassis, a primary system board, and a front drive cage. The front drive cage includes a plurality of front bays. An open compute project (OCP) storage controller module is installable within a given front bay of the plurality of front bays. The OCP storage controller module includes an OCP form factor PCB including an OCP edge connector formed in an edge therein. The OCP edge connector mates mated with an OCP connector disposed in the given front bay sch that the OCP storage controller module is electrically connected to a primary system board. Storage controller circuitry is mounted to and / or formed in the PCB, and an energy storage device is mounted to the PCB. The energy storage device comprises a housing and a battery contained in the housing and electrically connected to the storage controller circuitry.

A storage device includes a memory device that includes a plurality of memory cells, and a memory controller that controls the memory device. The memory device includes a memory cell array that includes the plurality of memory cells, a control logic circuit that writes data to the memory cell array or reads data from the memory cell array in response to a command received from the memory controller, and a page buffer that stores sensing data sensed from the plurality of memory cells. The control logic circuit includes an error detecting circuit that detects an error of first data stored in first memory cells of the memory cell array, and the control logic circuit writes the first data to second memory cells of the memory cell array, based on an error comparison result obtained by comparing the error of the first data with a preset value.

A technique for recovering data following a failure of a first availability zone (AZ) of a cloud-based system includes creating a plurality of temporary instances in a second AZ of the cloud-based system. The technique further includes copying, by the plurality of temporary instances, recovery data from multiple cloud-based snapshots to a plurality of local volumes of the second AZ such that the temporary instances of the plurality of temporary instances copy respective portions of the recovery data in parallel. The technique still further attaching the plurality of local volumes to a storage-controller instance running in the second AZ.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

A storage device includes a volatile memory and a storage controller, which is configured to control the volatile memory. The volatile memory includes a memory cell array, which has a plurality of sub-cell arrays therein, and a plurality of sub-wordline driver blocks, which are configured to drive sub-wordlines electrically connected to at least one of the plurality of sub-cell arrays. The storage controller includes: a volatile memory interface configured to transmit data to and receive data from the volatile memory, and detect an error bit(s) of data output from the volatile memory, a working memory configured to store a structure map table, which maps unit areas of the volatile memory, the sub-wordlines, and the plurality of sub-wordline driver blocks, and a processor, which is configured to: update an error count of a unit area of the volatile memory that corresponds to the error bit(s) detected from the volatile memory interface to the structure map table, detect at least one of a defective sub-wordline and defective sub-wordline driver block, by accessing the structure map table, and then repair at least one memory cell connected to the defective sub-wordline and / or repair at least one memory cell associated with the defective sub-wordline driver block.

The application discloses a layered data storage method and device, a storage medium and an electronic device, relates to the technical field of computers, and comprises the following steps: receiving a data write request, wherein the data write request is used for requesting to write target data into a target storage device, the target storage device comprises a plurality of storage layers used for storing data, a target storage controller is used for performing data access on the storage layers, and different storage layers have different data storage granularities; dividing target storage layers into which target data falls according to a target data amount of the target data and the data storage granularities; and writing the target data into the target storage layers, so as to solve the technical problem of low data layered storage efficiency in the prior art and achieve the technical effect of improving the data layered storage efficiency.

An example memory system includes a memory device and a memory controller coupled to the memory device. The memory device may include memory cells having a memory bit count of multiple bits, the memory cells include first and second types of memory bits, the first type of memory bits are used to store valid data, the second type of memory bits are used to store first type of check data, and the first type of check data is obtained by performing error correction encoding on the valid data stored in the first type of memory bits. The memory controller is configured to: perform error correction on the valid data in which an error occurs by at least using the first type of check data in the second type of memory bits when the error occurs in reading the valid data in the first type of memory bits.

Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.

Based on the WAF (Write Amplification Factor) value, the efficiency of writing data to non-volatile memory is improved, extending the lifespan of the non-volatile memory. [Solution] The image forming apparatus includes an image forming unit, a non-volatile memory (flash memory) for storing data, a memory controller for controlling the writing of data to the non-volatile memory, a storage device (SSD) including a storage unit that holds size information of the first data written to the non-volatile memory by the memory controller, and a main controller that outputs the second data to be written to the non-volatile memory to the memory controller. The main controller suspends the writing of the second data to the non-volatile memory if the size of the second data to be written to the non-volatile memory is less than or equal to a preset minimum size, and writes the two or more suspended second data to the non-volatile memory as a single second data if the combined size exceeds the minimum size.

A storage controller (for example, a storage control unit 123) can execute log creation processing of, when a write request is processed and control information or cache data is updated, adding a header to the updated data to create an update log and storing the update log in a log buffer. In the log creation processing when first-type control information (normal control information) is updated, the storage controller adds a log header to each piece of updated first-type control information to create an update log (normal log 132), and in the log creation processing when second-type control information (cache directory) is updated, the storage controller creates one consolidated log (consolidated log 137) as an update log related to a plurality of pieces of second-type control information.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.