1237 results about "Control store" patented technology

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

A method for managing a storage system includes initiating, by a hardware resource manager, a boot-up of a storage controller managing the storage system comprising a plurality of storage devices, making a determination, by the storage controller, that the storage controller is in a secured mode, based on the determination: identifying a security state of each of the plurality of storage devices, determining that a storage device of the plurality of storage devices is in an unsecured state, and based on the unsecured state, sending, by the storage controller, a security operation request for securing the storage device, obtaining a secure state response from the hardware resource manager corresponding to securing the storage device, and based on the secure state response, resuming operation of the storage controller based on the secure mode.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

The invention discloses a performance test method and device of a storage device, an electronic device and a storage medium, and relates to the technical field of data storage, and the performance test method comprises the steps of controlling the storage device to execute data operation in response to test input; wherein the data operation comprises read operation and / or write operation; in the process of executing the data operation by the storage device, obtaining performance data of the storage device through the performance test model; wherein the performance data comprises performance data of a data link of the storage device and performance data of the storage controller, the storage controller is electrically connected with the storage device through the data link, the data link is used for transmitting data between the storage controller and the storage device, and the performance test model comprises at least one performance monitoring tool. The at least one performance monitoring tool is used for performing performance monitoring on the data link and the storage controller; and generating a performance test report of the storage device according to the performance data. The technical effect of improving the performance test efficiency of the storage device can be achieved.

The invention discloses a time delay optimization method and device of a network interconnection system, electronic equipment and a medium, and relates to the field of network communication, and the method comprises the steps: adjusting the BAR resource window size of a non-transparent bridge processor in a BIOS based on a firmware file of a target processor, and re-burning the adjusted BIOS to a BMC processor, and initializing each DMA channel in the non-transparent bridge processor to obtain a physical address of each DMA channel, identifying the minimum physical address as a mapping initial address of the BAR, and mapping the mapping initial address and the BAR address space sum to a virtual address space of a user mode so as to access each DMA channel. The problem that the requirements for the overall bandwidth and low delay of the storage controller cannot be met when one DMA channel is started is solved, the data concurrent processing capacity of the non-transparent bridge processor is improved by enabling the four DMA channels and mapping the four DMA channels to the user mode, and therefore the interconnection bandwidth of the controllers is higher, and the interconnection delay of the controllers is lower.

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory blocks, each including a plurality of memory cells configured to store data, and a memory controller in communication with the memory device and configured to 1) determine a write mode of a memory block of the memory device to be either a first write mode in which one data bit is stored in a memory cell of a memory block or a second write mode in which a plurality of data bits is stored in a memory cell based on a temperature of the storage device and a number of read reclaim operations that have been performed in the memory block and 2) control the memory device to perform a write operation in the determined write mode.

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and / or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

A storage system includes: a host configured to receive a software image and a first signature for the software image, the first signature being generated based on a first secret key, and generate, based on a second secret key, a second signature for the software image; and a storage device configured to receive, from the host, the software image, the first signature, the second signature, and a second public key related to the second secret key and execute the software image, based on a first verification and a second verification the first verification being performed on the first signature on the basis of a first public key related to the first secret key, and the second verification being performed on the second signature on the basis of the second public key.

A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input / output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input / output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input / output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input / output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall. The IC structure further includes a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor memory die, and a packaging substrate under and electrically connected to the logic die with memory controller and processor. There is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.

A storage device may include; a non-volatile memory including a first memory region including first memory cells having a first data storage capacity, a second memory region including second memory cells having a second data storage capacity greater than the first data storage capacity, and a third memory region including third memory cells having a third data storage capacity greater than the second data storage capacity, and a storage controller configured to receive a request, data, and storage time information associated with the data from a host, and program the data in a selected one of the first memory region, the second memory region and the third memory region in response to the request and on the basis of the storage time information.

The present disclosure relates to the field of chips. Provided are a computing chiplet and an electronic device. The computing chiplet is arranged on a first plane and is connected to a storage chiplet on a second plane, wherein storage arrays of the storage chiplet are connected to storage controllers of the computing chiplet, the number of transmission channels between each pair of connected storage controllers and storage arrays is greater than a first threshold value, and the connection direction of the storage controllers and the storage arrays intersects the first plane. The increase in the number of transmission channels can improve the memory access bandwidth, and arranging the computing chiplet and the storage chiplet on different planes can shorten a signal transmission path between the computing chiplet and the storage chiplet, thereby reducing power consumption. Using an optimized routing system to complete the communication between computing engines and the storage controllers of the computing chiplet reduces the number of specification types of routing channels, thereby reducing the design complexity of the routing system. The routing system can be arranged on the computing chiplet in a distributed manner, reducing the area overhead of the computing chiplet.

Computing system and operating method thereof are provided. The computing system comprises a storage cluster which includes at least one storage devices, and a switch which is configured to provide an interface between the storage devices included in the storage cluster, in which the storage cluster includes a first storage device and a second storage device, the first storage device includes a first storage controller, a first non-volatile memory which is controlled by the first storage controller, and a first volatile memory which includes a first memory region and a second memory region, in which the first storage device is configured to provide first data stored in the first memory region to the second storage device through the switch, in response to power not being supplied at the first storage device, and the first data is caching data.

A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2N states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2N states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.

A memory system includes a semiconductor memory device; and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a first pin configured to receive a first signal and a second signal sent from the memory controller, the second signal having a smaller amplitude than the first signal. A first receiving circuit is connected to the first pin and is configured to output a third signal and a fourth signal having a smaller amplitude than the third signal. The first receiving circuit outputs the third signal based on a comparison between the first signal and a first voltage, and outputs the fourth signal based on a comparison between the second signal and a second voltage. A first terminating circuit is connected to the first pin and is configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal.

A memory device of a storage device may receive a garbage collection command from a memory controller coupled to the memory device to perform an internal garbage collection operation within the memory device. The memory device may attempt to perform the garbage collection operation to internally move valid memory pages from a first memory block to a second memory block to free up the first memory block in response to the garbage collection command. The memory device may send an acknowledgement to the memory controller for the garbage collection command.

According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.

Provided are a computer program product, system, and method for generating data protection directives to provide to a storage controller to control access to data in cache. A data protection directive is generated for a data subset indicating access request type and a protective action with respect to the access request type for the data subset. The data protection directive is transmitted to the storage controller. The storage controller includes the data protection directive in metadata for the data subset. The data protection directive causes the storage controller to perform the protective action in response to an access request of the access request type to a portion of the data subset.

The invention discloses a command transmission method, system and device and a computer readable storage medium, relates to the technical field of storage, is applied to a host, and determines a target memory allocated for a data transmission field in an NVMe specification; obtaining to-be-queried first attribute information; filling the first attribute information into a target memory; generating a first NVMe query instruction which does not carry the first attribute information; transmitting the first NVMe query instruction to a storage controller, so that the storage controller reads the first attribute information from the target memory after receiving the first NVMe query instruction; and in response to a received first NVMe response instruction transmitted by the storage controller, reading a query result of the first attribute information filled in the storage controller from the target memory. According to the invention, the number of times of message interaction between the host and the storage controller is reduced through time-sharing multiplexing of the target memory, and the data transmission efficiency is improved.

An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels are organized as a plurality of channel groups. The memory controller comprises a plurality of memory access request / response buffer sets, and each memory access request / response buffer set of the plurality of memory access request / response buffer sets corresponds to a different one of the plurality of channel groups.

A storage controller, a data reading method and a storage device. data reading method: identifying a plurality of logical addresses corresponding to files based on file read commands; determining a plurality of mapping tables corresponding to files based on logical addresses; loading a first mapping table corresponding to a first file to a first memory section of a buffer memory; identifying one or more second logical addresses of one or more second files corresponding to first mapping table among files or than first file; determining target content of first mapping table based on one or more second logical addresses, and copying target content to a second memory section of buffer memory; and from target content, finding a fourth physical address corresponding to a fourth logical address of a fourth file among second files, to read fourth data of fourth file, so as to respond to a fourth file read command.

The invention discloses a debugging method, electronic equipment and a readable storage medium, in the method, after a storage controller receives an instruction reading notification sent by a host, a to-be-executed submission instruction is read from a submission queue; in the process of executing the submission instruction, if an error is detected, determining error basic information and error detail information; adding the error basic information into a core control field in the completion instruction, and adding the error detail information into an error detail field of the completion instruction according to an invalid byte identifier, an error subtype code and a context parameter form; and putting the completion instruction into a completion queue, and sending a command reading notification to the host, so that the host positions an error reason in combination with the error basic information and the error detail information. According to the method, the completion instruction is optimized, so that the completion instruction can carry not only the error basic information but also the error detail information, the host can quickly position specific error reasons, manual error analysis is avoided, the positioning efficiency is improved, and the debugging efficiency is accelerated.

Secure and efficient access to host memory for guests is disclosed. For example, a system includes (i) a processor, (ii) a host memory, (iii) a hypervisor including a filesystem daemon, (iv) a guest including a storage controller, and (v) a first filesystem queue. The storage controller is configured to receive a file request, translate the file request, and add the translated file request to a filesystem queue. The filesystem daemon is configured to retrieve the translated file request from the filesystem queue and provide access to a file in the host memory identified in the file request to the guest.

Providing scalable and reliable container-based storage services, including: deploying a containerized storage controller on a first node among of plurality of nodes operable to support execution of the containerized storage controller; associating a dataset stored in backing storage accessible by the first node with one or more virtualized volumes presented by the containerized storage controller; and providing, by the containerized storage controller to one or more client hosts, a set of storage services for the one or more virtualized volumes.

A memory apparatus includes a memory device, a memory controller and a memory physical layer interface. The memory physical layer interface comprises a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit. The tap reset circuit generates a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset a DFE taps of the multi-tap DFE receiver during the gap interval between the read bursts. The tap reset circuit resets the plurality of DFE taps using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval. The tap reset circuit resets the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval. The second predetermined interval is greater than the first predetermined interval.

A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass / fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.