1948 results about "Physical address" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

The invention relates to the technical field of solid state disks, and discloses a load collaborative scheduling method and system for a solid state disk, and the method comprises the steps: carrying out the data collection of a main controller of the solid state disk, and obtaining the original feature data; a Kolmogorov-Arnold neural network is input to carry out nonlinear feature transformation and linear combination operation, and a load prediction result is obtained; performing hierarchical processing to obtain a hierarchical scheduling model; constructing a multi-objective optimization function and carrying out constraint setting to obtain a constraint optimization equation set; performing convex difference function decomposition and augmented Lagrange function construction on the constraint optimization equation set, and solving through an alternating direction iteration method to obtain a scheduling decision scheme; according to the scheduling decision scheme, load balancing control is carried out on data write-in physical address allocation, data read cache scheduling and multi-channel parallel transmission, a real-time performance monitoring index is obtained, and the method realizes load collaborative scheduling of the solid state disk.

A key-value cache management system processes inference requests of a generative model. An inference request requests a starting virtual memory address and a number of layers in the generative model. In response to receiving an inference request, contiguous virtual memory space is reserved for the key-value cache in accordance with the inference request by assigning the starting virtual memory address in the key-value cache and calculating memory pointers for each layer in the model and each block so that the one or more blocks are written sequentially. The generated memory pointers are outputted to the generative model so that each self-attention layer writes computed key-value pairs at physical addresses in the key-value cache specified by the memory pointers.

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

The invention discloses an address mapping method in DPU local storage virtualization, which comprises the following steps: a virtual machine calls a system call interface provided by an address mapping configuration management module on a host side to perform mapping configuration of a virtual machine physical address and a host physical address, and issues the virtual machine physical address and length to a virtual address mapping module of a DPU; the virtual address mapping module manages global direct memory access address resources, firstly allocates a global direct memory access address on a host side, then maps a virtual machine physical address to the allocated global direct memory access address in a mapping page table of the DPU, and returns the virtual machine physical address to the address mapping configuration management module; and the address mapping configuration management module obtains the distributed global direct memory access address, and maps the distributed global direct memory access address to a host physical address in the IOMMU. According to the method, by optimizing address mapping, the efficient and flexible local storage virtualization service can be realized while the data reliability is ensured.

A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

According to the system memory management method and system, the electronic equipment and the storage medium provided by the invention, the virtual address information in the access information is extracted, and the virtual address information comprises the target virtual address; under the condition that the target virtual address is determined to be in a first preset virtual address range according to the virtual address information, determining an initial physical address corresponding to an initial virtual address in the first preset virtual address range according to a preset address mapping table; performing physical address calculation processing according to the target virtual address, the initial virtual address and the initial physical address to obtain a target physical address corresponding to the target virtual address; and accessing a system memory based on the target physical address and performing memory management on the system memory. By quickly returning the conversion relation from the virtual address to the physical address in the specified range, the conversion efficiency from the virtual address to the physical address can be improved, a conversion page table does not need to be configured according to MMU granularity, waste of storage space can be reduced, and the address conversion efficiency can be improved.

Embodiments of the present application relate to a method, a bridging device, a system and a medium of virtualization processing of a storage device. The method comprises: receiving an initial access request to a virtual disk sent by a virtual machine user; translating the virtual address corresponding to the virtual machine to a first physical address corresponding to a host based on a preconfigured address mapping relationship; translating the virtual access address to a second physical address corresponding to the storage device based on a preconfigured virtual partition mapping relationship; and generating a target access request based on the first physical address and the second physical address, and sending the target access request to the host, so as to cause the host to perform information interaction with the storage device based on the target access request.

The embodiment of the invention provides memory equipment based on a computing fast link protocol and a control method. The memory device comprises a plurality of dynamic random access memories, a plurality of nonvolatile memories and a controller of the memory device, wherein the controller comprises a CXL subsystem; the cache manager is used for storing a cache table recording the mapping relation between the physical address of the equipment and the cache address; the controller of the dynamic random access memory is set to perform read or write operation on the dynamic random access memory according to the cache address; and the controller of the nonvolatile memory is set to perform read or write operation on the nonvolatile memory according to the equipment physical address so as to write the data from the dynamic random access memory into the nonvolatile memory, or read out the data from the nonvolatile memory so as to store the data into the dynamic random access memory. According to the embodiment of the invention, based on the existing server architecture, the expansion of the memory is realized, and the use cost of the memory is reduced.

The invention discloses a memory allocation method and related equipment, which are applied to electronic equipment, and the method comprises the following steps: receiving a first memory request of an application program, the first memory request comprising a target memory space value; determining a virtual address matched with the target memory space value from a virtual memory space, and determining a target virtual address to be mapped from the virtual address; a to-be-mapped target physical address is determined from a physical memory space, whether the target virtual address and the size and byte boundary of the target physical address meet a first condition is judged, and the first condition comprises the alignment type of the byte boundary; if the first condition is met, determining an attribute parameter matched with the first condition; and creating a page table matched with the attribute parameter, and establishing a mapping relationship between the target virtual address and the target physical address. By adopting the embodiment of the invention, the memory access efficiency can be improved.

The invention provides a solid state disk testing method and device, equipment and a medium, and relates to the technical field of hard disk detection. The test method comprises the following steps: in a process of writing data into physical areas of a to-be-tested solid state disk according to a physical address in sequence, randomly selecting at least part of areas from the physical areas written with the data at a preset time interval to perform reset operation until the physical areas reach a target area state, the target area state comprises a target filling state and a target fragmentation state; executing a read-write test on the physical region in the target region state to obtain test data; and generating a test report based on the test data.

The invention provides a DPU (Data Processing Unit)-based RDMA (Remote Direct Memory Access) virtualized memory address conversion and data transmission method and a DPU-based RDMA virtualized memory address conversion and data transmission system. The method comprises the following steps that: a user process specifies a client virtual address and a corresponding memory The virtual machine kernel generates a first memory conversion table, and the first memory conversion table records conversion from the client virtual address to the client physical address. When the drive program of the remote direct memory access device obtains the first memory conversion table, a preset instruction is triggered to enable the execution control right to be switched to the virtual machine supervision program from the virtual machine kernel. The customer physical address is converted into the host virtual address in the switching process. The virtual machine supervision program obtains mapping from the host virtual address to the host physical address through the host system information, and a second memory conversion table containing the conversion relation from the client virtual address to the host physical address is obtained. The execution control right is switched back to the kernel of the virtual machine, and the second memory conversion table is configured to the remote direct memory access device DPU. According to the method, address conversion can be simplified, hardware dependence is reduced, and RDMA performance is improved.

The invention provides a multi-host system and a cross-domain access method. The system comprises a structure manager and at least two host domains, the structure manager is used for discovering and managing a topological structure of the multi-host system, distributing segment serial numbers for hosts and distributing port identification numbers for host edge switches, edge ports and downstream edge switches; the structure manager obtains equipment information of the terminal equipment and sends the equipment information to the host; the host sends a request message to the terminal equipment through the host edge switch via the port-based routing switching network; the downstream edge switch establishes an association relationship between a segment serial number and a port identification number carried in the request message, and maps a physical address of a host needing cross-domain to a physical address of a host subjected to cross-domain; and the downstream edge switch receives the completion message, determines a port identification number corresponding to the segment serial number carried in the completion message based on the association relationship, carries the port identification number in the completion message as a destination end identifier, and sends the port identification number to a corresponding host.

A system can include a memory device and a processing device operatively coupled with the memory device, to perform operations of maintaining a set of data items reflective of a state of a host application and receiving a first request to make a checkpoint copy of the state of the host application. The operations can also include responsive to receiving the first request, associating a snapshot identifier with the object identifier, and receiving a second request to modify a data item of the set of data items at the first set of physical address ranges. They can also include executing the second request by recording a modification a data item exclusively at a second set of physical address ranges and making the checkpoint copy by copying the set of data items of the snapshot from the first set of physical address ranges to a second memory device.

Embodiments of the present disclosure provide a memory access instruction processing method and a communication device. The method comprises: acquiring a memory access instruction, and parsing the memory access instruction to obtain a parsing result; according to instruction type information of the memory access instruction in the parsing result, allocating for the memory access instruction an instruction processing queue adapted to the memory access instruction; determining a physical address corresponding to each memory access instruction in the instruction processing queue; determining an address access sequence of the physical address corresponding to each memory access instruction in the instruction processing queue, and executing an instruction processing policy for the memory access instruction corresponding to the access sequence conforming to a preset memory model.

Methods, apparatuses, and systems related to storing non-mission-critical data using retired memory slots are described. An apparatus includes circuitry configured to determine that a post package repair (PPR) operation, associated with a memory row of a memory device, has been requested by a host device communicably coupled to the circuitry. The memory row is associated with a physical address. The circuitry determines a location of a defective bit in the memory row. Retired row data comprising the physical address associated with the memory row and the defective bit location is maintained in non-transitory memory of the apparatus.

A memory pooling configuration system includes: a plurality of servers, an expansion switch in communication with the plurality of servers, and a memory configuration device. A target server acquires first memory pooling configuration information, which instructs the target server to send a second memory access request to the expansion switch when a virtual address indicated by a first memory access request does not correspond to a physical address space of the target server. The expansion switch acquires third memory pooling configuration information, which instructs the expansion switch to forward the second memory access request to an associated server based on the second memory access request. The associated server acquires second memory pooling configuration information, which instructs the associated server to return the memory access result of the second memory access request to the expansion switch, which forwards the memory access result to the target server.

The invention provides a data interaction method and device based on a shared memory, virtual electronic equipment and a storage medium, and the method comprises the steps: responding to a detected packet sending request of a first application for a first protocol stack of first virtual network equipment, and calling a first packet sending function; encapsulating the to-be-sent data into a first data packet based on the first packet sending function; obtaining a storage address of the first data packet, and mapping the storage address in a mode of directly accessing a mapping interface by a memory to obtain a mapped physical address; and filling the physical address into a corresponding position of the descriptor of the first virtual network equipment, and updating the position of a tail pointer of the descriptor. The RC and the EP are registered as the virtual network card through the network driving technology, so that the communication function can be realized through the PCIE slot and by means of the PCIE connecting line, data message transmission can be realized without the aid of peripheral equipment such as the network card, the stability of data transmission is improved, and the configuration cost of hardware is saved.

The invention discloses a memory allocation method and device, electronic equipment and a nonvolatile storage medium, and is applied to the technical field of storage. The method comprises the steps that in the memory initialization process, a corresponding application program special memory is applied according to a reserved memory configuration file, and the application program special memory is assembled into a continuous memory space in the mode that physical addresses are continuous and belong to the same memory device; in the user mode, assembling the continuous memory space to generate a user mode memory structure according to memory mapping information of the continuous memory space mapped to the user mode under the triggering of the memory application request; when a memory calling request sent by the target application program in the initialization process is detected, a matched target memory is applied for the target application program from the user mode memory structure, and the target memory is cached into the process space to be used by the target application program. According to the invention, the problem that memory application is caught in a kernel mode in related technologies can be solved, and the memory allocation efficiency is effectively improved.

Embodiments for communicating between first and second hosts according to CXL.mem and CXL.cache protocols. A computer translates a CXL.mem M2S RwD with a Tag, received by a CXL Type 2 or Type 3 device (EP1) from the first host, to a CXL.cache D2H Req with a CQID. A CXL Type 1 or Type 2 device (EP2) sends the D2H Req to the second host, and receives a CXL.cache H2D Rsp with the CQID and a UQID. EP1 sends a CXL.mem S2M NDR with the Tag to the first host, and EP2 sends a CXL.cache D2H Data message with the UQID to the second host. Optionally, EP1 receives and terminates CXL.io / PCIe Configuration Request TLPs from the first host, the M2S RwD further includes a first physical address and Data, and the D2H Req further includes a second physical address.

The invention discloses a memory management method, a program product, equipment and a medium, and relates to the technical field of computers.The memory management method comprises the steps that memory configuration information in the system kernel starting process is obtained, and a reserved memory range is determined based on the memory configuration information; segmenting the reserved memory based on the hot plug framework of the memory and the reserved memory range; allocating corresponding target metadata to each reserved memory segment to obtain a configured physical memory; the target metadata is metadata representing a data structure of the physical memory page; establishing a target mapping array based on the memory configuration information; the target mapping array is used for recording a mapping relation between a physical address and a logic page number in the configured physical memory; responding to the target memory access request by utilizing the target mapping array, and completing corresponding memory access operation; the target memory access request is an access request initiated for the reserved memory, so that the universality of the reserved memory is improved, the overall manageability of the system is enhanced, and the complexity and maintenance burden of the system are reduced.

The invention relates to a virtualized nested translation method and system and a readable medium. The method comprises the following steps: receiving a virtual address translation request, judging an address translation mode of the virtual address translation request, and determining a virtual address type; selecting a corresponding translation cache according to the determined virtual address type; under the selected translation cache, executing address translation in the multi-level translation cache by adopting a parallel or serial lookup mode to obtain a lookup result; judging whether the search result hits a leaf item of the page table or not; if the searching result hits the leaf item, the corresponding physical address is returned to complete translation; and if the leaf item is not hit, performing page table traversal to obtain the physical address. According to the method, the speed of virtualization nested translation can be increased, the translation cache redundant virtual address and the translation path cache redundant PTE under the single technical condition are reduced, and the translation delay from the virtual address to the physical address in memory virtualization or peripheral virtualization is improved.

Provided in the present application are a memory pre-loading processing method, and a device and a storage medium. The method comprises: a virtual machine manager collecting a plurality of pieces of historical page fault information that are generated by a target application program in a client; on the basis of a plurality of client virtual addresses that are included in the plurality of pieces of historical page fault information, determining a target client virtual address to be accessed when a page fault occurs in the target application program next time; on the basis of the target client virtual address and a storage address of a target client system page table corresponding to the target application program, determining a target host machine virtual address corresponding to the target client virtual address; and controlling a host machine operating system to allocate a target host machine physical address corresponding to the target host machine virtual address, and loading data, which corresponds to the target host machine virtual address, into the target host machine physical address. By means of loading, into a memory in advance, data corresponding to a target client virtual address in which a page fault may occur in the future, an access delay duration caused by the page fault is shortened.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

The invention provides a memory preloading processing method and device and a storage medium, and the method comprises the steps that a virtual machine manager collects a plurality of pieces of historical missing page exception information generated by a target application program in a client, and stores the historical missing page exception information according to a plurality of client virtual addresses contained in the historical missing page exception information; determining a target client virtual address to be accessed when the target application program is subjected to page missing exception next time; determining a target host machine virtual address corresponding to the target client virtual address according to the target client virtual address and a storage address of a target client system page table corresponding to the target application program; and controlling the host machine operating system to distribute a target host machine physical address corresponding to the target host machine virtual address, and loading data corresponding to the target host machine virtual address into the target host machine physical address. And the data corresponding to the target client virtual address which may cause the page missing abnormity in the future is loaded into the memory in advance, so that the access delay duration caused by the page missing abnormity is reduced.

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of pages in which data is stored, and a memory controller configured to provide, when a read request is externally received, address information including a physical address and a dummy address to the memory device. The memory device may perform a successive read operation of sequentially reading data from pages starting from a selected page corresponding to the physical address, among the plurality of pages, according to the dummy address.

The invention provides a remote direct memory access system, equipment and a cluster. The system comprises the following steps: a remote direct memory access device sends a first address conversion request to a host under the condition that a first physical address corresponding to a first virtual address does not exist; the host queries a first physical address corresponding to the first virtual address in a memory of the host according to the first address translation request, and returns a translation failure response to the remote direct memory access device under the condition that the first physical address corresponding to the first virtual address cannot be queried; the remote direct memory access device sends a page request to the host based on the conversion failure response; the host migrates data corresponding to the first virtual address from a hard disk of the host based on the page request and locks the data in a memory of the host, and returns a page request response; and the remote direct memory access device stores the corresponding relationship between the first virtual address and the first physical address into an address translation list based on the page request response.

A system may include multiple processors. One of the processors may receive an indication of a data synchronization barrier (DSB) instruction in another processor that follows a translation look-ahead buffer invalidate (TLBI) instruction to invalidate an entry of a translation look-ahead buffer. The processor may determine whether instructions are pending in the processor for which the virtual addresses used for memory accesses have been translated to physical addresses before receiving the DSB indication. If there are such pending instructions, the processor may provide, after these instructions retire, an indication to the other processor as a response to the DSB indication.

An apparatus comprises request receiving circuitry to receive a given memory system request specifying a target address in a given physical address space and a target memory encryption context identifier (MECID) indicative of a selected memory encryption context associated with the memory system request. Snoop filtering circuitry determines whether a snoop request is to be transmitted to a given caching agent in response to the given memory system request. The snoop filtering circuitry determines, based on the target MECID of the given memory system request and on snoop filtering information associated with the given caching agent, whether the target MECID is a snoop-not-required MECID for the given caching agent. In response to determining that the target MECID is a snoop-not-required MECID for the given caching agent, the snoop filtering circuitry suppresses transmission of a snoop request to the given caching agent in response to the given memory system request.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.