154 results about "Physical address" patented technology

Disclosed in the embodiments of the present application are a root file system loading method and a related apparatus. In the method, a part of a virtual memory is simulated as a random access memory disk (RAMDISK) mechanism used by a block device. First, a read-only memory file system (ROMFS) mirror image file on an initial physical address is acquired; and then, a virtual address corresponding to the initial physical address of the ROMFS mirror image file is directly used as the starting address of the block device, such that the copy operation of copying the ROMFS mirror image file to the block device is executed on the initial physical address, thereby formatting the block device. Then, a kernel can be booted by means of mounting the ROMFS mirror image file in the block device as a root file system. By using the ROMFS image file as a root file system and reducing copy operations during a boot process, the kernel boot time is shortened in read‑only application scenarios requiring fast boot, thereby achieving fast kernel boot.

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.

The application provides a data storage method, medium and computer program product for a large model. The data storage method for the large model comprises: in an inference stage of the large model, organizing quantized data to be stored and corresponding quantized parameters in a same storage tensor, wherein the storage tensor has multiple dimensions, and from an outermost layer to an innermost layer dimension, the dimensions comprise: a block dimension corresponding to a physical storage block in a paging management mechanism, each physical storage block having a continuous physical address range; an attention head dimension corresponding to an attention head defined for the large model; a word element dimension corresponding to a word element generated in the inference stage; a quantization grouping dimension corresponding to a quantization grouping of each word element on a feature dimension of each attention head; and a data dimension organizing quantized data and quantized parameters of each quantization grouping; and based on a logical storage structure of the storage tensor, storing the quantized data and the quantized parameters in a physical storage block of a cache.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

A host command to deallocate a memory device is received. A logical-to-physical (L2P) status data structure associated with a logical-to-physical (L2P) data structure is invalidated. The L2P mapping data structure includes a plurality of regions. Each region comprises a set of L2P address mappings and a region identifier identifying a respective region. The L2P status data structure includes a plurality of L2P status entries. An L2P status entry comprises a region identifier identifying a region of the plurality of regions of the L2P mapping data structure and a physical address identifying a location of the region of the L2P mapping data structure stored on the memory device. A host is notified that deallocation of the memory device is completed. Invalidation of the L2P mapping data structure is initiated.

This application provides a memory management apparatus and method for an intelligent processor. The memory management apparatus includes a prefetch circuit, a setting circuit, and a mapping circuit. The prefetch circuit obtains raw data via a direct memory access circuit. The raw data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory. The setting circuit parses the raw data to sequentially map each of the physical addresses to a plurality of second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores the mapping relationship between each physical address and the corresponding second virtual address as a first mapping table according to the write request, and accesses the memory using the first mapping table according to at least one read request corresponding to at least one channel of the direct memory access circuit.

Various embodiments include techniques for translating memory addresses in a virtualized computing system that hosts multiple virtual machines. In such a virtualized computing system, conventional approaches for translating a guest virtual address to a system physical address can involve a large number of memory accesses. With the disclosed techniques, address translation can be reduced to approximately 5 memory accesses. This performance savings results from storing two data structures in high-speed on-chip memory that indicate which system physical address segments are mapped to and valid for the virtual machine that is accessing the memory segment. A third data structure indicates whether a system physical address segment is a protected / secure system physical address segment. If the virtual machine already has access to the segment, then confidential / secure compute policies can be applied on the accesses from this virtual machine based on whether this system physical segment is protected / secure.

An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

Methods, systems, and devices for physical prefetch are described. A memory system may prefetch data from physical addresses that are sequential to a physical address that has recently been read by the memory system. For example, the memory system may determine that a rate of access for a virtual block exceeds a threshold, and the memory system may prefetch the physically sequential data in response to the rate of access exceeding the threshold. In some examples, the memory system may receive a command to read a logical block address corresponding to a first physical address. The memory system may determine that the rate of access to the virtual block exceeds the threshold. The memory system may identify one or more second physical addresses that are sequential to the first physical address, and the memory system may transfer data from the one or more second physical addresses to a buffer.

A data item is programmed to a first set of physical management units (MUs) associated with a memory sub-system in accordance with a first pass programming operation of a multi-pass programming scheme. An entry of a data structure is updated to include a mapping that associates a first physical address associated with the first set of physical MUs with a set of virtual MUs associated with the memory sub-system. A detection is made that a second pass programming operation of the multi-pass programming scheme is initiated to program the data item to a second set of physical MUs associated with the memory sub-system. Responsive to the detecting, the entry of the data structure is updated to include an additional mapping that associates the set of virtual MUs with a second physical address associated with the second set of physical MUs.

A physical address determining method and apparatus, a computing device, and a storage medium, where the method includes generating an input tag based on a virtual page number in a first virtual address, which is matched with a plurality of entries in a page table cache. If the input tag successfully matches a first entry in the plurality of entries, and a combination flag bit in the first entry indicates that a page table entry corresponding to the first entry is a combined entry, a physical address corresponding to the first virtual address is determined based on the virtual page number in the first virtual address and an entry tag and a physical page number in the first entry.

Disclosed are a data copying method and device, and relate to the field of computers, and realize data copying without access awareness under the premise of ensuring the accuracy of data access and without increasing the complexity of scripts or frameworks. The method can include: a first processor receiving a first instruction for indicating copying data stored at a first physical address to a second physical address in a fourth memory; the first processor copying target data stored at the first physical address to a space indicated by the second physical address in response to the first instruction; the first processor receiving a second instruction for remapping a virtual address to the second physical address, and in response to the second instruction, releasing a mapping relationship between the virtual address and the first physical address, and mapping the virtual address to the second physical address.

This invention relates to the intersection of cloud computing security, trusted computing, and hardware acceleration technologies, and discloses a virtual machine trusted state verification method and system based on TIPU. The method includes: configuring a measurement task on the host side of the TIPU, the measurement task containing the memory address information of the target virtual machine and its corresponding expected hash value; the TIPU directly reading the memory data of the target virtual machine via DMA based on the memory address information to generate an actual hash value; the TIPU comparing the actual hash value with the expected hash value to determine whether the target virtual machine is in a trusted state; when the virtual machine is determined to be in an untrusted state, the TIPU calls a built-in root of trust to sign the verification result and generate a remote proof report. This invention obtains the mapping table from the client's physical address to the host's physical address through the virtualization platform interface via a host agent and pre-configures it to the TIPU. The TIPU only accesses the target virtual machine's memory, achieving virtual machine context awareness and effectively avoiding cross-virtual machine information leakage.

This invention discloses a BIM building model construction method for architectural engineering design, specifically relating to the field of electronic digital data processing technology. First, based on spatial boundary vertices, a mapping table is established between memory page identifiers and physical addresses for each node. Based on this mapping table, a dynamic preloading instruction set is generated using a viewpoint prediction algorithm. Based on the mapping table and the dynamic preloading instruction set, a dynamic attribute graph model is generated, followed by another dynamic attribute graph model. Based on the dynamic attribute graph model, a final optimized attribute graph model is obtained, and finally, a BIM building model is constructed. This invention utilizes graph neural network semantic mapping to achieve unified attribute graph representation of heterogeneous data from multiple disciplines, improving the accuracy of semantic mapping. Simultaneously, it uses graph convolutional networks to achieve real-time detection of design conflicts, combined with a bidirectional feedback mechanism to achieve real-time conflict correction, solving the problem of lagging offline detection in existing methods.

The application discloses an AI vision-based video VLM model inference acceleration method, comprising the following steps: S1, synchronously collecting a video stream and hardware state parameters; S2, dynamically sparsifying sampling to generate a sparse frame sequence; S3, allocating a continuous video memory physical address pool; S4, using an improved VideoMAE model and constructing a video memory direct-reading forward propagation layer to obtain a base address pointer to skip a standard interface, performing streaming calculation to reconstruct features in an SM, and outputting a compressed Token sequence; S5, using remaining space to store key-value caches to perform large model calculation to output semantic features; S6, using an Orca algorithm to insert micro-batch calculation during SM idle periods to cover up delayed output inference texts; and S7, releasing the caches and dynamically adjusting a frame rate and a compression ratio to perform a cycle. The application eliminates redundant copying and significantly improves inference throughput.

Provided are a storage management apparatus, a processor, related apparatuses and related methods. The storage management apparatus comprises: a first-level storage management unit configured to translate a specified virtual address to a corresponding virtual physical address according to a first-level page table cache table item matching the specified virtual address, the first-level page table cache table item storing a mapping relationship between a virtual address frequently accessed by a process in an operation domain and a virtual physical address; and a second-level storage management unit configured to translate the specified virtual physical address to a physical address according to a second-level page table cache table item matching the specified virtual physical address, thereby realizing translation of the virtual address to the physical address, the second-level page table cache table item storing a mapping relationship between the virtual physical address corresponding to the virtual address frequently accessed by the process in the operation domain and the physical address. The embodiments of the present disclosure improve communication efficiency between processes in different operation domains and reduce a large amount of processor computing resources and bus bandwidth.

This invention discloses a data storage method and device based on a block storage engine. The data storage method includes: dividing a logical block of the block storage engine into multiple first logical units; dividing a second logical unit according to the capacity of the first logical units; dividing the physical disk space into physical mapping units with fixed capacities according to the capacity of the logical blocks; allocating corresponding physical mapping units according to the capacity of the logical blocks and storing physical data in the physical mapping units; forming the physical storage address of the physical data and the metadata corresponding to the physical storage address based on the first address mapping relationship between the logical blocks and the physical mapping units, the second address mapping relationship between the first logical units and the physical mapping units, and the physical address of each physical mapping unit. The data storage method based on the block storage engine provided by this invention effectively reduces the amount of metadata in address mapping in a distributed block storage engine.

The application discloses a control cabinet intelligent reconstruction method based on a standard communication protocol and relates to the technical field of industrial automation, and comprises the following steps: real-time scanning of communication port data of bottom-layer equipment in a control cabinet and loading of mutually independent drive containers based on equipment fingerprint features so as to establish physical connection; construction of a standardized semantic information model based on a mapping relationship between a physical address file and a semantic model; real-time monitoring of characteristic changes of data flow in a data acquisition process, dynamic segmentation of a data transmission channel and diversion of data to a real-time control channel or a telemetry archiving channel. The application can update state attributes based on a semantic model in real time, form an organic whole of perception, decision, execution and verification, effectively solve the problems of protocol closure, semantic loss and low integration efficiency in traditional control cabinet reconstruction and improve the interoperability and intelligent level of an industrial control system.

An embodiment of the present application provides a storage system and an information processing system capable of reducing the processing cost of data mapping that manages the validity of data written into a nonvolatile memory. According to an embodiment, the storage system is provided with a nonvolatile memory and a controller. The controller controls the nonvolatile memory according to an instruction from a host. The controller manages the validity of data on the nonvolatile memory using data mapping. The data mapping includes a plurality of first segment tables. The plurality of first segment tables each hold first information and second information, the first information indicating the validity of each of pieces of data of a prescribed size that is data written into a range of physical addresses within the nonvolatile memory allocated to the first segment table, the second information indicating the validity of a plurality of pieces of data of the prescribed size in a predetermined number of entries.

This application relates to an inter-card communication method, a data processing unit, a network interface card (NIC), a medium, and a product. The data processing unit includes a first physical functional device (PVM). The first BAR space of the first PVM includes at least the physical address of the second PVM of the first NIC, a first transmit queue producer pointer, a first transmit queue consumer pointer, and a first data buffer to be transmitted. The inter-card communication method includes: the data processing unit acquiring first data to be transmitted; writing the first data into the first data buffer to be transmitted according to the first transmit queue producer pointer value and the first transmit queue consumer pointer value; updating the first transmit queue producer pointer value according to the storage location of the first data; and writing the updated first transmit queue producer pointer value into the first NIC according to the physical address of the second PVM to notify the first NIC to read the first data. This application enables high-bandwidth transmission between the DPU and the NIC.

This application provides a method, electronic device, and storage medium for obtaining memory access permissions. The method includes: checking the management domain to which the transaction belongs and the physical address accessed based on permissions; performing a multi-level MTT cache parallel lookup operation to obtain the hit results of the multi-level MTT cache; and determining the memory access permissions based on the hit results of the multi-level MTT cache. The memory access permission acquisition method of this application first caches the multi-level page table results of IO-side device transactions under a specific management domain. In subsequent access permission checks, a multi-level page table cache parallel lookup strategy replaces the traditional serial page table process, allowing IO-side device transactions to simultaneously determine the hit results of the multi-level page table cache and obtain access permissions based on the hit results. This strategy not only significantly improves the speed of permission checks but also reduces the frequency of memory access and bandwidth consumption. Furthermore, it efficiently adapts to access scenarios of IO-side devices in different management domains, further improving the overall efficiency of permission checks.

This application is directed to accessing data in a memory system of an electronic system. The memory system a storage-side DRAM and one or more memory channels. The memory system receives a memory access request for target data stored in the memory system, and the memory access request includes a target virtual address of the target data. In response to the memory access request, the memory system searches a page table of the storage-side dynamic random-access memory (DRAM) for a target physical address mapped to the target virtual address of the target data. The page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses of the storage-side DRAM. Based on a search result, the memory system extracts the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address.

Memory devices can be protected (e.g., repaired) against hard bit errors by remapping logical pages to valid physical addresses and excluding those physical addresses having hard bit errors from being mapped to. The remapping can be done in unit of a finer granularity than a row of memory cells such that those valid memory cells within a row can still be used for the remapping despite that the row may include unusable memory cells.

The application provides a distributed memory pool memory batch allocation method and system. The method comprises the following steps: receiving a batch allocation request containing a number of slot positions, obtaining a CPU core identifier of a current thread; performing an atomic addition operation on a tail pointer of a corresponding logical shard in a single allocator according to the CPU core identifier, locking a continuous slot position interval, the single allocator being divided into a plurality of logical shards, each logical shard corresponding to a CPU core, each logical shard maintaining an independent tail pointer, the tail pointer being an atomic variable recording the highest bit offset of the allocated logical shard; updating the bit state of the corresponding slot position interval in the bitmap of the single allocator, completing the batch continuous slot position allocation and returning the continuous physical address corresponding to the slot position interval. The method realizes lock-free allocation to reduce the allocation delay under high concurrency, guarantees the global reuse of free slot positions, and maintains a high memory utilization rate.

The application provides a self-adaptive solid state disk power failure protection method and device. The method comprises the following steps: after triggering power failure, firstly, the physical address of the data to be persisted in the volatile cache is directly determined by calculation based on a pre-stored linear mapping relationship, so as to eliminate the energy consumption and delay of traditional traversal search; secondly, the real-time available energy of the energy storage array is obtained and compared with a preset energy demand threshold; the energy demand threshold is obtained based on load prediction; if the energy is insufficient, part of the data subset is abandoned to be written according to the dynamically generated data priority order; finally, the selected data subset is written into the non-volatile storage medium according to the calculated physical address. The application significantly improves the power failure protection success rate and system energy efficiency.

Embodiments of the present application provide a memory management method and device, and relate to the technical field of computers. The method comprises: receiving a continuous memory allocation request sent by a first CPU core, the continuous memory allocation request comprising a first number of pages; querying a bitmap of a continuous memory allocation area to obtain a first number of page frame numbers, the first number of page frame numbers corresponding to free memory pages with consecutive physical addresses, and the value of each bit in the bitmap indicating whether the corresponding memory page in the continuous memory allocation area is free or used; from a clean cache pool, reclaiming the memory pages corresponding to the first number of page frame numbers; allocating the reclaimed memory pages to the first CPU core and setting the value of the bit corresponding to the reclaimed memory pages in the bitmap to a value indicating that the memory pages are used. The scheme can reduce memory allocation delay, improve the control accuracy of memory allocation operations, and enhance memory security.

The embodiment of the invention provides a data processing method and device, electronic equipment and a storage medium. The method comprises the following steps: receiving a data read-write request carrying logic block index information, wherein the logic block index information is used for indicating a target logic block to which target data belongs; according to the logic block index information, obtaining the physical address offset of the target logic block in the physical storage space through the data index interface; on the basis of the physical address offset, reading or writing of target data is executed in a physical storage space, the physical storage space is used for storing data in at least one logic block, and multiple logic blocks with continuous indexes are mapped to discontinuous physical address areas in the physical storage space; the data index interface is constructed based on a logic block data arrangement mode. According to the method, a uniform data index interface is provided, so that a logic block physical address corresponding to a logic block index identifier is supported to be accurately obtained, and the method is adaptive to the situation that physical and logic arrangement sequences are inconsistent under a specific storage architecture.

The application relates to the technical field of electric digital data processing, and discloses a big data fast indexing and querying system based on general surgery diagnosis and treatment characteristics, which comprises a data stream acquisition module, a topological sequence reorganization module, a physical space mapping module, an index key synthesis module and a preloading execution engine; the topological sequence reorganization module analyzes heterogeneous diagnosis and treatment data streams and reorganizes the data streams into logically continuous patient whole-course data aggregates; the physical space mapping module sequentially maps the aggregates to a continuous physical address space of a bottom-layer storage; the index key synthesis module generates composite index items according to physical address offsets among data blocks; and the preloading execution engine drives the bottom-layer storage to burst read, the application converts cross-modal diagnosis and treatment correlation queries into one-way sequential reading of the storage, reduces the track delay and access overhead in the searching process, and guarantees the searching response delay certainty under the condition that the data volume continuously grows.

The application discloses a load sharing table entry generation method, an electronic device and a readable storage medium, and belongs to the technical field of communication. The load sharing table entry generation method comprises the following steps: receiving, through a first interface of a first device, first signaling sent by a second interface of a second device, wherein the first signaling carries a physical address and a virtual address of the second interface, the second device is a neighbor node of the first device, and the virtual addresses carried in at least two first signalings received by a plurality of first interfaces are the same; and generating a load sharing table entry according to the first signaling, wherein the load sharing table entry comprises a load sharing entry corresponding to each first interface, a next-hop virtual address of the load sharing entry is the virtual address carried in the first signaling received by the corresponding first interface, and a next-hop physical address of the load sharing entry is the physical address carried in the first signaling received by the corresponding first interface.