1414 results about "Physical address" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

A key-value cache management system processes inference requests of a generative model. An inference request requests a starting virtual memory address and a number of layers in the generative model. In response to receiving an inference request, contiguous virtual memory space is reserved for the key-value cache in accordance with the inference request by assigning the starting virtual memory address in the key-value cache and calculating memory pointers for each layer in the model and each block so that the one or more blocks are written sequentially. The generated memory pointers are outputted to the generative model so that each self-attention layer writes computed key-value pairs at physical addresses in the key-value cache specified by the memory pointers.

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

The invention discloses an address mapping method in DPU local storage virtualization, which comprises the following steps: a virtual machine calls a system call interface provided by an address mapping configuration management module on a host side to perform mapping configuration of a virtual machine physical address and a host physical address, and issues the virtual machine physical address and length to a virtual address mapping module of a DPU; the virtual address mapping module manages global direct memory access address resources, firstly allocates a global direct memory access address on a host side, then maps a virtual machine physical address to the allocated global direct memory access address in a mapping page table of the DPU, and returns the virtual machine physical address to the address mapping configuration management module; and the address mapping configuration management module obtains the distributed global direct memory access address, and maps the distributed global direct memory access address to a host physical address in the IOMMU. According to the method, by optimizing address mapping, the efficient and flexible local storage virtualization service can be realized while the data reliability is ensured.

According to the system memory management method and system, the electronic equipment and the storage medium provided by the invention, the virtual address information in the access information is extracted, and the virtual address information comprises the target virtual address; under the condition that the target virtual address is determined to be in a first preset virtual address range according to the virtual address information, determining an initial physical address corresponding to an initial virtual address in the first preset virtual address range according to a preset address mapping table; performing physical address calculation processing according to the target virtual address, the initial virtual address and the initial physical address to obtain a target physical address corresponding to the target virtual address; and accessing a system memory based on the target physical address and performing memory management on the system memory. By quickly returning the conversion relation from the virtual address to the physical address in the specified range, the conversion efficiency from the virtual address to the physical address can be improved, a conversion page table does not need to be configured according to MMU granularity, waste of storage space can be reduced, and the address conversion efficiency can be improved.

The invention provides a solid state disk testing method and device, equipment and a medium, and relates to the technical field of hard disk detection. The test method comprises the following steps: in a process of writing data into physical areas of a to-be-tested solid state disk according to a physical address in sequence, randomly selecting at least part of areas from the physical areas written with the data at a preset time interval to perform reset operation until the physical areas reach a target area state, the target area state comprises a target filling state and a target fragmentation state; executing a read-write test on the physical region in the target region state to obtain test data; and generating a test report based on the test data.

The invention provides a DPU (Data Processing Unit)-based RDMA (Remote Direct Memory Access) virtualized memory address conversion and data transmission method and a DPU-based RDMA virtualized memory address conversion and data transmission system. The method comprises the following steps that: a user process specifies a client virtual address and a corresponding memory The virtual machine kernel generates a first memory conversion table, and the first memory conversion table records conversion from the client virtual address to the client physical address. When the drive program of the remote direct memory access device obtains the first memory conversion table, a preset instruction is triggered to enable the execution control right to be switched to the virtual machine supervision program from the virtual machine kernel. The customer physical address is converted into the host virtual address in the switching process. The virtual machine supervision program obtains mapping from the host virtual address to the host physical address through the host system information, and a second memory conversion table containing the conversion relation from the client virtual address to the host physical address is obtained. The execution control right is switched back to the kernel of the virtual machine, and the second memory conversion table is configured to the remote direct memory access device DPU. According to the method, address conversion can be simplified, hardware dependence is reduced, and RDMA performance is improved.

The invention discloses a memory allocation method and device, electronic equipment and a nonvolatile storage medium, and is applied to the technical field of storage. The method comprises the steps that in the memory initialization process, a corresponding application program special memory is applied according to a reserved memory configuration file, and the application program special memory is assembled into a continuous memory space in the mode that physical addresses are continuous and belong to the same memory device; in the user mode, assembling the continuous memory space to generate a user mode memory structure according to memory mapping information of the continuous memory space mapped to the user mode under the triggering of the memory application request; when a memory calling request sent by the target application program in the initialization process is detected, a matched target memory is applied for the target application program from the user mode memory structure, and the target memory is cached into the process space to be used by the target application program. According to the invention, the problem that memory application is caught in a kernel mode in related technologies can be solved, and the memory allocation efficiency is effectively improved.

Embodiments for communicating between first and second hosts according to CXL.mem and CXL.cache protocols. A computer translates a CXL.mem M2S RwD with a Tag, received by a CXL Type 2 or Type 3 device (EP1) from the first host, to a CXL.cache D2H Req with a CQID. A CXL Type 1 or Type 2 device (EP2) sends the D2H Req to the second host, and receives a CXL.cache H2D Rsp with the CQID and a UQID. EP1 sends a CXL.mem S2M NDR with the Tag to the first host, and EP2 sends a CXL.cache D2H Data message with the UQID to the second host. Optionally, EP1 receives and terminates CXL.io / PCIe Configuration Request TLPs from the first host, the M2S RwD further includes a first physical address and Data, and the D2H Req further includes a second physical address.

The invention discloses a memory management method, a program product, equipment and a medium, and relates to the technical field of computers.The memory management method comprises the steps that memory configuration information in the system kernel starting process is obtained, and a reserved memory range is determined based on the memory configuration information; segmenting the reserved memory based on the hot plug framework of the memory and the reserved memory range; allocating corresponding target metadata to each reserved memory segment to obtain a configured physical memory; the target metadata is metadata representing a data structure of the physical memory page; establishing a target mapping array based on the memory configuration information; the target mapping array is used for recording a mapping relation between a physical address and a logic page number in the configured physical memory; responding to the target memory access request by utilizing the target mapping array, and completing corresponding memory access operation; the target memory access request is an access request initiated for the reserved memory, so that the universality of the reserved memory is improved, the overall manageability of the system is enhanced, and the complexity and maintenance burden of the system are reduced.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

The invention provides a remote direct memory access system, equipment and a cluster. The system comprises the following steps: a remote direct memory access device sends a first address conversion request to a host under the condition that a first physical address corresponding to a first virtual address does not exist; the host queries a first physical address corresponding to the first virtual address in a memory of the host according to the first address translation request, and returns a translation failure response to the remote direct memory access device under the condition that the first physical address corresponding to the first virtual address cannot be queried; the remote direct memory access device sends a page request to the host based on the conversion failure response; the host migrates data corresponding to the first virtual address from a hard disk of the host based on the page request and locks the data in a memory of the host, and returns a page request response; and the remote direct memory access device stores the corresponding relationship between the first virtual address and the first physical address into an address translation list based on the page request response.

An apparatus comprises request receiving circuitry to receive a given memory system request specifying a target address in a given physical address space and a target memory encryption context identifier (MECID) indicative of a selected memory encryption context associated with the memory system request. Snoop filtering circuitry determines whether a snoop request is to be transmitted to a given caching agent in response to the given memory system request. The snoop filtering circuitry determines, based on the target MECID of the given memory system request and on snoop filtering information associated with the given caching agent, whether the target MECID is a snoop-not-required MECID for the given caching agent. In response to determining that the target MECID is a snoop-not-required MECID for the given caching agent, the snoop filtering circuitry suppresses transmission of a snoop request to the given caching agent in response to the given memory system request.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.

The invention relates to a video memory management method and device, electronic equipment and a storage medium, the method is applied to a GPU drive in a virtual machine, and the method comprises the steps that when it is detected that the remaining amount of a GPU video memory is lower than a set remaining amount threshold value, cold pages in a GPU page table are recognized; wherein the cold page is a page table item which is not accessed in a recent preset time interval; and under the condition that the cold page is a video memory, replacing a physical address corresponding to the virtual address in the cold page to a physical address in a system memory so as to replace video memory data corresponding to the cold page to the system memory. The embodiment of the invention can improve the overall utilization rate of the video memory.

Apparatus, method and code for fabrication of an apparatus. The apparatus comprises address translation circuitry (116) to translate virtual addresses to physical addresses in response to advance address translation requests issued by devices (105) on behalf of software contexts (125). The apparatus also comprises translated access control circuitry (117) to control access to memory (110) in response to translated access requests issued by the devices (105) on behalf of the software contexts (125), based on permissions information defined in a device permission table (220), wherein the corresponding access permissions provide information for checking whether translated access requests from a plurality of software contexts are prohibited.

The invention discloses a traceability application-oriented block chain database data management system, particularly relates to the technical field of block chain database data management, and is used for solving the problems of easy data tampering and low verification efficiency caused by traceability data logic association and physical storage splitting. The method comprises the following steps: firstly, matching a parent physical sector offset through an association analysis module, determining a storage partition, and assembling a write-in instruction; then, a topology binding module executes a disk write operation, synchronously reads parent node hash and performs combinatorial operation in combination with a physical address to generate a topology binding check value bound with the physical position; the aggregation anchoring module uses a Merkel tree aggregation check value to generate a root fingerprint and perform uplink, and establishes an anchoring voucher; and finally, a path verification module positions a physical position according to the certificate, executes reverse recursive addressing and step-by-step Hash recalculation, and assembles a pedigree verification packet, so that a closed-loop trust system from physical storage to chain certificate storage is constructed, and the tamper-proof capability and verification efficiency of the traceability data are improved.

The present application discloses a method, system, and computer system for performing failovers of traffic carrying devices. The method includes (i) generating, by one or more processors a virtual routing IP address that is common to a plurality of network nodes, and (ii) sending to an upstream device a physical IP address for a particular network node of the plurality of network nodes, wherein the physical IP address is sent as metadata in a packet to the upstream device.

The invention discloses a U.2 interface-based server intelligent integrated hierarchical storage system and method, relates to the technical field of computer server storage, and is used for solving the problem of optimization of multi-type SSD data access efficiency and storage resource utilization rate. Firstly, a multi-protocol parallel channel is established by redefining U.2 interface reserved pins, signal integrity parameters are monitored in real time and fused with equipment I / O access features, and an I / O feature sequence of physical layer state information is generated; then, based on a time sequence convolutional neural network, extracting access mode multi-scale features, calculating a data block access heat probability, mapping and determining a target storage hierarchy, and generating a scheduling instruction containing a source physical address, the target hierarchy and a migration priority; the migration execution module realizes zero-copy migration of the data block between the shared DRAM pool and the SSD according to the instruction; and the resource coordination module monitors system load in real time, dynamically adjusts migration concurrency and an I / O sampling strategy, and realizes self-adaptive optimization of storage performance and resource utilization.

The invention discloses a server system based on a public cloud technology and an access method thereof, and belongs to the technical field of cloud services. The server system comprises a server and an external device inserted in the server. A virtual machine manager in the server is used for providing a virtual external device and a virtual memory for a virtual machine in the server, the virtual external device is obtained through device simulation based on the external device, and the virtual memory is obtained through device simulation based on a memory configured for the external device. The virtual device driver of the virtual external device is used for sending an access request carrying the target GPA to the external device when the virtual external device accesses the target GPA of the virtual memory. And the external device is used for obtaining a target host physical address corresponding to the target client physical address based on the access request, obtaining target data recorded by the target host physical address, and sending the target data to the virtual device driver. According to the invention, the address translation performance of the server system is effectively improved.

The invention discloses a memory fault processing method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers.The method comprises the steps that when a memory line fault exists in a memory of a target system, an isolation operation is triggered for a target physical address, the target physical address at least comprises the physical address of the fault line with the memory line fault in the memory, the technical problem of system downtime caused by the fact that the memory line fault cannot be rapidly processed in the related technology is solved, the isolation process is started for the target physical address in time when the memory line fault is detected, and the system downtime is reduced. Performance reduction and data error accumulation caused by the fact that the fault line continues to participate in data reading and writing are avoided, and then the technical effect of reducing the risk of system downtime is achieved.

The present disclosure relates to a computing system, a PCI device manager and an initialization method thereof. The PCI device manager is used to realize peer-to-peer data transmission between PCI devices, and the PCI device manager includes: a DMA engine module that realizes data and command communication with a host and a PCI device through DMA; a device memory; a memory mapping module that maps a data cache space of the device memory to a physical address space of the host memory, so as to perform data communication and / or command communication with the PCI device via the DMA engine module in a running process; and a processor that sends a PCI device configuration instruction to the host through the DMA engine module, and creates PCI device objects respectively for PCI devices discovered by the host.

The invention discloses a memory management method, device and equipment and a computer readable storage medium. The method comprises the following steps: when a mapping request exists, determining a target I / O virtual address corresponding to the mapping request and triggering an application identity identifier of the mapping request; detecting whether the target I / O virtual address is associated with the application identity label or not; and if yes, establishing mapping between the target I / O virtual address and the corresponding memory physical address. According to the method and the device, the memory protection capability of the equipment can be enhanced on a system without IOMMU (Input / Output Management Unit); and the complexity of hardware design can be reduced on a system with an IOMMU, and the hardware cost is reduced.

Instead of a system that does not address host buffer fragmentation or saturation, utilize a different metric for command prioritization. Commands are re-ordered and prioritized based on the number of outstanding host buffers that will be released on command completion, thereby limiting and / or reducing the physical address fragmentation and host memory overhead. Command processing priority will take the number of host memory page segments represented by the command into consideration.

The invention relates to a memory isolation method and device, a server, a storage medium and a program product. The method comprises the steps that firstly, a memory address of a target memory where single-bit errors occur multiple times is obtained from a preset storage space which can be jointly accessed by an operating system and a BIOS, then, a physical address corresponding to the target memory is determined based on the memory address, the physical address is written into the storage space, and finally, indication information is generated, the indication information is used for indicating the CPU to perform memory isolation on the target memory according to the physical address in the process of running the kernel program. The method can be applied to a platform in which the physical address of the target memory cannot be directly obtained when the CPU runs the operating system, and the application range is wider.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

The invention discloses a data scheduling and control method based on mainboard memory straight-through, and relates to the technical field of computer hardware, the method comprises the following steps: pre-allocating a straight-through memory area for mounting equipment in a firmware initialization stage, establishing a mapping relation between equipment identification and a physical address of an exclusive memory segment, and through address translation and access control rules of a firmware layer, the device bypasses a system cache level and accesses the exclusive memory segment in a direct memory access mode. Constructing a firmware scheduling table based on the mapping relation to manage access requests of all devices, monitoring transmission delay in real time, and dynamically adjusting priority weight and bandwidth allocation in the scheduling table according to a monitoring result; and sequencing the requests according to the updated scheduling table to complete scheduling and control of the memory access behavior of the equipment. According to the method and the device, the delay bottleneck caused by multi-level copying and firmware scheduling lag in mainboard data forwarding is effectively solved.

The invention discloses an accelerator card resource sharing system, method and device and electronic equipment, and relates to the technical field of accelerator cards, the system comprises an address mapping module and a memory copying engine module, the address mapping module is used for receiving an access request of an accelerator card video memory of a source host, querying a mapping relation of virtual addresses in a dynamic mapping table and copying the virtual addresses to the source host; the memory copy engine module generates target label information for identifying a target data packet transmitted across hosts, the dynamic mapping table reflects a mapping relation between a source host virtual address and a target host accelerator card physical address, and the memory copy engine module copies the target data packet according to the transmission priority and sequence information of the target data packet contained in the target label information. And executing cross-host data transmission to ensure that the data is efficiently transmitted to an accelerator card video memory of a target host. According to the embodiment of the invention, the problems of relatively high delay and insufficient flexibility in coping with the complex demand of acceleration card cluster sharing in the prior art are effectively solved.

A memory device includes a memory module including a normal memory area and a swap memory area, and a memory processing unit. The swap memory area is configured to store swapped-out data. The memory processing unit is configured to provide a host with physical address information corresponding to an additional memory area determined based on a size of the swapped out data and the normal memory.

The invention discloses a cache security defense method and system based on RI SC-V. The method comprises the steps that when an RI SC-V processor executes a target data loading instruction of a target request component, a target physical address in the target data loading instruction is extracted; encrypting the target physical address through a physical address encryption module to obtain a target encrypted address; and accessing a security data cache in the security cache module according to the target encrypted address, and if a target cache line corresponding to the target encrypted address exists in the security data cache, outputting the target cache line to the target request component, so that the target request component executes a target data operation on the target cache line. According to the method and the device, the channel attack on the cache side can be effectively resisted, the performance of the cache in the RI SC-V processor is improved, the information security guarantee level is improved, the potential information leakage risk is reduced, and the method and the device can be widely applied to the technical field of data security.