903 results about "Physical address" patented technology

The invention discloses an android container rendering optimization method based on cross-domain hard real-time Fen synchronization, which comprises the following steps: by taking a swan-mong system as a host and an android system as a container, creating a hash table, a synchronous thread and a shared memory corresponding to a GPU core when the host is started, acquiring VSync cycle registration callback, transmitting shared memory FD to the container, and finishing shared memory mapping and alignment by the container. Registering a GPU queue to complete callback; when the Android application is started, a container obtains a queue and a physical address of a rendering buffer area, creates a Fen and binds the Fen to the queue, after the queue is submitted, metadata is written into a shared memory to inform a host, after the host receives the metadata, nodes are created and stored in a hash table, and an overtime timer is registered; after the GPU completes the command queue, the container calls back an update state and a verification value to notify the host, and after the host is verified to be valid, the corresponding hash table is updated, the timer is reset, and asynchronous screen loading is triggered; and the host executes buffer area synthesis and submission of the display equipment to finish on-screen, so that the stability of the rendering frame rate is improved, and the reliability of cross-domain synchronization is ensured.

The invention relates to a video memory management method and device, electronic equipment and a storage medium, the method is applied to a GPU drive in a virtual machine, and the method comprises the steps that when it is detected that the remaining amount of a GPU video memory is lower than a set remaining amount threshold value, cold pages in a GPU page table are recognized; wherein the cold page is a page table item which is not accessed in a recent preset time interval; and under the condition that the cold page is a video memory, replacing a physical address corresponding to the virtual address in the cold page to a physical address in a system memory so as to replace video memory data corresponding to the cold page to the system memory. The embodiment of the invention can improve the overall utilization rate of the video memory.

The invention discloses a traceability application-oriented block chain database data management system, particularly relates to the technical field of block chain database data management, and is used for solving the problems of easy data tampering and low verification efficiency caused by traceability data logic association and physical storage splitting. The method comprises the following steps: firstly, matching a parent physical sector offset through an association analysis module, determining a storage partition, and assembling a write-in instruction; then, a topology binding module executes a disk write operation, synchronously reads parent node hash and performs combinatorial operation in combination with a physical address to generate a topology binding check value bound with the physical position; the aggregation anchoring module uses a Merkel tree aggregation check value to generate a root fingerprint and perform uplink, and establishes an anchoring voucher; and finally, a path verification module positions a physical position according to the certificate, executes reverse recursive addressing and step-by-step Hash recalculation, and assembles a pedigree verification packet, so that a closed-loop trust system from physical storage to chain certificate storage is constructed, and the tamper-proof capability and verification efficiency of the traceability data are improved.

The present application discloses a method, system, and computer system for performing failovers of traffic carrying devices. The method includes (i) generating, by one or more processors a virtual routing IP address that is common to a plurality of network nodes, and (ii) sending to an upstream device a physical IP address for a particular network node of the plurality of network nodes, wherein the physical IP address is sent as metadata in a packet to the upstream device.

The invention discloses a U.2 interface-based server intelligent integrated hierarchical storage system and method, relates to the technical field of computer server storage, and is used for solving the problem of optimization of multi-type SSD data access efficiency and storage resource utilization rate. Firstly, a multi-protocol parallel channel is established by redefining U.2 interface reserved pins, signal integrity parameters are monitored in real time and fused with equipment I / O access features, and an I / O feature sequence of physical layer state information is generated; then, based on a time sequence convolutional neural network, extracting access mode multi-scale features, calculating a data block access heat probability, mapping and determining a target storage hierarchy, and generating a scheduling instruction containing a source physical address, the target hierarchy and a migration priority; the migration execution module realizes zero-copy migration of the data block between the shared DRAM pool and the SSD according to the instruction; and the resource coordination module monitors system load in real time, dynamically adjusts migration concurrency and an I / O sampling strategy, and realizes self-adaptive optimization of storage performance and resource utilization.

The invention discloses a memory management method, device and equipment and a computer readable storage medium. The method comprises the following steps: when a mapping request exists, determining a target I / O virtual address corresponding to the mapping request and triggering an application identity identifier of the mapping request; detecting whether the target I / O virtual address is associated with the application identity label or not; and if yes, establishing mapping between the target I / O virtual address and the corresponding memory physical address. According to the method and the device, the memory protection capability of the equipment can be enhanced on a system without IOMMU (Input / Output Management Unit); and the complexity of hardware design can be reduced on a system with an IOMMU, and the hardware cost is reduced.

The invention discloses a data scheduling and control method based on mainboard memory straight-through, and relates to the technical field of computer hardware, the method comprises the following steps: pre-allocating a straight-through memory area for mounting equipment in a firmware initialization stage, establishing a mapping relation between equipment identification and a physical address of an exclusive memory segment, and through address translation and access control rules of a firmware layer, the device bypasses a system cache level and accesses the exclusive memory segment in a direct memory access mode. Constructing a firmware scheduling table based on the mapping relation to manage access requests of all devices, monitoring transmission delay in real time, and dynamically adjusting priority weight and bandwidth allocation in the scheduling table according to a monitoring result; and sequencing the requests according to the updated scheduling table to complete scheduling and control of the memory access behavior of the equipment. According to the method and the device, the delay bottleneck caused by multi-level copying and firmware scheduling lag in mainboard data forwarding is effectively solved.

The invention discloses an accelerator card resource sharing system, method and device and electronic equipment, and relates to the technical field of accelerator cards, the system comprises an address mapping module and a memory copying engine module, the address mapping module is used for receiving an access request of an accelerator card video memory of a source host, querying a mapping relation of virtual addresses in a dynamic mapping table and copying the virtual addresses to the source host; the memory copy engine module generates target label information for identifying a target data packet transmitted across hosts, the dynamic mapping table reflects a mapping relation between a source host virtual address and a target host accelerator card physical address, and the memory copy engine module copies the target data packet according to the transmission priority and sequence information of the target data packet contained in the target label information. And executing cross-host data transmission to ensure that the data is efficiently transmitted to an accelerator card video memory of a target host. According to the embodiment of the invention, the problems of relatively high delay and insufficient flexibility in coping with the complex demand of acceleration card cluster sharing in the prior art are effectively solved.

The invention discloses a memory access method based on a memory expansion controller, a memory expansion card and equipment, and relates to the technical field of computers, and the method comprises the following steps: carrying out twice address mapping on a target access address in a memory read-write instruction through the pre-created memory expansion controller, the target access address is mapped to a hard disk storage space from a processor memory physical address space, whether the mapped access address is hit in a preset cache space or not is judged, and if the mapped access address is hit, read-write operation is directly conducted on corresponding target data in the preset cache space; and if not, performing read-write operation on the corresponding target data in the solid state disk. By means of the mode, the solid state disk can be used as the extended memory of the host, the memory extension cost is remarkably reduced, ultra-large-capacity memory extension can be achieved, accordingly, the memory access cost is reduced, and meanwhile the access speed is taken into account in the mode of presetting the cache space.

A system and method for providing reliable, legally compliant access to geographically restricted ATSC television signals via user-owned devices hosted in a datacenter. The invention verifies the physical address of each applicant to ensure eligibility within the designated market area before installation. It eliminates the need for rooftop or indoor antennas, resolving common ATSC reception challenges, including interference, terrain obstruction, and lightning risks. Designed for ease of use by non-technical users, the system provides consistent high-quality reception through a managed datacenter infrastructure. The invention complies with legal boundaries set by the U.S. Supreme Court's ruling in ABC v. Aereo by ensuring individualized device ownership and avoiding centralized retransmission. An optional encrypted group addressing mode further reduces energy and hardware redundancy while enforcing regional access through a conditional access system with access limited to persons with validated addresses and members of the datacenter.

The invention relates to the technical field of signal processing, and discloses a multichannel data acquisition system and method based on an FPGA (Field Programmable Gate Array), an acquisition module drives a global counter by using a global synchronous clock, writes acquired data into an annular buffer area with a physical address and a counter value in a linear mapping relationship, and establishes implicit time index storage. When a trigger event occurs, the system broadcasts the locked global trigger timestamp, and the acquisition module backtracks and reads historical data according to the global trigger timestamp, and packages the historical data into a sparse matrix type data packet in combination with the channel validity mask. And after receiving the data packet, the data processing module directly calculates a memory mapping address by using global time information in the data packet, and writes a data load into a corresponding position of the waveform reconstruction buffer area. According to the method, through strict binding of the physical address and the absolute time, independent time label redundancy is eliminated, high-precision synchronization of distributed multiple channels is ensured, and out-of-order automatic in-situ recombination and efficient waveform reconstruction of data of a receiving end are achieved.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

The invention provides an address mapping method and device, equipment, a storage medium and a program product. The address mapping method comprises the following steps: acquiring a physical address field through a physical address field acquisition interface; generating a virtual address through the virtual address generation interface according to a preset virtual address field; and mapping the virtual address to a physical address in the physical address field through an address mapping interface.

The invention discloses a traffic incident detector system based on a domestic intelligent DSP and a detection method. The system comprises a video acquisition unit, a data exchange and storage unit, an intelligent processing core and a communication interaction unit. The intelligent processing core adopts a heterogeneous SoC chip integrating a multi-core DSP, an NPU and an FFT hardware acceleration module, the FFT module is responsible for video frame frequency domain enhancement, the NPU runs a deep learning model to carry out target detection, and the multi-core DSP executes multi-target parallel tracking and event judgment. And the data exchange and storage unit supports direct carrying of data among the modules through a unified physical address space and a DMA mechanism. The method comprises the following steps: carrying out NPU target detection on a video subjected to environment self-adaptive preprocessing; a multi-core DSP is used for tracking a target in parallel and judging an event; and finally, alarm information is generated and reported. Through heterogeneous hardware division and software and hardware cooperation, high-real-time and high-precision edge analysis is realized, and the detection reliability is improved.

The invention discloses a memory allocation method and device for a direct access memory device, and relates to the technical field of servers. The method comprises the following steps: in response to a memory access request of a user process, allocating virtual address information to the user process; obtaining a physical address range of the direct access memory device, wherein the physical address range comprises physical address sub-regions corresponding to a plurality of memory channels respectively; establishing an interleaving mapping relationship between the virtual address information and physical address sub-regions corresponding to the memory channels respectively; and writing an interleaving mapping relationship between the virtual address information and the plurality of physical address sub-regions into a page table, and processing a memory access request of the user process according to the interleaving mapping relationship in the page table. The method can improve the memory access speed of the server.

The invention discloses an SSD B + tree indexing method and system based on wear leveling, and relates to the technical field of database indexing structure optimizing.The method comprises the steps that B + tree logic nodes and SSD physical addresses are decoupled, and a dynamic node mapping table is introduced; replacing local updating with additional updating, and writing the new version of the node into a new position of the SSD; when a write-in address is allocated to the node, an allocation strategy considering a block wear state is adopted, and write operation is guided to an area with relatively light wear; during garbage collection, high-wear blocks are preferentially treated to integrate wear. According to the method, the problems of writing hot spots and unbalanced abrasion of the B + tree on the SSD are effectively solved on the database software level, the service life of the SSD can be remarkably prolonged while the high performance of the B + tree is kept, and the method has very high universality and practical value.

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention relates to a data processing method and device and a computer program product. The method comprises the steps of determining a physical address of a target file fragment on a storage medium; determining a target file record of the target file fragment from the metadata file, and determining a physical address of the target file record on a storage medium; and moving the target file fragment and the target file record to a target position of the storage medium based on the physical address of the target file fragment and the physical address of the target file record. Therefore, the I / O operation of the storage medium does not need to search and read the file fragments and the file records back and forth at a plurality of dispersed positions, so that the track seeking time and the data transmission delay of the storage medium are greatly reduced, and the problem of low I / O efficiency of the storage medium caused by file dispersion is directly solved; the scattered distribution state of the files and the file records on the storage medium is changed, and the layout of the files and the file records on the storage medium is optimized, so that the read-write efficiency of the storage medium is improved, and the hardware performance is brought into full play.

The embodiment of the invention relates to an electricity meter data complementary reading method, which is applied to a concentrator terminal and comprises the following steps: sending a data reading instruction to all electricity meters according to a preset physical address sequence at the beginning of each preset meter reading period; if the effective collection data fed back by the electricity meter is not received within the preset overtime threshold value, establishing a collection missing queue according to the electricity meter information, the data information and the time information; and in the current meter reading period, after the current round of data acquisition is completed, calculating the residual idle time of the current meter reading period and the estimated single-time additional reading time consumption, and performing data additional reading according to the residual idle time of the current meter reading period and the estimated single-time additional reading time consumption. According to the technical scheme provided by the embodiment of the invention, the data which is not successfully acquired is subjected to supplementary reading by utilizing the remaining time of the current meter reading period and the subsequent meter reading period, a layered priority supplementary reading mechanism is provided, the timeliness and fairness of data supplementary reading are considered, and the loss risk of long-term missing acquisition of data can be avoided.

Provided is a system and method for memory pool management, the method including receiving, by a first control circuit of a memory device controller, a first request to create a first logical memory space, the first control circuit being associated with a first memory zone, based on determining that a first memory unit, at a first physical address range of the first memory zone is available, allocating the first memory unit to the first logical memory space, based on determining that a second memory unit of the first memory zone is occupied, sending a memory-donation request to a second control circuit of the memory device controller, the second control circuit being associated with a second memory zone, and based on determining that a third memory unit of the second memory zone is available, allocating the third memory unit to the first logical memory space.

The invention provides a strategy for an MCU to carry out automatic addressing on a proximity sensor. Constructing a preset address pool in the Flash; judging whether an effective physical address exists in a memory or not; if yes, taking the current effective physical address to carry out communication work; if not, the first slave equipment physical address is taken out from the top of the preset address pool, a read instruction is generated, and whether a slave equipment ACK response signal exists on the I2C bus or not is scanned; and if the slave equipment ACK response signal is received, the current slave equipment physical address is an effective address, the effective physical address is written into the memory, and the effective physical address is taken for communication. According to the invention, the problems of poor flexibility of the pairing mode of the MCU and the proximity sensor and high cost of replacing the proximity sensor in the prior art are solved.

Modem datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

Disclosed are a computing device for accessing a memory expander using a compute express link (CXL) interconnect and an operating method thereof. The computing device may include a processor, a memory, and a root complex configured to be connected with the processor, the memory, and a memory expander. The processor may recognize whether the memory expander is connected to the root complex. The processor may update a physical address space of the computing device based on a recognition that the memory expander is connected to the root complex.

The invention provides an online migration management method and device for database hotspot data and a medium, and belongs to the technical field of database migration. The method comprises the following steps: generating a hotspot object list based on hotspot statistical information collected in a preset time period; and according to the hot object list, determining a corresponding online migration task, and allocating the online migration task to a migration thread pool, so that the migration thread pool executes the online migration task based on preset migration strategies corresponding to different granularity levels. In response to an execution instruction of the online migration task, generating a corresponding hotspot object access mapping table, and configuring a preset access agent module to call the hotspot object access mapping table after performing access interception on a client request; and after a data access request from a client is received, determining a target access object corresponding to the data access request based on a preset access agent module, and forwarding the target access object to a corresponding data physical address. Through the method, the hotspot data management efficiency and the service continuity are improved.

Provided are systems, methods, and apparatuses for systems and methods for reducing latency of memory tiering devices. In one or more examples, the systems, devices, and methods include determining a number of pages in a first memory tier satisfies a threshold; based on the number of pages in the first memory tier satisfying the threshold, obtaining from an access log an access counter and a first physical address associated with a page of a second memory tier; translating the first physical address to a second physical address associated with a host; and modifying, based on the access counter, a counter field of a first data structure.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

The method comprises the following steps: S1, establishing a binding relationship between an identity code ID and a UWB tag physical address, and deploying a UWB positioning base station to construct a spatial topological graph; s2, arranging timing and circle counting devices on the starting line and the detection line; s3, a competition starting instruction is sent through the wireless command sender, and the timing and circle counting process is started through the timing and circle counting device; s4, performing joint verification on the identity code ID and the real-time coordinate by adopting an anti-cheating discrimination algorithm based on a space-time heterogeneous arbitration network; s5, generating a spatio-temporal data packet according to the accumulated number of turns of the athletes passing verification and the competition time, generating a hash value according to the spatio-temporal data packet, and uploading the hash value to the block chain evidence storage network; and S6, generating an anti-cheating analysis report based on the space trajectory and a final school report after the competition. According to the invention, automatic timing and circle counting management of middle and long distance race events is realized, the data accuracy and real-time performance are improved, cheating is effectively prevented and controlled, and the fairness and management efficiency of the race are guaranteed.

The embodiment of the invention provides a data writing method and device, a data reading method and device and electronic equipment, and relates to the technical field of data processing, the data writing method is applied to a first host, the first host runs a file system, the file system is mounted with memory equipment, and metadata of the file system is stored in the memory equipment. The memory device provides a shared memory for multiple hosts, the multiple hosts run file systems, and the data writing method comprises the steps that shared files are created in the file systems; based on the mapping relation between the virtual address of the first host and the physical address of the memory device, address information of the shared file is written into metadata stored in the memory device; and based on the mapping relationship and the address information of the shared file, writing the shared data in the memory device. According to the scheme, data sharing among a plurality of hosts can be realized.

The embodiment of the invention provides a video memory control method, device, equipment and system and a computer storage medium. The method comprises the steps that in response to an obtained drive upgrading request of an image processing unit (GPU), a before-upgrading page table corresponding to the GPU is obtained, and the before-upgrading page table comprises a mapping relation between a physical address and a virtual address of a GPU video memory; determining a data cleaning queue corresponding to the GPU, wherein the data cleaning queue is used for performing global cleaning on data in a GPU video memory; under the condition that the data cleaning queue is locked, driving upgrading operation is carried out on the GPU based on the driving upgrading request, an upgraded page table corresponding to the GPU is obtained, and the upgraded page table comprises a mapping relation between a physical address and a virtual address of a GPU video memory; and regulating and controlling data in the GPU video memory based on the pre-upgrading page table and the post-upgrading page table. In the embodiment of the invention, the driver upgrading operation of the GPU can be realized without operations such as video memory backup, shutdown, restart and the like.