331 results about "Host memory" patented technology

A Data Storage Device (DSD) includes a first memory storing reference files used to derive vector embeddings in a vector database. A query vector embedding is received from a host and one or more vector embeddings similar to the query vector embedding are identified in the vector database. One or more reference files from which the one or more vector embeddings were derived are identified and stored in a second memory for faster access. In another aspect, a query vector embedding is received by a host that identifies one or more vector embeddings that are similar to the query vector embedding and retrieves the one or more vector embeddings from a DSD to provide to an Artificial Intelligence (AI) model. One or more reference files are identified from which the one or more vector embeddings were derived and are prefetched from the DSD for storage in a host memory.

The invention provides an RDMA (Remote Direct Memory Access) message aggregation processing method and a network card device, which belong to the technical field of data communication, and comprise the following steps: S1, an RDMA message analysis step which comprises the links of hardware-level message capture, BTH header analysis and message classification and metadata generation; s2, an RDMA (Remote Direct Memory Access) caching step, wherein the step comprises a message descriptor recording link and a caching strategy link; s3, an RDMA message aggregation step, wherein the step comprises a context table aggregation step, an aggregation process step, a new aggregation process step and an existing context aggregation process step; s4, a zero-copy aggregation step, wherein the step comprises the links of metadata transmission, DMA delay processing and host memory writing; in order to solve the problem that stateless aggregation processing is not tried to be carried out on RDMA messages when an existing network card processes the RDMA messages, a plurality of received RDMA messages are aggregated into a larger RDMA message, and the larger RDMA message is sent to a downstream module for processing, so that the number of messages processed by a rear-stage module is reduced, and the bandwidth of the network card for processing the RDMA messages is improved.

The invention discloses a large language model semantic query acceleration method based on a sparse KV Cache index. The method comprises a KV Cache semantic pruning strategy based on an attention mechanism and a set of asynchronous pipeline reasoning architecture with overlapped calculation and I / O. According to the method, the attention sparsity characteristic of the large language model in the reasoning stage and the asynchronous transmission capacity between the Host memory and the GPU video memory are fully utilized, calculation redundancy and video memory occupation in repetitive semantic query are greatly reduced, and high-throughput, low-delay and high-performance batch semantic data processing service is provided. Through a mechanism for mapping a static text into a compressed semantic index and combining a prefix cache technology in a reasoning process to realize state multiplexing, high-performance reasoning acceleration and high-efficiency storage compression are provided for a data-intensive semantic analysis task in a resource-constrained environment.

The invention discloses a garbage collection optimization method and device, equipment and a medium. The invention relates to the technical field of solid state disks, which comprises the following steps that: a global invalid data bit chart is established in a host memory, each table item in the global invalid data bit chart corresponds to a physical block, and a bitmap bit in each table item corresponds to a physical page in the physical block; bit values corresponding to the bitmap bits comprise a first bit value and a second bit value; responding to a data updating event through an access acceleration engine so as to dynamically update the bit value of the corresponding physical page in the global invalid data bit graph; and when garbage collection is triggered, screening the physical page of which the bit value is the second bit value in a to-be-collected source physical block according to the global invalid data bit chart and the access acceleration engine to perform validity verification and data migration, and skipping the physical page of which the bit value is the first bit value. According to the invention, the garbage recycling efficiency is improved.

Modem datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

The invention discloses a communication transmission method, a product, electronic equipment and a medium, and relates to the technical field of storage. In the method, a host end determines a nonvolatile memory host controller interface specification protocol command according to address information of equipment managed by the host end, and sends the command to the equipment, so that any equipment can obtain address information of other equipment, which is the premise for realizing direct data transmission between the equipment; further, the host end determines an end-to-end data transmission instruction according to the address information of the source device and the address information of the target device, and sends the instruction to the source device. According to the method, under the condition that address information of other devices is stored in any device, end-to-end data transmission instructions of the source device and the target device are added, so that data transmission can be directly carried out between the source device and the target device, namely, host memory transfer is bypassed, the data copying frequency is reduced, and the data transmission efficiency is improved. And the delay and the occupation of host resources are reduced.

A data processing method, a network interface card, an electronic device, and a storage medium. The method includes: determining a target dispatch queue to be dispatched from a host memory in response to a doorbell signal sent by a target host, where the doorbell signal indicates that there is a target message to be sent; determining a current target dispatch state of the target dispatch queue, where the target dispatch state is obtained based on an activity and a credit value corresponding to the target work queue element; determining whether a dispatch mechanism corresponding to the target dispatch queue is valid based on the target dispatch state, where the dispatch mechanism indicates whether the target dispatch queue is allowed to be dispatched; and performing a dispatch operation on the target work queue element and the target message in response to the dispatch mechanism being valid.

A storage device may simplify an ungraceful shutdown recovery process and reduce a time-to-ready (TTR) value associated with an ungraceful shutdown bootup sequence. The storage device may include a cache to store data structures associated with host data and meta data. The storage device may also include a controller to store the data structures in a host memory buffer. After an ungraceful shutdown, the controller may execute a bootup sequence and access the host memory buffer during the bootup sequence. The controller may use the data structures stored in the host memory buffer to recover the host data and meta data. The controller applies the host data and meta data to the bootup sequence to simplify the ungraceful shutdown recovery process and reduce the TTR value associated with the ungraceful shutdown bootup sequence.

A module identifier and a request address associated with an access request are received at a host memory buffer (HMB) access module in a solid-state drive (SSD) system. A translated address is determined based at least in part on the module identifier and the request address, including by accessing at least one translation table that stores address mappings between (1) a plurality of processors in the SSD system and (2) a host memory buffer; each processor in the plurality of processors has a non-overlapping memory space in the host memory buffer. The access request is performed at a host interface, including by accessing the host memory buffer using the translated address, wherein the host memory buffer is located in host memory that is external to the SSD system.

A system receives, by a network interface card (NIC), inputs including an instruction to read or write a payload of a message, a tracker state indicating a round of processing, and a datatype descriptor defining organization of the message payload. The system identifies a current context and a processing state for the instruction. If the datatype descriptor indicates a first type, the system: obtains the current context associated with the first type from a host memory or a cache of the NIC; and creates direct memory access (DMA) instructions corresponding to the received instruction by executing operations in a nested loop. If the datatype descriptor indicates a second type, the system: obtains the current context associated with the second type by fetching vector entries from a buffer of the NIC; and creates the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries.

Distributed fiber optic sensing (DFOS) / distributed acoustic sensing (DAS) that illustrate inventive techniques—applicable to all embedded systems—that deliver high-bandwidth traffic from a DFOS system to a cloud or other processing resources in real-time, employ firmware that operates at a register-transfer level and writes data repeatedly into the embedded host memory directly—without software intervention after initial configuration. This technique advantageously enables the use of the relatively large host memory to compensate for any software jitter. Preferably configured, the firmware employs only a small buffer to compensate for a transaction and host-memory arbitration latency. A second dedicated thread sends out data from the user space buffer to a cloud, or a connected server. Remote procedures that are executed on a remote system (a computer, network of computers, or cloud), receive data transmitted from the embedded system, and perform further processing as necessary.

Apparatuses, systems, and techniques of using one or more circuits (e.g., of a network interface) to obtain assembly code for one or more machine code segments loaded and / or injected into a process, and determine whether the assembly code is likely to perform at least one unauthorized task.

A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.

Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

To provide an information processing device that enables overlapping of communication and calculation without buffering the communication between calculation processes on a host.SOLUTION: In an information processing device, a coprocessor-host memory translation function maps a calculation process virtual memory for a calculation process in a coprocessor provided in the information processing device to an offloading function virtual address for collective communication offloading. The collective communication offloading function uses the mapped offloading function virtual address to perform remote direct memory access (RDMA) for another information processing device connected via a network, and implements communication between the calculation process and a calculation process of the other information processing device.SELECTED DRAWING: Figure 1

The embodiment of the invention provides a memory pooling management system, a memory pooling management method, electronic equipment and a storage medium. The memory pooling management system comprises a first server used for creating an expansion device memory through a first operating system and configuring a first address mapping relation between a first virtual memory and the expansion device memory; the second server is used for dividing a pooling host memory in a host memory of the second server through a second operating system; and the expansion switch is in communication connection with the first server through a first bus, is in communication connection with the second server through a second bus, and is used for configuring a second address mapping relation between the expansion equipment memory and the pooling host memory. The first server searches the first address mapping relation based on the virtual address to obtain an intermediate physical address, the extension switch routes the intermediate physical address to the access physical address, and the second server accesses the pooling host memory based on the access physical address.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

A computer system executes a machine learning model having multiple layers, and includes host and work accelerator processors. A window size representing a number of layers to be loaded into accelerator memory is determined. Model data associated with a subset of layers the same size as the window is loaded to the accelerator. The model is iteratively executed by processing a current layer to provide output data and storing this in accelerator memory, offloading the output data to host memory, replacing model data for an already processed layer with model data corresponding to a next layer, and moving to a next layer. The window size is updated during execution based on a transfer duration for loading into accelerator memory, a transfer duration for loading into host memory, or a processing duration of a layer.

The application discloses a kind of application layer bucket level local host memory weight cache management method, equipment and medium, it is related to big language model inference field, method includes: obtaining the bucket level cache index table established by application layer, wherein, bucket level cache index record at least one bucket corresponding to big language model in local cache state, bucket is formed by the independent unit of all weight tensor of big language model according to preset bucketing rule division;The cached bucket is fixed in local host memory by memory locking system call, can solve the defect that operating system autonomously expels weight data in existing scheme, application layer cannot intervene;And when target big language model is loaded, based on bucket level cache index table, cache state is inquired bucket by bucket, and the cached bucket is loaded from local host memory, the expelled bucket is supplemented from other remote storage source, can accurately identify missing weight and only supplement from remote storage source, without full load, finally reduce cold start time consumption.

The invention discloses a log management method, device and equipment and a storage medium, is applied to solid state disk equipment, and relates to the technical field of computers, and the log management method comprises the steps that in the power-on initialization process, host memory demand information is reported to a host, so that the host returns a cache allocation result based on the host memory demand information; when a log export instruction sent by a host is received through a local out-of-band command processing component, determining a to-be-exported log and a segmented loop export strategy in combination with a local flash memory; completing a log export operation by using a segmented loop export strategy, the to-be-exported log, the cache allocation result and a local preset direct memory access engine to obtain instruction completion information; and feeding back instruction completion information to the host, so that the host reads the log in the local memory based on the instruction completion information to trigger log processing operation. According to the log exporting method and device, the problems existing in existing related schemes can be effectively solved, and therefore log exporting is efficiently, stably and reliably achieved.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

The invention provides a high-efficiency memory repair system and method based on a pooling memory. The method comprises the following steps: a memory test module performs UCE error address detection on a memory bank by taking cache as granularity; the management module is used for converting the memory error address into a memory page address to which the memory error address belongs, and issuing a repair command for the memory page address; the address routing module replaces and adds a memory page address into a routing table by utilizing a routing table look-up algorithm according to the repair command so as to finish address repair, performs corresponding address conversion according to a repair state of an accessed host memory address, and routes the address to a port where the memory bank or the out-of-band storage module is located; and the out-of-band storage module is an out-of-band memory pool independent of the system memory pool and is used for repairing the damaged memory by taking the memory page as the granularity. According to the method, the effects of improving the utilization efficiency and compatibility of the memory and enhancing the RAS system of the memory are achieved through the high-efficiency memory repair system which is provided with the out-of-band memory module and takes the memory page capable of being dynamically configured as the granularity.

The invention discloses a data processing method, a solid state disk, a system and a storage medium, and relates to the technical field of solid state disk storage, and the data processing method comprises the steps that it is detected that an NVMe PCIe link configures an instruction register, and an NVMe KV instruction is loaded from a host memory; based on the NVMe KV instruction, obtaining a key value pair configured by a host according to to-be-operated data and an operation code corresponding to a host demand operation type; the KV operation corresponding to the operation code is executed according to the key value pair, and the configuration operation of the key value pair is unloaded to the host to be executed, so that the computing resource occupation amount of the SSD is reduced, and the service quality of the SSD is improved.

The embodiment of the invention provides a memory super-division processing method and system, the memory super-division processing method is applied to a host machine, the host machine runs a plurality of virtual machines, and the method comprises the following steps: determining missing page state data of the plurality of virtual machines in a first historical time period; determining performance loss results of the plurality of virtual machines according to the missing page state data; according to historical cold page data of the multiple virtual machines in a second historical time period, predicted cold page data of the multiple virtual machines in the future time period is determined, the duration of the second historical time period is smaller than or equal to that of the first historical time period, and the duration of the second historical time period is the same as that of the future time period; according to the performance loss result and the predicted cold page data, determining memory super-resolution indexes of the plurality of virtual machines in the future time period; according to the method, the page replacement pressure and the address conversion pressure of the virtual machine are reduced, the performance reduction probability of the host machine is reduced, and the stability of the memory and operation of the host machine is improved.

The present specification provides a data write method applied to a local terminal including a host and a remote direct data access (RDMA) device, the method comprising: receiving, by the RDMA device, a write instruction for target data initiated by a peer terminal based on an RDMA link, the target data including target content, a check value corresponding to the target content, and a target pointer corresponding to the target content; performing, by the RDMA device, a write operation according to the write instruction, the write operation being used to write the target content and the check value to a first memory segment of a host memory, and write the target pointer to a second memory segment of the host memory; and reading, by the RDMA device, the written data corresponding to the write operation and returning to the peer terminal in response to a read instruction for target data initiated by the peer terminal based on the RDMA link.

This invention provides a data storage device and a data reading method. The data storage device is coupled to a host computer, which includes a host memory buffer. The data storage device includes a controller, non-volatile memory, and a buffer. The data reading method includes: downloading firmware data to be updated from the data storage device via the host computer; determining that the host memory buffer contains the firmware data to be updated; reading the firmware data to be updated from the host memory buffer into the buffer; determining that the firmware data to be updated in the buffer is correct through an error correction mechanism; and updating the firmware data of the data storage device. This reduces read / write operations on the data storage device and improves stability, while also increasing data transmission speed without affecting read / write operations.

An exemplary procedure involves a host operating system (host OS) receiving an initial request to allocate memory pages in virtual host memory. In response, the host OS allocates a first guest memory region of the virtual host memory to a virtual machine by at least pinning the first guest memory region. The procedure further involves the host OS receiving a second and a third request to allocate memory pages. In response, the host OS allocates a second and a third guest memory region to the virtual machine. The second guest memory region overlaps a first subregion of the first guest memory region, and the third guest memory region overlaps a second subregion of the first guest memory region.The procedure further involves unpinning, by the host OS, a third subregion of the first guest storage region, with the third subregion not overlapping either the first or the second subregion.

Techniques and systems for data access are provided. For example, a process may include determining a storage device address for a storage device, determining a tag for obtaining encrypted metadata for data for the storage device, generating a return address, the return address including a host memory address and the tag, and accessing the storage device based on the return address and the storage device address.

A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

Systems, methods, and apparatus for a memory system supporting low latency multi-cycle queue (MCQ) functionality. In a first aspect, a method performed by a host memory controller in a flash memory system includes storing response information as an entry in a completion queue based on a response received from a memory system coupled to a host device. The method includes updating an entry in a completion queue pointer register corresponding to the completion queue based on storage of the response information at the completion queue. The method includes clearing an entry in a complete queue interrupt state (CQIS) register, and issuing an MCQ event specific interrupt (ESI) to a processor core of the host device after clearing the entry in the CQIS register.