250 results about "Host memory" patented technology

The invention discloses a large language model semantic query acceleration method based on a sparse KV Cache index. The method comprises a KV Cache semantic pruning strategy based on an attention mechanism and a set of asynchronous pipeline reasoning architecture with overlapped calculation and I / O. According to the method, the attention sparsity characteristic of the large language model in the reasoning stage and the asynchronous transmission capacity between the Host memory and the GPU video memory are fully utilized, calculation redundancy and video memory occupation in repetitive semantic query are greatly reduced, and high-throughput, low-delay and high-performance batch semantic data processing service is provided. Through a mechanism for mapping a static text into a compressed semantic index and combining a prefix cache technology in a reasoning process to realize state multiplexing, high-performance reasoning acceleration and high-efficiency storage compression are provided for a data-intensive semantic analysis task in a resource-constrained environment.

The invention discloses a garbage collection optimization method and device, equipment and a medium. The invention relates to the technical field of solid state disks, which comprises the following steps that: a global invalid data bit chart is established in a host memory, each table item in the global invalid data bit chart corresponds to a physical block, and a bitmap bit in each table item corresponds to a physical page in the physical block; bit values corresponding to the bitmap bits comprise a first bit value and a second bit value; responding to a data updating event through an access acceleration engine so as to dynamically update the bit value of the corresponding physical page in the global invalid data bit graph; and when garbage collection is triggered, screening the physical page of which the bit value is the second bit value in a to-be-collected source physical block according to the global invalid data bit chart and the access acceleration engine to perform validity verification and data migration, and skipping the physical page of which the bit value is the first bit value. According to the invention, the garbage recycling efficiency is improved.

Modem datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

A data processing method, a network interface card, an electronic device, and a storage medium. The method includes: determining a target dispatch queue to be dispatched from a host memory in response to a doorbell signal sent by a target host, where the doorbell signal indicates that there is a target message to be sent; determining a current target dispatch state of the target dispatch queue, where the target dispatch state is obtained based on an activity and a credit value corresponding to the target work queue element; determining whether a dispatch mechanism corresponding to the target dispatch queue is valid based on the target dispatch state, where the dispatch mechanism indicates whether the target dispatch queue is allowed to be dispatched; and performing a dispatch operation on the target work queue element and the target message in response to the dispatch mechanism being valid.

A system receives, by a network interface card (NIC), inputs including an instruction to read or write a payload of a message, a tracker state indicating a round of processing, and a datatype descriptor defining organization of the message payload. The system identifies a current context and a processing state for the instruction. If the datatype descriptor indicates a first type, the system: obtains the current context associated with the first type from a host memory or a cache of the NIC; and creates direct memory access (DMA) instructions corresponding to the received instruction by executing operations in a nested loop. If the datatype descriptor indicates a second type, the system: obtains the current context associated with the second type by fetching vector entries from a buffer of the NIC; and creates the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries.

Distributed fiber optic sensing (DFOS) / distributed acoustic sensing (DAS) that illustrate inventive techniques—applicable to all embedded systems—that deliver high-bandwidth traffic from a DFOS system to a cloud or other processing resources in real-time, employ firmware that operates at a register-transfer level and writes data repeatedly into the embedded host memory directly—without software intervention after initial configuration. This technique advantageously enables the use of the relatively large host memory to compensate for any software jitter. Preferably configured, the firmware employs only a small buffer to compensate for a transaction and host-memory arbitration latency. A second dedicated thread sends out data from the user space buffer to a cloud, or a connected server. Remote procedures that are executed on a remote system (a computer, network of computers, or cloud), receive data transmitted from the embedded system, and perform further processing as necessary.

A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.

Modern datacenters require flexible interconnect solutions that bridge diverse protocol domains while maintaining compatibility with existing infrastructure. Embodiments herein disclose semiconductor devices that implement protocol translations and physical address translations within IC packages conforming to the PCIe Retimer Supplemental Features and Standard BGA Footprint Specification. The devices comprise first and second interfaces communicating according to first and second protocols respectively, with an embedded computer that extracts physical addresses from messages received via the first interface, translates these addresses, and generates messages carrying the translated addresses for transmission via the second interface. This retimer-compatible form factor essentially enables drop-in deployment within existing PCIe and cabling infrastructures while providing protocol bridging and address translation capabilities. The standardized BGA layout provides high-speed differential signaling suitable for low-latency address translation, optionally supporting memory disaggregation, host-to-host memory sharing, accelerator integration, and protocol conversion between CXL, UALink, NVLink, and / or PCIe domains, addressing interoperability challenges.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

A computer system executes a machine learning model having multiple layers, and includes host and work accelerator processors. A window size representing a number of layers to be loaded into accelerator memory is determined. Model data associated with a subset of layers the same size as the window is loaded to the accelerator. The model is iteratively executed by processing a current layer to provide output data and storing this in accelerator memory, offloading the output data to host memory, replacing model data for an already processed layer with model data corresponding to a next layer, and moving to a next layer. The window size is updated during execution based on a transfer duration for loading into accelerator memory, a transfer duration for loading into host memory, or a processing duration of a layer.

The application discloses a kind of application layer bucket level local host memory weight cache management method, equipment and medium, it is related to big language model inference field, method includes: obtaining the bucket level cache index table established by application layer, wherein, bucket level cache index record at least one bucket corresponding to big language model in local cache state, bucket is formed by the independent unit of all weight tensor of big language model according to preset bucketing rule division;The cached bucket is fixed in local host memory by memory locking system call, can solve the defect that operating system autonomously expels weight data in existing scheme, application layer cannot intervene;And when target big language model is loaded, based on bucket level cache index table, cache state is inquired bucket by bucket, and the cached bucket is loaded from local host memory, the expelled bucket is supplemented from other remote storage source, can accurately identify missing weight and only supplement from remote storage source, without full load, finally reduce cold start time consumption.

The invention discloses a log management method, device and equipment and a storage medium, is applied to solid state disk equipment, and relates to the technical field of computers, and the log management method comprises the steps that in the power-on initialization process, host memory demand information is reported to a host, so that the host returns a cache allocation result based on the host memory demand information; when a log export instruction sent by a host is received through a local out-of-band command processing component, determining a to-be-exported log and a segmented loop export strategy in combination with a local flash memory; completing a log export operation by using a segmented loop export strategy, the to-be-exported log, the cache allocation result and a local preset direct memory access engine to obtain instruction completion information; and feeding back instruction completion information to the host, so that the host reads the log in the local memory based on the instruction completion information to trigger log processing operation. According to the log exporting method and device, the problems existing in existing related schemes can be effectively solved, and therefore log exporting is efficiently, stably and reliably achieved.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

The invention provides a high-efficiency memory repair system and method based on a pooling memory. The method comprises the following steps: a memory test module performs UCE error address detection on a memory bank by taking cache as granularity; the management module is used for converting the memory error address into a memory page address to which the memory error address belongs, and issuing a repair command for the memory page address; the address routing module replaces and adds a memory page address into a routing table by utilizing a routing table look-up algorithm according to the repair command so as to finish address repair, performs corresponding address conversion according to a repair state of an accessed host memory address, and routes the address to a port where the memory bank or the out-of-band storage module is located; and the out-of-band storage module is an out-of-band memory pool independent of the system memory pool and is used for repairing the damaged memory by taking the memory page as the granularity. According to the method, the effects of improving the utilization efficiency and compatibility of the memory and enhancing the RAS system of the memory are achieved through the high-efficiency memory repair system which is provided with the out-of-band memory module and takes the memory page capable of being dynamically configured as the granularity.

The invention discloses a data processing method, a solid state disk, a system and a storage medium, and relates to the technical field of solid state disk storage, and the data processing method comprises the steps that it is detected that an NVMe PCIe link configures an instruction register, and an NVMe KV instruction is loaded from a host memory; based on the NVMe KV instruction, obtaining a key value pair configured by a host according to to-be-operated data and an operation code corresponding to a host demand operation type; the KV operation corresponding to the operation code is executed according to the key value pair, and the configuration operation of the key value pair is unloaded to the host to be executed, so that the computing resource occupation amount of the SSD is reduced, and the service quality of the SSD is improved.

The embodiment of the invention provides a memory super-division processing method and system, the memory super-division processing method is applied to a host machine, the host machine runs a plurality of virtual machines, and the method comprises the following steps: determining missing page state data of the plurality of virtual machines in a first historical time period; determining performance loss results of the plurality of virtual machines according to the missing page state data; according to historical cold page data of the multiple virtual machines in a second historical time period, predicted cold page data of the multiple virtual machines in the future time period is determined, the duration of the second historical time period is smaller than or equal to that of the first historical time period, and the duration of the second historical time period is the same as that of the future time period; according to the performance loss result and the predicted cold page data, determining memory super-resolution indexes of the plurality of virtual machines in the future time period; according to the method, the page replacement pressure and the address conversion pressure of the virtual machine are reduced, the performance reduction probability of the host machine is reduced, and the stability of the memory and operation of the host machine is improved.

The present specification provides a data write method applied to a local terminal including a host and a remote direct data access (RDMA) device, the method comprising: receiving, by the RDMA device, a write instruction for target data initiated by a peer terminal based on an RDMA link, the target data including target content, a check value corresponding to the target content, and a target pointer corresponding to the target content; performing, by the RDMA device, a write operation according to the write instruction, the write operation being used to write the target content and the check value to a first memory segment of a host memory, and write the target pointer to a second memory segment of the host memory; and reading, by the RDMA device, the written data corresponding to the write operation and returning to the peer terminal in response to a read instruction for target data initiated by the peer terminal based on the RDMA link.

This invention provides a data storage device and a data reading method. The data storage device is coupled to a host computer, which includes a host memory buffer. The data storage device includes a controller, non-volatile memory, and a buffer. The data reading method includes: downloading firmware data to be updated from the data storage device via the host computer; determining that the host memory buffer contains the firmware data to be updated; reading the firmware data to be updated from the host memory buffer into the buffer; determining that the firmware data to be updated in the buffer is correct through an error correction mechanism; and updating the firmware data of the data storage device. This reduces read / write operations on the data storage device and improves stability, while also increasing data transmission speed without affecting read / write operations.

An exemplary procedure involves a host operating system (host OS) receiving an initial request to allocate memory pages in virtual host memory. In response, the host OS allocates a first guest memory region of the virtual host memory to a virtual machine by at least pinning the first guest memory region. The procedure further involves the host OS receiving a second and a third request to allocate memory pages. In response, the host OS allocates a second and a third guest memory region to the virtual machine. The second guest memory region overlaps a first subregion of the first guest memory region, and the third guest memory region overlaps a second subregion of the first guest memory region.The procedure further involves unpinning, by the host OS, a third subregion of the first guest storage region, with the third subregion not overlapping either the first or the second subregion.

A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

Systems, methods, and apparatus for a memory system supporting low latency multi-cycle queue (MCQ) functionality. In a first aspect, a method performed by a host memory controller in a flash memory system includes storing response information as an entry in a completion queue based on a response received from a memory system coupled to a host device. The method includes updating an entry in a completion queue pointer register corresponding to the completion queue based on storage of the response information at the completion queue. The method includes clearing an entry in a complete queue interrupt state (CQIS) register, and issuing an MCQ event specific interrupt (ESI) to a processor core of the host device after clearing the entry in the CQIS register.

The disclosure configures a multi-port memory sub-system controller to store data in one or more host memory buffers. The disclosure associates, with a first port of a memory sub-system, a first host memory buffer (HMB) of a first temporary storage device that has been allocated to the memory sub-system by a first host system of a plurality of host systems and associates, with a second port of the memory sub-system, a second HMB of a second temporary storage device that has been allocated to the memory sub-system by a second host system of the plurality of host systems. The disclosure performs one or more memory operations on user data using the first HMB and the second HMB and a set of memory components.

A system receives input from a network interface card (NIC) containing: a command to read or write a message payload, a tracker state indicating a processing round, and a data type descriptor defining the organization of the message payload. The system identifies a current context and processing state for the command. If the data type descriptor indicates a first type, the system retrieves the current context associated with that first type from host memory or the NIC cache and generates direct memory access (DMA) commands corresponding to the received command by performing operations in a nested loop.If the data type descriptor indicates a second type, the system obtains the current context associated with the second type by retrieving vector entries from a buffer of the NIC and generates the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries.

The present invention relates to a system for protecting against cyber-attacks on a host machine, comprising: (a) at least one MTS, connected to the bus lines, of said memory device(s), of said host, for sampling the electrical signals, intended for said memory device(s); (b) at least one MRMU, connected to said MTS(s), for receiving said sampled signals from said MTS(s) and translating said sampled signals for reconstructing the physical and virtual memory content of said host, into at least one MLM of said host machine; (c) a memory, connected to said MRMU, for storing said at least one MLM; and (d) an IPU, connected to said MRMU(s), and connected to said memory, for detecting, identifying, and analyzing at least one EOI within the reconstructed host memory content, on said memory, and for classifying said at least one EOI as legitimate or malicious.

The invention discloses a data writing method applied to a storage device and the storage device. The data writing method comprises the following steps: writing data to be written into a source physical block in a storage medium according to a single-bit programming mode; backing up the data to be written into a host memory buffer area; writing the to-be-written data into a target physical block in the storage medium according to a multi-bit programming mode to complete rough programming; re-acquiring the data to be written from the host memory buffer area; and writing the to-be-written data into the target physical block in the storage medium according to a multi-bit programming mode to complete fine programming. Compared with an existing scheme, the data writing method has the advantages that intermediate data carrying is reduced, performance is improved, writing amplification of flash memory particles is reduced, and the service life of the whole storage device is prolonged.

The invention provides data shaping of a DMA (Direct Memory Access) unit. The DMA unit comprises a first data migration unit, a first DMA cache, a first data protection and detection unit, a first data shaping unit and a second data migration unit, the first data migration unit migrates the first data in the host memory to the first DMA cache; the first data protection and detection unit executes a predetermined operation on the first data and outputs the first data with a first data format, and user data and metadata in the first data format are arranged adjacently; the first data shaping unit is used for shaping the first data in the first data format and outputting the first data in the second data format, the user data in the second data format are adjacently arranged, and the metadata in the second data format are adjacently arranged; and the second data migration unit migrates the first data with the second data format to the allocated first cache unit. By performing format shaping on the transmission data, the transmission frequency can be reduced, and the transmission efficiency can be improved.

Embodiments of the present application provide a host memory access method and device and electronic equipment, wherein the method comprises: obtaining a control command, determining a host memory access mode adopted by the control command according to a preset condition; if the preset condition is met, realizing host memory access through an address mapping mode, the address mapping being a mapping relationship between an address of a host storage unit and a source address; if the preset condition is not met, realizing the host memory access through a DMA mode. In this way, the host memory access can be realized through the address mapping mode or the DMA mode, which can improve access efficiency and avoid access delay.

The application provides a stateless RDMA server network card and a communication method, which comprises the following steps: a data transceiving unit is used for receiving an RDMA message, and based on the lightweight state information carried, the information in a session identification storage unit is inquired to perform verification processing, and after the verification processing is completed, it is stored in a server host memory; the latest message sequence number in the session identification storage unit is updated; the lightweight state information comprises a session identification and a current message sequence number; the session identification storage unit is used for storing the session identification, an effective flag and the latest message sequence number received by a state agent unit; the state agent unit is used for communicating with a client host memory, a session is established based on the session identification and the connection state information issued from the client host memory, and the session identification and the initial message sequence number are stored in the session identification storage unit. The application can completely break the limitation of the network card on the memory to the number of concurrent connections, and greatly reduce the storage and processing pressure of the network card hardware.

This application provides a data transmission method, a network interface card (NIC) for a data receiving end, an electronic device, and a storage medium. The data transmission method is applied to the NIC of the data receiving end. The NIC writes data to the host memory of the data receiving end via a bus. The data transmission method includes: if the bus bandwidth resources required for the NIC to write the target data to the host memory exceed the bus bandwidth resources available to the NIC, then writing a portion of the target data to the NIC's NIC buffer; the NIC buffer includes a first memory buffer configured for the NIC based on its on-chip memory and a second memory buffer configured for the NIC based on its onboard memory; the data sending end sends the target data to the data receiving end via remote direct memory access; and a portion of the data is written from the NIC buffer to the host memory. The solution of this application can better avoid data packet loss problems when facing sudden traffic surges.

The invention discloses an access authentication method based on network interface card master control firmware function extension, and aims to solve the security problem that a client private key is easy to leak due to the fact that the client private key is loaded from a file or loaded to a host memory in the authentication process in the prior art. The method comprises the following steps: after a host of client equipment receives an authentication request from an authentication server, an authentication challenge is sent to a network interface card through a driving program; and the firmware in the network interface card calls a client private key preset in a non-export mode in a secure storage module of the firmware, completes cryptographic operation on the content by using the private key, and returns an operation result to the host. Due to the fact that the client side private key and the relevant cryptographic operation process are completely completed in the hardware boundary of the network interface card and do not leave the network card, an attacker is effectively prevented from stealing the private key after breaking through a host system, and the safety of the client side identity authentication process is remarkably improved.