18 results about "Memory window" patented technology

The present disclosure provides methods for programming multilevel memory devices. The methods may include determining a first plurality of memory windows representative of gaps between dispersions of adjacent conductance states of the memory device, determining a plurality of dispersion parameters representative of estimated dispersions of the conductance states, and determining a second plurality of memory windows based on the first plurality of memory windows and the plurality of dispersion parameters. The second plurality of memory windows represents separations between mean conductance values of adjacent conductance states of the memory device. The second plurality of memory windows has varying values.

The application discloses a no-interface wurtzite ferroelectric nitride memory, which comprises a nitride semiconductor substrate and a wurtzite ferroelectric dielectric layer in contact; the wurtzite ferroelectric dielectric layer is directly grown on the nitride semiconductor substrate by using a good lattice matching between the wurtzite ferroelectric material and the nitride substrate material, through an in-situ sputtering process, an atomic layer deposition process or an epitaxial growth process; and finally, the no-interface wurtzite ferroelectric nitride memory between the wurtzite ferroelectric material and the nitride semiconductor substrate is realized, so as to solve a series of problems such as additional power consumption and reliability degradation caused by the existing non-ideal interface layer of the ferroelectric memory. The no-interface wurtzite ferroelectric nitride memory provided by the application has low power consumption, high reliability, high switching ratio and high memory window, and can be applied to the development of high-computing-power, high-energy-efficiency, low-power-consumption and high-reliability storage and computing devices and chip technologies.

Crystalline taos with ultrahigh memory window x Resistive random access memory and its preparation method, belong to semiconductor thin film and its resistive random access memory technical field. Mainly include: 1) handle (100) oriented single crystal Si substrate; 2) prepare (222) oriented ITO bottom electrode on the substrate by magnetron sputtering method; 3) grow the crystalline TaO with the main crystal direction (100) and the maximum grain size of 30 nm on the ITO bottom electrode by radio frequency reactive magnetron sputtering method x Thin film as resistance layer; 4) deposit Ta electrode on the resistance layer by magnetron sputtering method. The crystalline TaO with the main crystal direction (100) and the maximum grain size of 30 nm is prepared x The thin film has good thin film crystal structure and grain size, fast growth speed and controllable thin film composition, and the crystalline TaO with the thin film as the resistance layer x The resistive random access memory shows ultrahigh memory window, very low operating voltage and strong durability, and can be crystalline TaO x The application provides certain technical guidance for commercialization and industrial application of the resistive random access memory.

In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.

The application discloses a kind of communication systems and methods between vehicle-mounted heterogeneous SoC based on PCIe non-transparent bridge, including vehicle-mounted first SoC and vehicle-mounted second SoC connected physically by PCIe interface, wherein vehicle-mounted first SoC is configured as RC end NTB equipment driver, responsible for discovery, mapping and using the memory window and doorbell interrupt presented by EP side vNTB EPF function driver virtualization;Vehicle-mounted second SoC is configured as EP end vNTB EPF function driver based on EPF framework, responsible for virtualization and presentation of its local memory window and doorbell interrupt mechanism, for RC end access. Through shared memory window and doorbell interrupt mechanism, efficient, low-delay bidirectional data transmission is realized between vehicle-mounted heterogeneous processors. The application constructs the infrastructure of vehicle-mounted gigabit-level communication, solves the data throughput and real-time bottleneck in vehicle-mounted ADAS, automatic driving and other applications, and is suitable for vehicle-mounted multi-domain fusion architecture.

A HfO2-based ferroelectric capacitor and a preparation method therefor, and a HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging the memory window of the ferroelectric memory is achieved by inserting an Al2O3 intercalation layer having a coefficient of thermal expansion smaller than TiN between a dielectric layer and an upper electrode (TiN) of the ferroelectric capacitor. The HfO2-based ferroelectric capacitor comprises a substrate layer, a lower electrode, a dielectric layer, an Al2O3 intercalation layer, an upper electrode and a metal protection layer from bottom to top. The memory window can be increased, information misreading is effectively prevented, and therefore, the reliability of the memory is improved.

The application relates to the technical field of data security and privacy protection, and specifically provides an elliptic curve PSI batch processing method, system and device based on double hashing and window mapping and a medium, which comprises the following steps: obtaining hardware parameters such as CPU last-level cache capacity and parallel thread number, calculating the optimal capacity of each memory window to ensure that window data can be completely loaded in the last-level cache; performing a first-level encryption hash operation on each element in an input set to obtain a security feature value, performing a second-level non-encryption high-speed hash operation on the security feature value to obtain a window index value, and distributing each element to a corresponding memory window in a continuous memory block; performing flow parallel calculation of elliptic curve point multiplication operation in batches in a continuous memory area in units of memory windows to generate a ciphertext set. The application can significantly improve the cache hit rate and calculation throughput by forcibly converting random access into sequential flow access.

The present technology provides a threshold sensing device including an inductor, a ferroelectric varactor, and a resonator sensitive to a selected parameter of interest. The unbiased varactor has a memory window that grows proportionally with the partial switching of the varactor's ferroelectric domains. A DC voltage is generated across the varactor which, above a parameter threshold sensed by the resonator, drives the ferroelectric switching of the varactor. A nonvolatile shift in a radio frequency readout signal serves as a memory of an exceeded parameter threshold detected by the resonator. The sensor device can be used to detect temperature violations in a cold chain or the presence of a chemical or biological agent and is capable of battery-less operation.

The application provides a trust-aware security distributed tracking method for an interactive multi-target system and belongs to the technical field of state estimation. The application has the following steps: a nonlinear random state space model is established; a memory attack detection mechanism based on trust awareness is designed, an attack detection function is constructed based on measurement residuals, and a limited memory window is used to realize real-time detection of whether the measurement data is attacked; three states of the measurement data are divided, and a measurement credibility factor is constructed; weighted fusion processing is performed to obtain effective measurement information; a security distributed state estimator is constructed to calculate one-step prediction of the system state; an upper bound of a one-step prediction error covariance matrix of each target state is recursively calculated; an estimator gain matrix of each target is calculated; the estimation of each target state is updated by using the gain matrix, and the upper bound of the estimation error covariance matrix is recursively calculated until a preset termination time. The application can improve the security, robustness and reliability of the system in a complex network environment.

A system (20; 30; 40; 50; 60) for enabling non-transparent bridging, hereinafter referred to as NTB, in a motor vehicle environment, comprising the following: at least one PCIe switch (5), a first system-on-a-chip (3), hereinafter referred to as SoC 1, connected to the PCIe switch, and a second system-on-a-chip (4), hereinafter referred to as SoC 2, connected to the PCIe switch; wherein the PCIe switch contains hardware components for a buffer; where SoC 1 contains the following: a PCIe interface and a memory containing the following: a memory window shared with SoC 2, and a PCIe base address register containing a base address of a cache in the PCIe switch and a base address of a memory window of the SoC 2; where SoC 2 contains the following: a PCIe interface and a memory containing the following: a memory window shared with SoC 1, and a PCIe base address register containing a base address of a cache in the PCIe switch and a base address of a memory window of the SoC 1; to enable communication between SoC 1 and SoC 2; and further comprising a first address translation unit, hereinafter referred to as ATU 1, which is assigned to SoC 1, and a second address translation unit, hereinafter referred to as ATU 2, which is assigned to SoC 2, for translating address spaces between SoC 1, SoC 2 and the PCIe switch, such that ATU 1 and ATU 2 enable memory transaction packets to flow between SoC 1 and SoC 2, in particular without CPU intervention.

The invention discloses a heat sensing data center energy consumption and service life optimization method and system based on the health degree and a storage medium thereof, and belongs to the technical field of data center energy saving and equipment service life management. A sustainable updating server health degree scoring model is constructed, a temperature fluctuation memory window is introduced to describe a thermal fatigue effect, IT energy consumption, cooling energy consumption and life loss cost converted from health degree reduction are uniformly incorporated into a multi-time-period joint optimization model, and a two-stage time scale scheduling strategy is adopted to optimize the health degree of a server. On the premise that service requirements and temperature safety are guaranteed, the server operation environment and the load state are guided to evolve towards the direction of low energy consumption, low temperature impact and low failure rate, and collaborative optimization of the total energy consumption of the data center and the service life of the server is achieved. On the premise of meeting business requirements and temperature safety, comprehensive energy consumption is reduced, health degree attenuation is slowed down, the service life of the server is prolonged, and long-term operation stability is improved.

The invention relates to the technical field of wireless communication, and discloses a signal detection method and electronic equipment for a large-scale MIMO system, and the method comprises the steps: generating a linear parameter of a preset algorithm in a current iteration round according to a channel model parameter of the MIMO system and memory information recorded when the preset algorithm is used for iteration in a signal detection process; determining effective information according to the linear parameter by using a preset first memory window; according to the effective information, extracting data corresponding to the serial number of the preorder iteration round from the linear parameter and the memory information, and calculating to obtain an influence coefficient of the preorder iteration round on the current iteration round; iteratively calculating a posteriori mean value and a posteriori variance when each channel in the MIMO system is used as an estimated channel according to the linear parameter and the influence coefficient, and updating memory information; and determining a detection value of the sending signal of the MIMO system based on the posterior mean value when the maximum iteration number is reached. The beneficial effect is that the signal detection efficiency is improved.

The communication system comprises a first vehicle-mounted SoC and a second vehicle-mounted SoC which are physically connected through a PCIe interface, and the first vehicle-mounted SoC serves as an RC end to configure an NTB device driver and is responsible for discovering, mapping and utilizing a memory window and doorbell interruption which are virtually presented by a vNTB EPF function driver on an EP side; and the vehicle-mounted second SoC is used as an EP end to realize vNTB EPF function driving based on an EPF framework, and is responsible for virtualization and presentation of a local memory window and a doorbell interruption mechanism for the RC end to access. Through a shared memory window and a doorbell interruption mechanism, high-efficiency and low-delay bidirectional data transmission between vehicle-mounted heterogeneous processors is realized. According to the invention, the infrastructure of vehicle-mounted 10-gigabit communication is constructed, the bottleneck of data throughput and real-time performance in applications such as vehicle-mounted ADAS, automatic driving and the like is solved, and the method is suitable for a vehicle-mounted multi-domain fusion architecture.

A nonvolatile memory device is disclosed that incorporates a FeFET having a gate stack with a ferroelectric dielectric layer positioned below a charge trapping layer. During programming, polarization switching in the ferroelectric layer drives charge injection from the gate into the overlying trapping layer. The trapped charge combines with the ferroelectric polarization to shift the threshold voltage of the device. A capping dielectric may be included above the trapping layer to improve charge retention. This gate-side charge injection mechanism supports efficient programming while maintaining a compact vertical stack suitable for integration into high-density memory architectures such as vertical NAND.

The application discloses a kind of based on NTB-vNTB EPF cooperation's vehicle-mounted kernel queue transmission optimization system and method, traditional kernel queue tasklet asynchronous mechanism is converted into high priority real-time kernel thread, using SCHED_FIFO or SCHED_RR real-time scheduling strategy to handle the data transmission queue of NTB / vNTB driving layer, ensure the determinacy and minimum delay of data processing.The method is combined with NTB device driving discovery, mapping and using EP end through vNTB EPF function drive virtual configuration and the memory window and doorbell interrupt provided, and vNTB EPF function drive is virtually realized and manages these NTB functions in EP end.Meanwhile, dynamic vehicle-mounted kernel thread scheduling, CPU idle state intelligent management, vehicle-mounted zero-copy technology and pre-allocated memory pool strategy are integrated.Through these optimizations, the data transmission efficiency between vehicle-mounted heterogeneous SoCs is significantly improved.

The application provides a high-dynamic infrared countermeasure scene anti-distortion feature reconstruction and target tracking defense method, comprising: monitoring an infrared image sequence through a state machine of a memory window, freezing the memory window and extracting an absolute cold background anchor point when a mutation feature appears; when a target area pixel saturation ratio is greater than a high-risk threshold, assigning a single-frame concealment degree to a limit value; otherwise, when optical vignetting overflows, a nonlinear exponential penalty is applied to the concealment degree; performing multi-peak dynamic clustering on a local background, combining the absolute cold background anchor point to determine the number of effective wave peaks, and when the number is greater than a limited value, determining a comprehensive confusion degree according to a high-order amplification multiplier and a basic single-frame confusion degree; fusing the single-frame concealment degree and the comprehensive confusion degree into a comprehensive complexity, and performing target tracking defense based on the comprehensive complexity. The application can provide an objective, real and robust anti-interference performance measurement scale in a high-dynamic infrared countermeasure scene, effectively supporting the defense decision of an automatic target tracking algorithm.

The invention discloses a temperature self-adaptive reading circuit for a capacitance-free dynamic random access memory and an operation method of the temperature self-adaptive reading circuit, and belongs to the technical field of micro-nano electronics. According to the invention, a structure which is completely consistent with a storage unit is adopted as an adaptive load, so that the reference branch and the storage branch generate synchronous response to temperature change. When the environment temperature changes, the current characteristic of the storage unit and the resistance characteristic of the self-adaptive load drift towards the same direction, so that the difference value between the unit current and the reference current is kept. Degradation of a memory window along with temperature is effectively restrained, it is ensured that data can be correctly judged within a wide temperature range, and the reliability and the maximum working temperature of a reading circuit are remarkably improved.