42 results about "Band-gap engineering" patented technology

Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.

Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.

A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced by utilization of nano-crystals and/or bulk trapping materials in a composite non-conductive trapping layer and a high K dielectric insulating layers. The band-gap engineered gate-stack with asymmetric direct tunneling or crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage high speed tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. Memory cell embodiments of the present invention allow multiple levels of bit storage in a memory cell through multiple charge centroids and/or multiple threshold voltage levels.

The present invention is a tunable semiconductor laser for swept source optical coherence tomography, comprising a semiconductor substrate; a waveguide on top of said substrate with multiple sections of different band gap engineered multiple quantum wells (MQWs); a multiple of distributed feedback (DFB) gratings corresponding to each said band gap engineered MWQs, each DFB having a different Bragg grating period; and anti-reflection (AR) coating deposited on at least the laser emission facet of the laser to suppress the resonance of Fabry-Perot cavity modes. Each DFB MQWs section can be activated and tuned to lase across a fraction of the overall bandwidth as is achievable for a single DFB laser and all sections can be sequentially activated and tuned so as to collectively cover a broad bandwidth, or simultaneously activated and tuned to enable a tunable multi-wavelength laser. The laser hence can emit either a single lasing wavelength or a multiple of lasing wavelengths and is very suitable for swept-source OCT applications.

Disclosed is a light emitting diode (LED) having an active region of a multiple quantum well structure in which well layers and barrier layers are alternately laminated between a GaN-based N-type compound semiconductor layer and a GaN-based P-type compound semiconductor layer. The LED includes a middle barrier layer having a bandgap relatively wider than the first barrier layer adjacent to the N-type compound semiconductor layer and the n-th barrier layer adjacent to the P-type compound semiconductor layer. The middle barrier layer is positioned between the first and n-th barrier layers. Accordingly, positions at which electrons and holes are combined in the multiple quantum well structure to emit light can be controlled, and luminous efficiency can be enhanced. Furthermore, an LED is provided with enhanced luminous efficiency using a bandgap engineering or impurity doping technique.

Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

A method of fiber core material band gap engineering for artificially modifying fiber material properties is provided. The method includes doping the fiber core material with one or more atoms for enhancing photosensitivity to the fiber material. The method also includes co-doping the fiber core material with one or more ions for enhancing an amorphous network crosslink mean coordination number. The method further includes thermally annealing the fiber core material for widening the band gap of the fiber core material.

A method of detecting electromagnetic radiation with an active pixel sensor photosensitive device having an extremely thin virtual pinning layer formed by inverting semiconductor material at the surface of a photosensitive region. The thin pinning layer improves blue light response. The inverted pinning layer is produced by connecting a negative potential source to a transparent conductive layer, preferably made of indium-tin-oxide positioned over most of the photosensitive region. The conductive layer is insulated from the photosensitive region by a thin insulating layer. Connection to the pinning layer is through a coupling region formed in an area not covered by the conductive and insulating layers. Red light response is improved and the depth of the photosensitive region reduced by creating a strained layer, preferably of germanium silicon, deep within the photosensitive region. The strained layer has a modified bandgap which increases the absorption rate of red light.

A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.

Expitaxial substitutional solid solutions of silicon carbon can be obtained by an ultrafast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si_1−yC_y, y<0.1 is desired for strain engineering or bandgap engineering.

Techniques to use energy band gap engineering (or band offset engineering) to produce a photodetector semiconductor assembly that can be tuned to absorb light in one or more wavelengths. For example, the assembly can be tuned to receive infrared (IR) and/or ultraviolet (UV) light. The photodetector assembly can operate as a photodiode, a phototransistor, or can include both a photodiode and a phototransistor.