Band gap engineering with self-aligned process

Abstract

A method includes removing at least a portion of a first layer that is over a second layer. The methos also includes band gap tuning the second layer. The method further includes removing at least a portion of the second layer. A device includes: a first semiconductor layer; a second semiconductor layer; and a band gap tuned material layer between the first semiconductor layer and the second semiconductor layer.

Description

[0001] BAND GAP ENGINEERING WITH SELF-ALIGNED PROCESS

[0002] CROSS-REFERENCE TO RELTATED APPLICATIONS

[0003] This application claims benefit of and priority to U.S. provisional patent application Ser. No. 63 / 626,714 filed on 30 January 2024.

[0004] FIELD

[0005] This disclosure relates to a method and device involving band gap engineering with a self-aligned process.

[0006] SUMMARY

[0007] According to an aspect, there is provided a method comprising: removing at least a portion of a first layer that is over a second layer; band gap tuning the second layer; and removing at least a portion of the second layer.

[0008] Removing at least the portion of the first layer may comprise: applying a first mask on the first layer; and performing a shallow etch at least partially through unmasked portions of the first layer.

[0009] The method may further include applying a second mask.

[0010] The second mask may be applied to at least one sidewall of the first layer formed by the shallow etch.

[0011] Band gap tuning the second layer further may include performing impurity diffusion to unmasked portions of the second layer.

[0012] Removing at least the portion of the second layer may further comprise performing a second etch at least partially through the unmasked portions of the second layer.

[0013] A sidewall angle formed by the second etch may differ from a sidewall angle formed by the shallow etch.

[0014] Removing at least the portion of the second layer may correspond to a self-aligned process.

[0015] According to another aspect, there is provided a device comprising: a first semiconductor layer; a second semiconductor layer; and a band gap tuned material layer between the first semiconductor layer and the second semiconductor layer.

[0016] The device may correspond to a light emitting diode, LED, and the band gap tuned material layer may include an embedded light emitting source.

[0017] The device may further comprise a lens material on the first semiconductor layer.

[0018] The device may further comprise a reflective mirror surrounding at least the light emitting source.

[0019] The reflective mirror may include a passivation material.

[0020] The first semiconductor layer, the band gap tuned material layer and the second semiconductor layer may form a mesa structure.

[0021] The band gap tuned material layer may include band gap tuned sidewalls surrounding a non-tuned region.

[0022] The first semiconductor layer and the second semiconductor layer may not include band gap tuned regions.

[0023] It will be appreciated that any features described herein as being suitable for incorporation into one or more aspects or embodiments of the present disclosure are intended to be generalizable across any and all aspects and embodiments of the present disclosure. Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure. The foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the claims.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings illustrate a number of exemplary embodiments and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0026] FIGS. 1A-B are diagrams of exemplary semiconductor devices.

[0027] FIG. 2 is a flow diagram of an exemplary method for band gap engineering with a selfaligned process.

[0028] FIGS. 3A-E are diagrams of exemplary stages of fabricating a semiconductor device using band gap engineering with a self-aligned process.

[0029] FIG. 4 is a diagram of an exemplary semiconductor device having band gap engineering with a self-aligned process.

[0030] Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0031] Display technology may be improved by reducing the size of light-emitting diodes (LEDs). For example, reducing LEDs to the sub-5 pm range may improve resolution and / or form factor in displays for devices, such as for wearable devices (e.g., glasses form factor devices, head-mounted devices, other small form-factor devices, etc.). Reducing LEDs includes size reduction of the light emitting region, which is often performed by dry or wet etching processes. However, etching processes often disrupt the crystalline structure of semiconductor layers, creating surface-related defects at the sidewalls which may significantly reduce the efficiency with the light emitting region because charge carriers may be trapped from generating photons.

[0032] The present disclosure is generally directed to combining band gap engineering with a self-aligned process for pLED small pitch arrays. Band gap engineering, which in some examples may refer to altering a band gap (e.g., a range of a solid material in which no electron state exists) of a material, such as through thin film deposition for impurity diffusion. A self-aligned process may, in some examples, refer to a semiconductor device manufacturing process in which features of the device may be used as a mask for fabricating other features (e.g., aligning with the masking feature). As will be explained in greater detail below, embodiments of the present disclosure may remove a portion of a first layer (e.g., via a shallow etch), band gap tune a second layer below the first layer (e.g., using impurity diffusion by thin film deposition), and removing a portion of the second layer (e.g., via a self-aligned process). The band gap engineering may advantageously remove surface-related defects and the self-aligned process may advantageously improve the uniformity of the band gap engineering (e.g., across multiple device structures) to advantageously allow reduced size LEDs with improved efficiency.

[0033] Features from any of the embodiments described herein may be used in combination with one another in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and claims.

[0034] The following will provide, with reference to FIGS. 1A-4, detailed descriptions of band gap engineering with a self-aligned process for fabricating semiconductor devices. Detailed descriptions of example semiconductor structures will be provided in connection with FIGS. 1A, IB, and 4. Detailed descriptions of example fabrication processes will also be provided in connection with FIGS. 2-3E.

[0035] FIG. 1A illustrates an example device 100 having a semiconductor device 102A and a semiconductor device 102B on a substrate 110. Device 100 may correspond to, for example, an LED array such that semiconductor device 102A and semiconductor device 102B may each correspond to LED structures. More specifically, device 100 may correspond to a pLED array having a small pitch size, such that an edge-to-edge distance between each LED may be approximately 1.5 pm, and each LED may be approximately 2 pm tall and approximately 1 pm wide, as illustrated in FIG. 1A, although other dimensions may be used. Each of semiconductor device 102A and 102B may include band gap engineered regions 124 and light emitting regions 126. Band gap engineered regions 124 may provide junction isolation (e.g., with respect to light emitting regions 124) that may improve efficiency by confining charge carriers to light emitting regions 126 without inducing surface-related defects. FIG. 1A illustrates an example device 100 having uniform impurity profile at the sidewalls (e.g., at band gap engineered regions 124) of each mesa (e.g., corresponding to semiconductor devices 102A and 102B), which in some examples may be ideal.

[0036] Band gap engineering may be accomplished by impurity diffusion by thin film deposition after mesa device isolation. FIG. IB illustrates a device 101 corresponding to device 100, illustrating band gap engineering via deposition of a film 122 after mesa device isolation (e.g., etching or otherwise forming structures corresponding to semiconductor devices 102A and 102B). Film 122 may correspond to, for example, a dopant or non-dopant film which, when applied to the desired regions (e.g., sidewalls surrounding light emitting regions 126) may diffuse to form band gap engineered regions 124.

[0037] The mesa step height (e.g., 2 pm, while having a gap of 0.5 pm between mesas) may cause uniformity challenges during impurity diffusion as deep trenches (e.g., trenches being deeper than the gap width) may be formed by the mesa etched structures. As illustrated in FIG. IB, film 122 may not be uniformly applied to desired sidewalls (e.g., within deep trenches), such that band gap engineered regions 124 may not be formed within the deep trenches, as illustrated in FIG. IB. As the pitch reduces, this non-uniformity may increase, such that scalability of this band gap engineering is reduced. FIG. IB illustrates a non-ideal example showing how band gap engineering may not be consistent across arrays with multiple etched devices. FIGS. 1A and IB illustrate simplified examples having two mesa structures, although in other examples multiple mesa structures may further exhibit uniformity issues. In addition, in some examples, undesired portions of the sidewalls (e.g., sidewalls above and / or below light emitting regions 126) may further exhibit impurities. In other words, this band gap engineering may not provide control over diffusion to specific desired regions.

[0038] FIG. 2 is a flow diagram of an exemplary method 200 for band gap engineering with a self-aligned process. The steps shown in FIG. 2 may be performed by any suitable system, apparatus, and / or device for fabricating or otherwise producing semiconductor devices. In one example, each of the steps shown in FIG. 2 may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which will be provided in greater detail below.

[0039] As illustrated in FIG. 2, at step 202 one or more of the systems described herein may remove at least a portion of a first layer that is over a second layer.

[0040] The systems described herein may perform step 202 in a variety of ways. In one example, removing at least the portion of the first layer may include applying a first mask on the first layer and performing a shallow etch at least partially through unmasked portions of the first layer. FIGS. 3A-3E illustrate simplified diagrams of a device 300 at various stages of fabrication corresponding to method 200. Device 300 may correspond to device 100, and may represent, in some examples, an LED device (e.g., a pLED array) and / or portions thereof. In other examples, device 300 may represent other devices, such as a vertical-cavity surfaceemitting laser (VCSEL), a backplane, etc.

[0041] FIG. 3A illustrates device 300 having a substrate 310, semiconductor layers 312 over substrate 310, light emitting region 320 over semiconductor layers 312, and semiconductor layers 314 over light emitting region 320. In some examples, semiconductor layers 312 and / or 314 may represent various layers of semiconductor materials, which may be simplified for illustrative purposes. Light emitting region 320 may correspond to an active layer of device 300, and may represent a light emitting portion of an LED (made of appropriate material such as phosphorus, nitride, etc., which may be based on desired light color emission), although in other examples may correspond to other active regions (and made of appropriate material).

[0042] FIG. 3B illustrates a mask 318 having been formed on semiconductor layers 314 in an appropriate pattern / arrangement such that semiconductor layers 314 may be accordingly etched (e.g., unmasked portions of semiconductor layers 314 being etched as illustrated in FIG. 3B) to form a shallow mesa structure 316. In some examples, the etch may correspond to a partial shallow material removal (e.g., a dry or wet etch), such as an etch depth of less than 300 nm (e.g., for a red pLED). In some examples, semiconductor layers 314 may be etched to expose light emitting region 320, although in LED examples, the etch may be limited to any depth that avoids exposing light emitting region 320 (e.g., no more than 500 nm thick).

[0043] Returning to FIG. 2, at step 204 one or more of the systems described herein may band gap tune the second layer.

[0044] The systems described herein may perform step 204 in a variety of ways. In one example, band gap engineer may optionally include applying a second mask. As illustrated in FIG. 3C, mask 319 may be applied to at least one sidewall of the first layer formed by the shallow etch.

[0045] Band gap tuning / engineering may include performing impurity diffusion to unmasked portions of the second layer. As illustrated in FIG. 3D, a film 322 (corresponding to a dopant and / or non-dopant film such as spin-on-glass or other appropriate file) may be applied (e.g., via an appropriate deposition process) over masked and unmasked portions of device 300, such that the desired impurity diffuses into desired regions.

[0046] In some examples, applying mask 319 to the sidewalls, as illustrated in FIG. 3C, may prevent external impurities from an applied film to diffuse through the top-most semiconductor layers (e.g., semiconductor layers 314) and only vertically through the light emitting region (e.g., light emitting region 320) such that mask 319 may allow further control of diffusion. Thus, as illustrated in FIG. 3D, the controlled diffusion may form band gap engineered regions 324 surrounding light emitting region 326 from light emitting region 320 without diffusing into semiconductor layers 314. Moreover, the shallow step height and reduced sidewall area for impurity coverage (as illustrated in FIG. 3D) may advantageously increase band gap tuning uniformity.

[0047] As illustrated in FIG. 2, at step 206 one or more of the systems described herein may remove at least a portion of the second layer.

[0048] The systems described herein may perform step 206 in a variety of ways. In one example, removing at least the portion of the second layer may include performing a second etch at least partially through the unmasked portions of the second layer. For example, FIG. 3E illustrates material removal through light emitting region 320 (e.g., band gap engineered regions 324) and into semiconductor layers 312. In other examples, etching may continue through semiconductor layers 312.

[0049] In some examples, removing at least the portion of the second layer may correspond to a self-aligned process. For instance, mask 318 and / or mask 319 may be used as part of the self-aligned process to further etch device 300 and form the resulting mesa structure (e.g., an LED) as illustrated in FIG. 3E. Further, in some examples, a sidewall angle formed by the second etch may differ from a sidewall angle formed by the shallow etch. Moreover, although method 200 and FIGS. 3A-3E illustrate a single mesa structure (e.g., single LED structure), in other examples the methods described herein may apply to multiple structures in arrays or other configurations, at any desired pitch (e.g., the pitch described with respect to FIG. 1A).

[0050] FIG. 4 illustrates a device 400, corresponding to, for example, device 100 and / or a finished version of device 300 corresponding to an example pLED using a self-aligned isolation process with band gap engineering. Device 400 may include semiconductor layers 412 (corresponding to semiconductor layers 312 as well as portions of semiconductor device 102A and / or 102B), semiconductor layers 414 (corresponding to semiconductor layers 314 as well as portions of semiconductor device 102A and / or 102B), band gap tuned material 424 (corresponding to band gap engineered regions 324 and / or 124), light emitting source 426 (corresponding to light emitting regions 326 and / or 126) that may be embedded in a band gap tuned material layer (e.g., such that light emitting source 426 may be surrounded by band gap tuned material 424 as sidewalls).

[0051] As further illustrated in FIG. 4, device 400 may include a lens 432 and a mirror 434. Lens 432 may, in some examples, correspond to a plens or other lens material that may be wider than light emitting source 426, and in other examples may correspond to other optical light extraction components. Mirror 434 may correspond to a reflective mirror surrounding light emitting source 426, and as illustrated in FIG. 4, may completely surround semiconductor layers 414, band gap tuned material 424, and at least partially surround semiconductor layers 412. In some examples, mirror 434 may be combined with passivation materials which may improve optical efficiency.

[0052] As illustrated in FIG. 4, semiconductor layers 412, band gap tuned material 424 (surrounding light emitting source 426), and semiconductor layers 414 may form a mesa structure having band gap tuned sidewalls surrounding a non-tuned region. More specifically, semiconductor layers 412 and semiconductor layers 414 may be free of band gap tuning or otherwise not include band gap tuned material 424 such that band gap tuned material 424 may be significantly limited to surrounding only light emitting source 426.

[0053] FIB SEM may detect the contrast between band gap engineered and light emitting or diode layers (e.g., band gap tuned material 424 and light emitting source 426). With the selfaligned process described herein, the shallow material removal (e.g., step 202 and / or FIG. 3B) may allow the top portion of the LED to be protected during the band gap engineering (e.g., step 204 and / or FIG. 3D), targeted for the active light emitting layers only (e.g., light emitting region 320). This is possible using a top-down band gap engineering (via impurity diffusion) and a shallow material removal as described herein. Contrast being only present in middle semiconductor layers may be indicative of a self-aligned process utilizing a shallow material removal.

[0054] Using a shallow etch to improve dopant (or non-dopant) film (such as spin-on-glass) uniformity is crucial to make sure that all pixels in a small pitch array lit up equally. If the band gap tuning is not uniform across the array (which may consist of over 1,000 x 600 pixels), then there will be significant dead pixels that do not light up and reduce the efficiency of the display.

[0055] As detailed above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those contained within the modules described herein. In their most basic configuration, these computing device(s) may each include at least one memory device and at least one physical processor.

[0056] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer- readable instructions. In one example, a memory device may store, load, and / or maintain one or more of the modules described herein. Examples of memory devices include, without limitation, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drives (HDDs), Solid-State Drives (SSDs), optical disk drives, caches, variations or combinations of one or more of the same, or any other suitable storage memory.

[0057] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor may access and / or modify one or more modules stored in the above-described memory device. Examples of physical processors include, without limitation, microprocessors, microcontrollers, Central Processing Units (CPUs), Field-Programmable Gate Arrays (FPGAs) that implement softcore processors, Application-Specific Integrated Circuits (ASICs), portions of one or more of the same, variations or combinations of one or more of the same, or any other suitable physical processor.

[0058] Although illustrated as separate elements, the modules described and / or illustrated herein may represent portions of a single module or application. In addition, in certain embodiments one or more of these modules may represent one or more software applications or programs that, when executed by a computing device, may cause the computing device to perform one or more tasks. For example, one or more of the modules described and / or illustrated herein may represent modules stored and configured to run on one or more of the computing devices or systems described and / or illustrated herein. One or more of these modules may also represent all or portions of one or more special-purpose computers configured to perform one or more tasks.

[0059] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, without limitation, transmissiontype media, such as carrier waves, and non-transitory-type media, such as magnetic-storage media (e.g., hard disk drives, tape drives, and floppy disks), optical-storage media (e.g., Compact Disks (CDs), Digital Video Disks (DVDs), and BLU-RAY disks), electronic-storage media (e.g., solid-state drives and flash media), and other distribution systems.

[0060] The process parameters and sequence of the steps described and / or illustrated herein are given by way of example only and can be varied as desired. For example, while the steps illustrated and / or described herein may be shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein may also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.

[0061] The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive.

[0062] Unless otherwise noted, the terms "connected to" and "coupled to" (and their derivatives), as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection. In addition, the terms "a" or "an," as used in the specification and claims, are to be construed as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives), as used in the specification and claims, are interchangeable with and have the same meaning as the word "comprising."

Claims

CLAIMS1. A method comprising: removing at least a portion of a first layer that is over a second layer; band gap tuning the second layer; and removing at least a portion of the second layer.

2. The method of claim 1, wherein removing at least the portion of the first layer comprises: applying a first mask on the first layer; and performing a shallow etch at least partially through unmasked portions of the first layer.

3. The method of claim 2, further comprising applying a second mask.

4. The method of claim 3, wherein the second mask is applied to at least one sidewall of the first layer formed by the shallow etch.

5. The method of any of claims 2 to 4, wherein band gap tuning the second layer further comprises performing impurity diffusion to unmasked portions of the second layer.

6. The method of claim 5, wherein removing at least the portion of the second layer further comprises performing a second etch at least partially through the unmasked portions of the second layer, and optionally wherein a sidewall angle formed by the second etch differs from a sidewall angle formed by the shallow etch.

7. The method of any preceding claim, wherein removing at least the portion of the second layer corresponds to a self-aligned process.

8. A device comprising: a first semiconductor layer; a second semiconductor layer; and a band gap tuned material layer between the first semiconductor layer and the second semiconductor layer.

9. The device of claim 8, wherein the device corresponds to a light emitting diode, LED, and the band gap tuned material layer includes an embedded light emitting source.

10. The device of claim 9, further comprising a lens material on the first semiconductor layer.

11. The device of claim 9 or claim 10, further comprising a reflective mirror surroundingat least the light emitting source.

12. The device of claim 11, wherein the reflective mirror includes a passivation material.

13. The device of any of claims 8 to 12, wherein the first semiconductor layer, the band gap tuned material layer and the second semiconductor layer forms a mesa structure.

14. The device of claim 13, wherein the band gap tuned material layer includes band gap tuned sidewalls surrounding a non-tuned region.

15. The device of claim 13 or claim 14, wherein the first semiconductor layer and the second semiconductor layer do not include band gap tuned regions.

Images