231 results about "Trench mosfet" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention provides a shield gate trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, according to the manufacturing method, a field oxide layer is formed twice (a first oxide layer and a second oxide layer), a polycrystalline silicon interlayer is introduced between the first oxide layer and the second oxide layer, and the polycrystalline silicon interlayer is only reserved on a side wall opposite to a non-floating shield gate layer after being etched twice, so that the field oxide layer is formed in the first oxide layer and the second oxide layer; and a floating shield grid layer is formed. As the floating shield grid layer is introduced to the side wall opposite to the non-floating shield grid layer, the field intensity of the middle area in the depth direction of the groove can be increased, and the overall voltage endurance capability is improved. The floating shield gate layer is introduced into the shield gate trench MOSFET structure, so that the voltage withstanding level of a device can be improved, and the voltage withstanding level of the device can be improved by utilizing a capacitive coupling effect between a part of the floating shield gate layer and a part of the floating shield gate layer and a capacitive coupling effect between a source electrode and the drain electrode. Therefore, gate-drain capacitance and source-drain capacitance of the device can be reduced, and switching speed of the device is improved.

The invention provides a low-on-resistance shield gate trench MOSFET fault diagnosis method and system, and relates to the technical field of MOSFET fault diagnosis, and the method comprises the steps: applying preset transient electrical excitation to a contact interface of a probe and a wafer bonding pad and an MOSFET before the steady-state on resistance of the MOSFET is measured; according to the obtained electrical response information of the contact interface and the MOSFET under each transient electrical excitation effect, constructing a transient feature vector; analyzing the transient feature vector according to a preset discrimination rule for contact part abnormity and a discrimination rule for device structure defects to determine whether an abnormity source is the contact part abnormity or the device structure defects; according to the determined abnormal source, the measured on-resistance value is adjusted, and the problem that the test system misjudges that the on-resistance of the device is abnormally increased due to instantaneous fluctuation of the contact resistance caused by the change of the microscopic geometrical shape of the tip of the probe is solved.

A superjunction trench MOSFET structure and its manufacturing method belong to the technical field of superjunction MOSFETs. A superjunction trench MOSFET structure includes an N+ substrate, a first cell structure, and a second cell structure. Among them, both the first cell structure and the second cell structure are regular hexagons. The first cell structure includes a first N pillar region and a first P pillar region surrounding the first N pillar region, and a first source trench is provided on the first N pillar region. The second cell structure includes a second N pillar region and a second P pillar region surrounding the second N pillar region, and a second source trench is provided on the second N pillar region. A number of second cell structures surround the first cell structure. The second cell structure further includes a gate trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different. By setting a regularly tiled cell structure in the shape of a regular hexagon and having an asymmetric double channel, the present application not only improves the channel density but also provides a good gate oxide protection effect.

A semiconductor device is provided which is a trench MOSFET with a vertical channel fin structure, capable of improving short-circuit tolerance and reducing gate capacitance while maintaining high channel density.A semiconductor 1 is configured so that a channel current flows in the vertical direction, and comprises: a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction in plan view, the plurality of trenches being arranged in the second direction; a first source region 3 of a first conductivity type; a second source region 4 of the first conductivity type and including a region having a fin structure at least partially partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type and having a fin structure partitioned by the plurality of trenches 2; a gate insulating film and gate electrodes disposed in the trenches 2; and a JFET region 8 of the first conductivity type and a body region 9 of the second conductivity type.The second source region 4 has a shallower depth from a surface than the first source region 3.

An SGT MOSFET comprising a substrate, an epitaxial layer, a masking dielectric layer, an interlayer dielectric layer, a source lead-out contact hole, and a source conductive layer and a method for manufacturing the SGT MOSFET are provided. The epitaxial layer is on an upper surface of the substrate and comprises a cellular trench structure, a terminal lead-out structure, a source lead-out structure, a body region, and a source region. The source lead-out structure comprises a source lead-out conductive layer. The masking dielectric layer and the interlayer dielectric layer are sequentially stacked above the epitaxial layer. The source lead-out contact hole penetrates the interlayer dielectric layer and the masking dielectric layer and extends into the source lead-out conductive layer, The source conductive layer fills the source lead-out contact hole. The masking dielectric layer is formed between the interlayer dielectric layer and the epitaxial layer and masks the third dielectric layer.

The invention provides a semiconductor device capable of improving short-circuit tolerance and reducing gate capacity while maintaining a high channel density in a trench MOSFET having a vertical channel fin structure. The present invention is provided with: a plurality of trenches (2) arranged in a second direction and having a long side direction in a first direction and a short side direction in the second direction in plan view; a first source region (3) of the first conductivity type; a second source region (4) of the first conductivity type including a region at least partially having a fin structure demarcated by the plurality of trenches (2); a second conductivity-type channel region (5) having a fin structure, the channel region (5) being partitioned by the plurality of trenches (2); a gate insulating film and a gate electrode disposed inside the trench (2); a JFET region (8) of the first conductivity type; and a body region (9) of a second conductivity type in which a channel current flows in the vertical direction, and in the semiconductor device (1), the depth of the second source region (4) from the surface is shallower than that of the first source region (3).

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

The invention relates to the technical field of power semiconductor devices, and discloses a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction control diode and a method. A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source electrode contact region and the P-type well region and goes deep into the trench MOSFET region of the first N-type epitaxial layer. According to the invention, the junction-controlled freewheeling diode is integrated at the side of the shield grid, so that the conduction voltage drop of the diode during freewheeling is reduced, and the reverse recovery time is greatly shortened. A high-turn-on-voltage diode is additionally arranged at the bottom of the shielding grid, the turn-on voltage is bipolar conduction, self-turn-on conduction is achieved under extreme working conditions such as surge, and the reliability of the device is improved. And the shielding grid electrode can form an electric field shielding effect during reverse voltage withstanding, so that electric field clamping at the bottom of the true grid electrode is realized.

The invention provides a chemical mechanical polishing method and device for polycrystalline silicon of a groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and relates to the technical field of preparation of the groove type MOSFET. According to the method, the polishing pressure partition control mode is adopted in the preliminary polishing stage, polycrystalline silicon in all areas is evenly removed, and the uniformity of the residual film thickness of the polycrystalline silicon is ensured. In the fine polishing stage, constant-pressure polishing is conducted, when a certain area reaches the polishing end point, the polishing pressure of the area is adjusted to be small so as to stop polishing of the area, the situation that the pressure is continuously adjusted when the area is close to the polishing end point is avoided, polishing rate drifting is avoided, end point control accuracy is improved, and polishing efficiency is improved. And the defects of over-polishing and under-polishing of the polycrystalline silicon at the groove structure are reduced. And in the residue removing and polishing stage, a third polishing pad with low hardness is adopted. The hardness of the polishing pad is small, the contact area between the polishing pad and the corner of the groove structure is increased, and residual polycrystalline silicon at the corner of the groove structure can be rapidly removed.

The present invention specifically relates to an accumulation-type wide bandgap semiconductor trench MOSFET device structure and a method for preparing the same. The structure comprises at least a substrate, an epitaxial layer, a source P+ region, and a gate electrode; an N+ current channel is provided below the gate electrode trench, and N-accumulation-type channels and / or P-inversion channels are provided on both sides of the gate electrode trench. The N+ current channel is prepared by ion implantation and is located in the epitaxial layer. The N-accumulation-type channels and / or P-inversion channels are formed by the lateral diffusion effect during ion implantation of the N+ current channel. The present invention forms the N+ current channel through a trench bottom ion implantation process, and utilizes the lateral diffusion effect of this process during ion implantation to naturally form the N-accumulation-type channel and / or P-inversion channel. Furthermore, the channel doping concentration and thickness can be carefully controlled by controlling the mask thickness of the trench sidewalls during ion implantation of the N+ current channel, thereby achieving the purpose of enhancing channel mobility and reducing device on-resistance without the need for additional processes.

The invention relates to a silicon carbide multi-channel longitudinal groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method thereof, and belongs to the technical field of silicon carbide semiconductors. The device comprises a substrate, a drift region arranged on the substrate and a plurality of grooves arranged in the drift region, wherein the plurality of grooves are periodically arranged along the transverse direction; the groove extends along a direction vertical to the surface of the substrate; gate oxide layers and gates located on the gate oxide layers are arranged on the two sides in the trenches respectively, channel regions are formed between the adjacent trenches and at the bottoms of the trenches in the drift region, source regions and body contact regions are formed in the channel regions, intermetallic dielectric layers are formed between the surfaces of the gates and the source regions, top-layer source metal is formed on the source regions, and bottom-layer source metal is formed on the body contact regions. And an ohmic contact layer is formed between the source electrode region and the top layer source electrode metal. According to the device disclosed by the invention, the inverted conduction channels are simultaneously formed in the side walls and the bottoms of the grooves, so that conduction current flows in parallel in the longitudinal and transverse directions, and the number of the effective conduction channels is remarkably increased.

A shielded gate trench MOSFET is disclosed, in which a first type body region is formed in an active region, and a first type electric field lowering region is formed in an adjacent region of a cross region between a first terminal trench and a trench end of a gate trench. The first type electric field lowering region is formed between the first type body region and the first terminal trench, and the first type electric field lowering region is free of the first type body region to enhance a breakdown voltage. At least one second type body region having a floating voltage and having a second conductivity type is formed in the first type electric field lowering region, and the second type body region is separated from the first type body region and the first terminal trench to further enhance the breakdown voltage.

The invention discloses a manufacturing method for improving the reliability quality of a p-type trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and belongs to the field of semiconductor power devices. On the basis of a p-type trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) process, the total dose resistance characteristic of the device is ensured through preposition of a junction pushing thermal process, and the single event burnout resistance of the device is improved through thermal oxidation thickening at the bottom of a trench. Meanwhile, after the bottom thermal oxidation thickening process is manufactured for the p-type anti-radiation trench MOSFET, the p-type concentration of silicon at the bottom of the trench is adjusted through p-type ion implantation, the problem that a device cannot be opened due to trench breaking is solved, the reliability quality of the p-type trench MOSFET is effectively improved, and the device meets the performance requirement for high reliability in the aerospace field.

The present application relates to SiC trench MOSFET super junction for enhancing reverse recovery performance and its preparation method, it includes drain, n+ substrate, n type drift region and two sources which are left-right symmetrical, n-drift region is equipped with n column region above, n column region both ends includes left-right symmetrical p1+ base region, high concentration first n+ source region and low concentration n1+ region formed super junction region, n column region top both ends includes left-right symmetrical p+ source region, p body region and high concentration second n+ source region, n column region top recess is equipped with p+ shielding region, n column region, p+ shielding region, p body region, second n+ source region jointly form the trench, the trench is equipped with a layer of gate oxide layer, the gate oxide layer is equipped with gate metal;The source is located at the left and right ends of the gate oxide layer respectively.The present application has the ability of strong reverse recovery, improve voltage resistance, reduce parasitic capacitance, improve switching speed, reduce on-resistance.

The present invention relates to the field of MOS semiconductor technology, and discloses a process for improving the cell density of a double trench MOSFET, including: injecting phosphorus elements of different concentrations into a semiconductor epitaxial layer to form an N substrate layer and a drift layer; continuing to ion-implant boron elements into the upper layer of the drift layer to form a P body region; ion-implanting at the center of the P body region to form an N well layer, and ion-implanting in the upper P body region to form a P well layer and a P-well layer; etching the surface of the semiconductor epitaxial layer by an etching process to form a rectangular groove; and depositing metal aluminum on both sides of the rectangular groove to form an L-type source. In the preparation process, the L-type source adopts an inwardly recessed design to contact the N well layer, and the prepared MOSFET device is not prone to heat accumulation and thus reduces the power consumption of the MOSFET device even when a smaller size is adopted. This process design using the source recess can greatly improve the cell density of the MOSFET device.

A flat contact trench MOSFET including a plurality of trenches, and a mesa between two trenches includes a half pitch P+ doped flat contact region and a half pitch N+ doped NP junction region, and a surface of the half pitch N+ doped NP junction region is level with the half pitch flat contact region. Furthermore, semiconductors devices including such flat contact trench MOSFETs and a process of manufacturing such semiconductor devices are provided.

The invention discloses a trench MOSFET with reverse fast recovery and a preparation method thereof. Relates to the technical field of semiconductors. According to the trench MOSFET disclosed by the invention, the source trench and the matched structure are additionally arranged between the adjacent gate trenches, so that a new current path is constructed. During reverse follow current, all current of a traditional trench MOSFET needs to flow through a body diode, however, in the structure, a source electrode oxide layer in a source electrode trench is thin, and a source electrode and a source region are short-circuited to form a built-in MOS channel. When the device is in a reverse working state, part of follow current can flow through the built-in MOS channel and does not depend on a body diode completely, if the thickness of the source electrode oxide layer is reduced properly, even all follow current can flow through the MOS channel and does not depend on the body diode completely, and therefore the flow path and the distribution condition of the current are changed. The current channel is optimized, so that the storage and recombination time of current carriers can be effectively reduced, and the reverse recovery performance is further improved.

A method for making a trench field effect transistor (TFET) may include forming a trench in a semiconductor layer, and forming a superlattice layer in the semiconductor layer extending along bottom and sidewall portions of the trench, the superlattice layer comprising a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source and drain regions defining, along with the superlattice layer, a channel region extending between the source and drain regions, and forming a gate within the trench comprising a gate insulator lining the trench and a gate electrode within the gate insulator.

A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type located above the drift layer, and a source region of the first conductivity type located above the channel layer. The second conductivity type is opposite to the first conductivity type. A plurality of trenches penetrates through the source region, the channel layer and a portion of the drift region. A gate electrode is located within each of the plurality of trenches via a gate insulating film and a plurality of shielding structures of the second conductivity type is located around the gate electrode. The plurality of shielding structures covers sidewalls and a bottom of the plurality of trenches. The plurality of shielding structures is arranged in an island-like manner.

The embodiment of the present specification provides a power semiconductor preparation method and a power semiconductor structure, wherein the semiconductor preparation method comprises: depositing a first N-type epitaxial layer on a silicon substrate, and depositing a second N-type epitaxial layer on the first N-type epitaxial layer; etching to remove the second N-type epitaxial layer of a target region, and depositing a third N-type epitaxial layer on the second N-type epitaxial layer and the target region; etching the first N-type epitaxial layer, the second N-type epitaxial layer and the third N-type epitaxial layer to form a trench; by setting an epitaxial layer with a medium doping concentration only on the upper part and the middle part outside the outermost peripheral trench of the terminal area, the space charge region is diffused outside the outermost peripheral terminal trench, the electric field strength at this position is reduced, the terminal structure withstand voltage is improved, the cell size is reduced without increasing the thickness of the oxide layer at the bottom of the trench of the separation gate trench MOSFET to ensure the terminal withstand voltage, and the on-resistance of the device is reduced.

The invention belongs to the technical field of semiconductors, and discloses a trench MOSFET device for improving switching loss, which comprises an epitaxial layer formed above a substrate; the trench gate structures are arranged at intervals and are formed above the epitaxial layer region; the first well region is formed between the trench gate structures which are arranged at intervals; the second well region is formed above the first well region and has a second conduction type; the third well region is formed above the first well region, is positioned on two sides of the second well region, and is respectively in contact with the vertical wall surfaces of the trench gate structure; the trench gate structure comprises a gate and a gate oxide layer wrapping the outer wall surface of the gate, groove sections arranged at intervals are distributed in the longitudinal straight line section, perpendicular to the wall surface, of the gate oxide layer in the longitudinal direction, and the groove sections are concaved outwards in the transverse direction from the gate. According to the invention, the gate-source capacitance and the gate-drain capacitance of the whole assembly can be improved only by optimizing the trench gate structure design, and the production cost is greatly reduced.

The present invention discloses an IGBT device with reverse conduction characteristics and a manufacturing method thereof, relating to the field of semiconductor device manufacturing, which includes the following steps: A. Preparation of an epitaxial layer, specifically including providing a semiconductor substrate, forming a first epitaxial layer on the surface of the semiconductor substrate, fabricating a reverse conduction region on the first epitaxial layer, and forming a second epitaxial layer on the first epitaxial layer; B. Preparation of a front-end terminal structure; C. Preparation of a front-end high-density trench MOSFET structure; D. Preparation of a circuit connection layer and a passivation layer; E. Preparation of the back side of the wafer. The present invention does not require a backside lithography process, saving costs, and the backside process reduces the risk of fragmentation. The front-end structure of the present invention can achieve a very high trench density, reducing the degree of wafer warping and enabling the production of high-density trench IGBTs on large wafer sizes.

The utility model provides a shield gate trench MOSFET layout and device, and the layout and device are characterized in that the edge position of a vapor deposition silicon oxide mask region is changed, a trench is staggered from a source polysilicon mask, and when the vapor deposition silicon oxide mask is used for etching, a hole can appear in a first trench of a cellular region, so that terminal polysilicon is connected with a contact hole, and the reliability of the mask region is improved. Therefore, not only can electric leakage of the source gate be avoided, but also the performance of avalanche energy (EAS for short) can be improved.

The application provides a silicon carbide trench power device and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. Aiming at the problems of high specific on-resistance, contradiction between gate oxide reliability and conductive channel and the like of a traditional silicon carbide trench MOSFET, a new structure and a manufacturing process are provided. The device comprises a semiconductor drain region, a drift region and a second conductive type semiconductor well region, a carrier diffusion layer is arranged at a first trench corner, the Z direction of the carrier diffusion layer passes through a semiconductor shielding region lead-out end, meanwhile, the semiconductor shielding region lead-out end of a side edge of the first trench is in stage distribution in the Z direction, the semiconductor shielding region directly below the first trench is in continuous distribution, and a second trench formed by over-etching silicon carbide is arranged in an interlayer dielectric layer. The carrier diffusion layer sacrifices the conductive channel which is not shielded by the lead-out end, and the second trench increases the ohmic contact area; by arranging a series of structures in the application, the specific on-resistance of the device can be significantly optimized.

The invention belongs to the technical field of semiconductor device design, and discloses a silicon carbide trench MOSFET device and a preparation method thereof, the MOSFET device comprises a plurality of gate trenches and source electrode contact layers, the source electrode contact layers are arranged between two adjacent gate trenches, the depth of the source electrode contact layers is lower than that of the gate trenches, and the source electrode contact layers are arranged between the gate trenches. The bottom end of each gate trench is provided with a first thick P + structure and a shielding structure, the upper end of the first thick P + structure is exposed out of the bottom of the gate trench, and the shielding structure wraps the first thick P + structure. The bottom end of each gate trench is provided with the shielding structure and the first thick P + structure to form a full-surrounding gate oxide shielding layer at the bottom of the trench, so that the gate oxide can be better protected from being damaged by a high electric field, and the reliability and the performance of the device are improved.

The application discloses a kind of shielded gate trench MOSFET cell structure and its manufacturing method, shielded gate trench MOSFET cell structure includes substrate, drift region and interlayer dielectric layer, the drift region is provided with deep groove, the deep groove is provided with shielded gate, intermediate oxide layer and control gate;The upper portion of the drift region is formed with body region and source region by injection, the interlayer dielectric is provided with source contact hole that is through source region and extends into body region, the sidewall and bottom of the source contact hole are formed with high-doped contact region by injection;The lower of the source contact hole is formed with charge balance region by high-energy ion injection.In the application, by setting charge balance region, the lateral depletion of adjacent drift region by shielded gate can be enhanced when shielded gate trench MOSFET device is in reverse bias state, the specific on-resistance of the device is reduced, the epitaxial layer drift region is accelerated, and the reliability and radiation resistance of the device are improved.