18 results about "Trench mosfet" patented technology

The application discloses a ground buried layer super-junction trench MOSFET device, belonging to the technical field of power semiconductor devices. The device is formed by a plurality of cells in parallel, and each cell structure comprises a first-conductivity-type substrate, a first-conductivity-type buffer layer, a first-conductivity-type drift region, a first-conductivity-type carrier storage layer, a second-conductivity-type super-junction, a second-conductivity-type well region, a second-conductivity-type base region, a second-conductivity-type ground layer, a first-conductivity-type source region, a trench dielectric layer, a gate electrode, a source electrode and a drain electrode. The device is grounded by island-shaped or strip-shaped super-junction through a longitudinally extended second-conductivity-type ground layer layout, the top cell structure and the lower drift region structure are separated by a buried super-junction structure, the conductive path is widened, and the JFET resistance of the device is reduced. The application solves the problem of switch performance deterioration caused by the floating buried super-junction charge storage, and is suitable for new energy, photovoltaic and other high-voltage and high-frequency power application scenarios with low on-resistance and high blocking voltage.

An improved reverse field-effect transistor semiconductor device and its fabrication method may include a source layer at the bottom and a drain at the top of a semiconductor substrate, and a vertical conduction channel between the source layer and the drain region, the trench being controlled by a trench gate electrode disposed in a gate trench lined with insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding the upper portion of the shielding trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding the lower portion of the shielding trench. A shielding electrode extends upward from the source layer in the shielding trench for electrically short-circuiting the source layer and the body region, wherein the shielding structure extends upward to the heavily doped drain region and is insulated from the heavily doped drain region to serve as a shielding electrode.

A SiC trench power device comprises at least one SiC MOSFET and a SiC super barrier rectifier (SBR) integrated together in each unit cell having at least one-step gate trench structure for the SiC MOSFET. The at least one step gate trench comprising a first top gate trench and at least one first bottom gate trench; the first top gate trench has a trench width larger than that of the at least one first bottom gate trench; a gate electrode of the SiC MOSFET is disposed in the first top gate trench surrounded with a first insulating film on a bottom region of the first top gate trench, and surrounded with a first gate oxide on sidewalls of the top step gate trench; the first insulating film fills up the at least one first bottom gate trench having a thickness greater than that of the first gate oxide; and a Y-shape grounded P-shield region surrounds the at least one first bottom gate trench for the first gate oxide electric field reduction and short circuit capability enhancement.

The application discloses a kind of semiconductor device technical field, specifically for a kind of split gate trench MOSFET, including device cell unit, the device cell unit includes first conductive type substrate and first conductive type drift region on first conductive type substrate, second conductive type well region is equipped in the upper portion of first conductive type drift region, first conductive type drift region is opened with dielectric slot and gate precipitate slot communicated with dielectric slot, and dielectric slot is filled with high-K oxide, the gate precipitate slot is filled with precipitate gate metal gate, oxide layer one coated on precipitate gate metal gate, precipitate gate silicon carbide coated on oxide layer, silicon carbide is used as the abutment between high-K oxide and precipitate gate metal gate in the application, silicon carbide can ensure the thermal stability of itself and silicon, to prevent the interaction between existing precipitate gate metal gate and high-k gate oxide layer from influencing threshold, to improve the performance of nanometer size MOSFET.

This invention discloses a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method. The structure includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p-type shielding layer, a p++ type source region layer, and an n++ type source region layer. The n-type drift layer is disposed on the first surface of the n++ type silicon carbide substrate. A superjunction structure is integrated below the p-type channel layer and the p-type shielding layer. The superjunction structure includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and p+ pillar regions are provided on both sides of the first n+ pillar region. A second n+ pillar region is provided on the outer side of each of the two p+ pillar regions. A p-type channel layer is provided on the n-type drift layer on both sides of the superjunction structure and the first trench. Adjacent p++ type source region layers and n++ type source region layers are provided on the p-type channel layer. A gate electrode is provided above the p-type shielding layer. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench, which reduces the on-resistance and the electric field in the gate oxide layer at the bottom corner of the trench.

In a trench MOSFET with a longitudinal channel fin structure, even when the trench spacing is reduced to increase the channel density, the decrease and deviation of the threshold voltage are suppressed. The semiconductor device (1) has: a plurality of trenches (2) which have a length direction in a first direction and a short side direction in a second direction when viewed from above, and are arranged in a plurality of trenches in the second direction; a source region (3) of a first conductivity type, which includes a fin structure divided by the plurality of trenches (2); a channel region (5) of a second conductivity type of fin structure, which is divided by the plurality of trenches (2); and a body region (9) of a second conductivity type, the channel region (5) being connected to the body region (9), and a channel current flowing longitudinally in the channel region (5), the channel region (5) having a first channel region (5A) connected to the lower surface of the source region (3) and a second channel region (5B) disposed below the first channel region (5A), the impurity concentration of the second conductivity type in the first channel region (5A) being higher than that in the second channel region (5B).

The application relates to the technical field of semiconductor device manufacturing, in particular to a trench MOSFET device capable of reducing high-frequency switching noise and a manufacturing method thereof. The trench MOSFET device comprises a substrate, an epitaxial layer, a doped region, a JTE region, a gate, a first implantation buried layer, a second implantation buried layer and a source metal layer. By optimizing the structure of the JTE region and the implantation buried layer, the high-frequency switching noise is effectively reduced, and the reliability and performance of the device are improved. In addition, by specific trench design and process steps, the voltage resistance and electrical characteristics of the device are further enhanced.

The application provides a manufacturing method of an active region and a termination region of a semiconductor device with independent control of doping concentration and a manufacturing method of the semiconductor device. The manufacturing method of the active region and the termination region comprises the following steps: providing a semiconductor substrate, the semiconductor substrate comprising an active region and a termination region, the active region comprising at least one vertical channel; covering a doping layer in the vertical channel, the doping layer being made of the same material as the covered vertical channel, and the doping layer having a doping concentration greater than that of the covered vertical channel; and making the doping layer and the vertical channel covered by the doping layer have the same doping concentration through a high-temperature thermal diffusion process. The above technical solution independently controls the doping concentration of the active region and the termination region through selective epitaxial growth and a thermal diffusion process. This method provides robustness for high-voltage trench MOSFET, TMBS and IGBT devices.

This invention provides a gallium nitride trench MOSFET device and its fabrication method. The device includes a drain metal, a GaN substrate, and an n-type MOSFET arranged sequentially from bottom to top. ‑ A GaN drift layer, a current blocking layer, and an n-type wide bandgap conductive layer are included. An source metal is deposited on the upper surface of the n-type wide bandgap conductive layer. The upper surface of the n-type wide bandgap conductive layer is etched downwards with a penetration layer reaching the n-type wide bandgap conductive layer. ‑ - Trenches in contact with the GaN drift layer, wherein protrusions protruding from the n ‑ The gate metal on the upper surface of the GaN drift layer is provided, and a gate dielectric layer is disposed between the gate metal and the trench. By replacing the traditional p-GaN layer with a current blocking layer and an n-type wide bandgap conductive layer, the doping activation problem, substrate mismatch defect problem and Mg secondary passivation risk in the p-GaN growth process can be avoided from the root. This provides a key solution for overcoming the bottlenecks of existing technologies and improving the performance stability and mass production yield of enhancement-mode GaN MOSFETs.

This application belongs to the field of semiconductor technology and provides a gallium nitride vertical trench MOSFET device, fabrication method, and chip. By forming a first P-type isolation region between the gallium nitride drift layer and the gate insulating layer, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the first N-type doped region, and multiple second P-type isolation regions between the gallium nitride drift layer and the second N-type doped region, the first P-type isolation region and the second P-type isolation region form a depletion region with the gallium nitride drift layer with only one photomask layer. At the same time, the electric field between the source and drain of the device is homogenized, and the electric field is avoided from concentrating on the gate insulating layer, thereby achieving the purpose of improving the breakdown voltage of the gallium nitride vertical trench MOSFET device.

This invention discloses a dual-gate trench MOSFET with a shielded gate electrode in a stepped trench. Each cell includes a first MOSFET with a single-step gate trench, or integrates a first MOSFET and a super-barrier rectifier, or a first MOSFET and a second MOSFET. The single-step gate trench contains a shielded gate electrode. The top trench width of the single-step gate trench is smaller than the bottom trench width, achieving a reduction in the device cell size. The improved structure of this invention effectively reduces the specific on-resistance and reverse recovery time of the device.

This invention relates to the field of power semiconductor technology, specifically providing a method for fabricating a shielded gate trench MOSFET device, aiming to solve the problem of poor gate oxide uniformity in existing SGT devices. To this end, the fabrication method of this invention includes: providing a semiconductor substrate; the semiconductor substrate comprising a substrate of a first conductivity type and an epitaxial layer of the first conductivity type on the substrate; forming a trench in the epitaxial layer; forming a first dielectric layer and a shielded gate in the trench, wherein the first dielectric layer covers the shielded gate, and a groove is formed on the top surface of the first dielectric layer near the trench sidewall; etching the first dielectric layer to a predetermined depth, retaining the top surface of the first dielectric layer above the shielded gate and forming a ridge near the trench sidewall on the top surface of the retained first dielectric layer, and forming a valley between the ridge and the trench sidewall; forming a gate oxide layer covering the valley of the retained first dielectric layer and the trench sidewall; and forming a control gate.

This invention discloses an optimized cell layout structure for a trench MOSFET and its fabrication method. The optimized cell layout structure of the trench MOSFET includes an epitaxial layer, within which multiple trench structures extending in the thickness direction and of different depths are formed. The trench walls are provided with a gate oxide layer and filled with a polysilicon gate. A first well region and a second well region with different extension depths are formed between the trenches, and a corresponding conductivity-type doped region is formed on the surface of each well region. By constructing trench and well region structures of different depths, this invention enables the formation of channel units with different conduction characteristics inside the device, achieving current distribution and flow when the device is turned on, improving current density concentration, enhancing current distribution uniformity, and improving device reliability.

The present application provides a trench power MOSFET assembly and a manufacturing method thereof. The trench power MOSFET assembly includes a substrate, an epitaxial layer, a buffer region, a first type of trench MOSFET, a second type of trench MOSFET, and a trench capacitor. The epitaxial layer is disposed on the substrate, and the buffer region is formed in the epitaxial layer. The first type of trench MOSFET includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is located in the epitaxial layer, the first source electrode is located on a top surface of the epitaxial layer, and the first drain electrode is located on a bottom surface of the substrate. The second type of trench MOSFET includes a second gate electrode, a second source electrode, and a second drain electrode, wherein the second gate electrode is located in the epitaxial layer, the second source electrode and the second drain electrode are both located on the top surface of the epitaxial layer, the first gate electrode is electrically connected to the second drain electrode, and the first source electrode is electrically connected to the second source electrode. The two ends of the trench capacitor are electrically connected to the first drain electrode and the second gate electrode, respectively.

A kind of trench MOSFET with high-speed switch. It relates to the field of semiconductor technology.The utility model trench MOSFET by adding source trench and supporting structure between adjacent gate trenches, build new current path.In reverse freewheeling, the current of traditional trench MOSFET needs to be all flowed through body diode, and in the structure, the source oxide layer in source trench is thinner, and the source and source region are short-circuited to form built-in MOS channel.When the device is in reverse working state, part of freewheeling current can flow through this built-in MOS channel, no longer completely rely on body diode, if the thickness of source oxide layer is appropriately reduced, even the whole freewheeling current can flow through MOS channel, completely not rely on body diode, so as to change the current flow path and distribution situation.This optimization of current channel can effectively reduce the storage and recombination time of carriers, and then improve the reverse recovery performance.

This application provides a silicon carbide trench MOSFET with integrated heterojunction diode and its fabrication method. Applied to the field of power semiconductor technology, it includes: an N+ type SiC substrate; an N- type SiC drift layer disposed above the N+ type SiC substrate; a P-type base region disposed above the N- type SiC drift layer; an N+ type source region disposed above the P-type base region; a trench gate structure including: a gate trench, a gate oxide layer, and a gate conductive material, the gate oxide layer being disposed on the inner wall of the gate trench, and the gate conductive material filling the gate trench; a source metal electrically connected to both the N+ type source region and the P-type base region; and a drain metal disposed below the N+ type SiC substrate. This invention reduces on-resistance, gate-drain capacitance, and switching losses, and fundamentally eliminates the risk of bipolar degradation.

In a trench MOSFET with a vertical channel fin structure, the on-resistance is reduced while ensuring short-circuit tolerance. A semiconductor device (1) has a plurality of trenches (2) arranged in a plan view with a longitudinal direction in a first direction and a transverse direction in a second direction; a first source region (3) of a first conductivity type, at least part of which is subdivided by the plurality of trenches (2); and a channel region (5) of a second conductivity type, which is in contact with a lower surface of the first source region (3) and is subdivided by the plurality of trenches (2). The channel region (5) is connected to a body region (9), and a channel current flows vertically through the channel region (5).The length in the first direction of a gate electrode (7) located inside the trench (2) is greater than the length in the first direction of a JFET region (8). The impurity concentration of the JFET region (8) is higher than that of the drift region (10). Both dimensions of the body region (9) and the JFET region (8) in a depth direction from a lower section of the trench (2) are greater than 0.5 µm.

This invention provides a method for fabricating a gallium nitride MOSFET device and a gallium nitride trench MOSFET device based on full ion implantation. The fabrication method includes: preparing a single-crystal undoped gallium nitride substrate; implanting donor ions or combinations thereof on one side of the single-crystal undoped gallium nitride substrate to form a drain contact layer; implanting compensation / charge-regulating ions or combinations thereof on the other side of the single-crystal undoped gallium nitride substrate away from the drain contact layer, followed by a second implantation of donor ions or combinations thereof; and annealing in a nitrogen-containing active atmosphere to form an electron blocking layer, a source contact layer, and a u-GaN drift layer between them; forming a drain on the side of the drain contact layer away from the u-GaN drift layer, and forming a gate and a source on the side of the source contact layer away from the u-GaN drift layer. In this scheme, the drain contact layer, electron blocking layer, and source contact layer are all formed by ion implantation, avoiding the tailing effect and achieving high activation efficiency, thus ensuring consistent device performance.