552 results about "Trench mosfet" patented technology

A method for manufacturing a trenched metal oxide semiconductor field effect transistor (MOSFET) cell includes the steps of opening a gate trench in a semiconductor substrate and implanting ions of a first conductivity type same as a conductivity type of a source region with at least two levels of implanting energies to form a column of drain-to-source resistance reduction regions below the gate trench. The method further includes steps of forming a gate in the gate trench and forming body and source regions in the substrate surrounding the gate trench. Then the MOSFET cell is covered with an insulation layer and proceeds with applying a contact mask for opening a source-body contact trench with sidewalls substantially perpendicular to a top surface of the insulation layer into the source and body regions. The method further includes a step of implanting ions of a second conductivity type opposite the first conductivity type with at least two levels of implanting energies to form a column of electrical field reduction regions below the source-body contact trench next to the column of drain-to-source resistance reduction regions to function as charge balance regions to the drain-to-source resistance reduction regions.

A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.

The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N⁺ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate trench so as to interpose an insulator; a channel region formed on the N type epitaxial region; a source region formed on the channel region; a source electrode formed on the source region; a source trench extending from the front surface into the N type epitaxial region; and a trench-buried source electrode positioned in the source trench so as to interpose an insulator, wherein the source electrode contacts with the trench-buried source electrode.

An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.

In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.

In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle α. The trench is formed with the standard deviation σ in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2σ] to [(90 degrees)−tan⁻¹ (0.87×tan α)−2σ] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)−tan⁻¹ (0.87×tan α)] can be obtained.

A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.

A trench MOSFET with split gates and diffused drift region for on-resistance reduction is disclosed. Each of the split gates is symmetrically disposed in the middle of the source electrode and adjacent trench sidewall of a deep trench. The inventive structure can save a mask for definition of the location of the split gate electrodes. Furthermore, the fabrication method can be implemented more reliably with lower cost.

A trench MOSFET comprising a plurality of transistor cells having shielded trenched gates and multiple trenched floating gates as termination region is disclosed. The trenched floating gates have trench depth equal to or deeper than body junction depth of body regions in termination area. In some preferred embodiments, the trenched floating gates in the termination area are implemented by using shielded electrode structure.

A semiconductor power device comprising a plurality of trench MOSFETs integrated with Schottky rectifier in same cell is disclosed. The invented semiconductor power device comprises a tilt-angle implanted drift region having higher doping concentration than epitaxial layer to reduce Vf in Schottky rectifier portion and to reduce Rds in trench MOSFET portion while maintaining a higher breakdown voltage by implementation of thick gate oxide in trench bottom of trenched gates. Furthermore, the invented semiconductor power device further comprises a Schottky barrier height enhancement region to enhance the barrier layer covered in trench bottom of trenched source-body-Schottky contact in Schottky rectifier portion.

An integrated circuit includes a plurality of trench MOSFET and a plurality of trench Schottky rectifier. The integrated circuit further comprises: tilt-angle implanted body dopant regions surrounding a lower portion of all trench gates sidewalls for reducing Qgd; a source dopant region disposed below a bottom surface of all trench gates for functioning as a current path for preventing a resistance increased caused by the body dopant regions.

A super-junction trench MOSFET with split gate electrodes is disclosed for high voltage device by applying multiple trenched source-body contacts with narrow CDs in unit cell. Furthermore, source regions are only formed along channel regions near the gate trenches, not between adjacent trenched source-body contacts for UIS (Unclamped Inductance Switching) current enhancement

A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect. The MOSFET device further includes a second Zener diode connected between a gate metal and a source metal of the MOSFET device for functioning as a gate-source (GS) clamp diode, wherein the GD clamp diode includes multiple back-to-back doped regions in the polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on the insulation layer above the MOSFET device having a lower breakdown voltage than a gate oxide rupture voltage of the MOSFET device.

A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.

A semiconductor power device comprising a termination area that includes a trenched gate runner electrically connected to a trenched gate of said semiconductor power device. The semiconductor power device further includes a trenched field plate disposed in a trench opened in the termination area and the trenched field plate is electrically connected to the trenched gate runner. A gate runner contact trench and a field plate contact trench opened through an insulation layer covering the gate runner and the trenched field plate for extending into a doped gate dielectric filling in the trenched gate runner and the field plate wherein the gate runner contact trench and the field plate contact trench filled with a gate runner contact plug and a field plate contact plug respectively. A gate metal disposed on top of the insulation layer to electrically contact the gate runner contact plug and the field plate contact plug for electrically interconnecting the trenched gate runner and the trenched field plate.

PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.