242 results about "Reverse recovery" patented technology

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention relates to a rapid estimation method and device for MMC loss in an electromagnetic transient model, and a medium. The method comprises the following steps: S1, constructing a Thevenin equivalent model of an MMC; s2, on the basis of an MMC Thevenin equivalent model, discretizing a sub-module capacitor based on a numerical integration method to establish an on-state loss model of the sub-module; s3, correcting to obtain the turn-on loss and turn-off loss of the IGBT and the reverse recovery loss of the diode; s4, in one simulation step, on-state loss is obtained through calculation based on an on-state loss model, the total switching frequency is obtained through calculation according to port data of the Thevenin equivalent model, and switching loss is obtained through combination of on-state loss and off-state loss of an IGBT and reverse recovery loss and switching frequency of a diode; and S5, taking the sum of the on-state loss and the switching loss as total loss. Compared with the prior art, the method has the advantages that real-time updating in the simulation step can be realized, the calculation complexity is controllable, and the overhead is remarkably reduced while the engineering precision is ensured.

The invention discloses an FCE diode and a manufacturing method thereof. The cathode metal is provided with a trench isolation region, cathode N + regions and cathode P + regions, the cathode N + regions and the cathode P + regions are transversely and alternately arranged, the trench isolation region isolates the cathode N + regions from the cathode P + regions, and the thickness of the trench isolation region exceeds 2 microns of the cathode N + regions and the cathode P + regions And then a plasma storage region, a field stop region, a base region, an anode P region and anode metal are sequentially arranged. The thickened trench isolation region is indispensable for improving the current density uniformity near the cathode, and can weaken low-frequency oscillation and reduce conduction voltage drop; the thickened plasma storage region can weaken low-frequency oscillation, improve the current density uniformity near the anode and reduce reverse recovery energy under severe or extreme conditions; the two measures can also ensure that the base region is greatly thinned on the premise of enlarging the safe working region, so that the loss is reduced. By optimizing and compromising the structural parameters of each area, the FCE diode can achieve the beneficial effects of self-clamping, low loss, uniform current density, no high-frequency oscillation, slight low-frequency oscillation and wide safe working area.

The invention belongs to the field of semiconductor devices, provides a gallium nitride high-electron-mobility transistor integrated with a Schottky diode and a preparation method of the gallium nitride high-electron-mobility transistor, and aims to solve the problem that a conventional gallium nitride high-electron-mobility transistor (GaN HEMT) lacks a body diode. According to the invention, monolithic integration of the SBD and the GaN HEMT is realized through structural design, a low-impedance path is provided for reverse current, and the integration mode not only retains the original high performance characteristic of a GaN device, but also additionally endows the GaN device with reverse conduction and reverse recovery capabilities; moreover, through the structural design, the SBD can be synchronously completed on the basis of the existing GaN HEMT process, a special process or new equipment is not needed, and the cost is effectively controlled while the performance improvement is ensured; compared with an external interconnection diode scheme, parasitic inductance caused by lead bonding is eliminated, the voltage overshoot and ringing phenomena in the switching process are remarkably reduced, high-frequency switching application is facilitated, and switching loss can be greatly reduced.

The invention relates to the technical field of data processing, in particular to a high-frequency diode conduction loss characteristic test system, which comprises an acquisition module, a first judgment module, a second judgment module, a first determination module, a second determination module, an adjustment module and an output module. According to the method, multiple key data are collected, rapid screening is carried out according to forward voltage and reverse recovery charges, then, hidden defects of abnormal dynamic relevance of parameters are analyzed and identified by introducing shell temperature, and finally, a high-loss diode is obtained; the trend abnormity is identified by using the space-time distribution characteristics of the high-loss diode, and the loss reason is accurately detected through the voidage fluctuation mode; and meanwhile, based on a self-adaptive adjustment mechanism fed back by the test accuracy, a test report is finally output, so that the problems of low identification accuracy of the high-loss diode and low detection accuracy of loss reasons caused by excessive dependence on static parameters and incapability of adapting to complex and changeable working conditions are effectively solved.

The invention relates to the technical field of power semiconductor devices, and discloses a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction control diode and a method. A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source electrode contact region and the P-type well region and goes deep into the trench MOSFET region of the first N-type epitaxial layer. According to the invention, the junction-controlled freewheeling diode is integrated at the side of the shield grid, so that the conduction voltage drop of the diode during freewheeling is reduced, and the reverse recovery time is greatly shortened. A high-turn-on-voltage diode is additionally arranged at the bottom of the shielding grid, the turn-on voltage is bipolar conduction, self-turn-on conduction is achieved under extreme working conditions such as surge, and the reliability of the device is improved. And the shielding grid electrode can form an electric field shielding effect during reverse voltage withstanding, so that electric field clamping at the bottom of the true grid electrode is realized.

The invention discloses a hybrid self-switching bidirectional wireless switched reluctance motor driving system provided and realized by the invention. An independent demagnetization loop is arranged on the motor side, rapid demagnetization is allowed, and energy recovery is achieved. The system wirelessly drives a multi-phase SRM through a single power transfer channel using a single resonant frequency to reduce coupling between multiple power channels. When the WPT system is in forward power, the LCC-S compensation network is adopted to drive the motor load, and the advantage of constant voltage gain when the load changes is achieved; the LCC-LCC / S hybrid self-switching compensation network is adopted to realize charging of a battery load, and has a constant voltage / constant current characteristic; and when the WPT system has negative power, the LCC-LCC compensation network is adopted to realize reverse recovery of energy, and energy interconnection between the motor and the power grid is realized. In addition, an SR motor does not need to be specially designed, and the system has the remarkable advantages of phase current balance, flexible transmission distance, high integration level, maintenance-free property and the like.

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

This invention relates to the field of power system and energy management technology, and in particular to a collaborative power supply system for energy storage batteries and distributed power sources in microgrids. The invention integrates a reverse recovery charge dynamic clamping module into the gate drive circuit of an IGBT module. The reverse recovery charge dynamic clamping module includes: a di / dt sensing unit, a pulse generation unit, a negative voltage injection unit, and a gate clamping execution unit. The di / dt sensing unit collects the rate of change of current flowing through the emitter of the IGBT module in real time, and triggers the pulse generation unit when the rate of change of current exceeds a set threshold. The pulse generation unit generates a delayed control pulse to control the negative voltage injection unit to switch the output voltage to a target voltage value and maintain it for a specified time. The gate clamping execution unit locks the gate potential of the IGBT module based on the target voltage value. This invention ensures that the system maintains low electromagnetic interference, high energy efficiency conversion, and long-term operational reliability during millisecond-level seamless switching.

An electric circuit in which a first switching element and a first diode element are connected in antiparallel to form an upper arm and a second semiconductor element and a second diode element are connected in antiparallel to form a lower arm, and the upper arm and the lower arm are connected in series. A gate current path in one of the upper and lower arms and a reverse recovery path in the other one of the upper and lower arms are disposed close enough and extend at least partially in parallel to each other, so as to generate mutual inductance by the reverse recovery current flowing through the reverse recovery path and the gate current flowing through the gate current path.

This invention discloses an IGBT parallel module having at least two IGBTs connected in parallel, each IGBT configured with a paired FRD; the two parallel IGBTs are designated as first and second IGBTs, and their corresponding paired FRDs are designated as first and second FRDs, respectively. A bridging FRD is also configured between the first and second FRDs; a portion of the anode pins of the bridging FRD is connected to the anode pins of the first FRD via bonding wires, and another portion of the anode pins of the bridging FRD is connected to the anode pins of the second FRD via bonding wires; when current imbalance occurs between the first and second FRDs, the bridging FRD reduces the rated current of the first and second FRDs and performs current buffering, thereby reducing the current density of each FRD; the pin connection structure of the anode of the bridging FRD makes the stray inductance of the bridging FRD greater than that of either the first or second FRD, thereby improving the softness of the reverse recovery of the first and second FRDs. This invention can prevent failure defects caused by current concentration.

The invention provides a super junction semiconductor power device which comprises a heavily doped first conductive type substrate, and a first conductive type epitaxial layer is arranged on the heavily doped first conductive type substrate; a groove is formed in the first conductive type epitaxial layer; second conductive type doped monocrystalline silicon is filled in the groove to form a second conductive type columnar epitaxy; first conductive type columnar epitaxy and second conductive type columnar epitaxy which are alternately distributed are formed in the first conductive type epitaxial layer; the doping concentration of the second conductive type columnar epitaxy is greater than that of the first conductive type columnar epitaxy; a plurality of heavily doped first conductive type impurity injection regions extending into the first conductive type columnar epitaxy are distributed on the side walls of the two sides of the second conductive type columnar epitaxy; according to the invention, the soft reverse recovery characteristic can be obtained, the electromagnetic radiation in the reverse recovery process of the device is reduced, and meanwhile, the voltage-resistant stability of the device is improved.

A method for reducing or eliminating current and voltage transients in a device including: providing the device, wherein the device comprises a transistor with a gate; and controlling the gate, wherein the gate is turned off to a non-zero value in a presence of the positive current flow and wherein the gate is turned on in a presence of the negative current flow; reducing the negative current flow; and reducing or eliminating current and voltage transients in the device.

The invention discloses a semiconductor device and an electronic apparatus, and the semiconductor device comprises a semiconductor substrate which comprises an insulated gate bipolar transistor region and a fast recovery diode region, and a collector layer is at least partially located in the insulated gate bipolar transistor region; the short circuit region is located in the fast recovery diode region; the rated current of the insulated gate bipolar transistor area is set to be I1, the rated current of the fast recovery diode area is set to be I2, and I1 and I2 meet the relational expression that I2 is smaller than or equal to I1 / 3. Therefore, the rated current of the fast recovery diode region can be small, and when the semiconductor device is used as a power chip in a PFC circuit, the area of the fast recovery diode region can be reduced, so that the whole semiconductor device is more miniaturized, the cost is reduced, the arrangement of the semiconductor device is convenient, the reverse recovery loss can be reduced, and the reliability of the semiconductor device is improved. And the heat dissipation performance can be improved.

The invention provides a manufacturing method of a field effect transistor, the field effect transistor and a layout structure, and the transistor enables a shielding grid and a grid electrode to be separately placed, enables the shielding grid to be in uniform contact with source electrode metal, facilitates the timely response to state conversion, and avoids the local breakdown of a device. And the oxide layer is thinned at the top end of the shield gate, and injection of reverse recovery charges is reduced during reverse recovery. By adjusting the position of the shield gate and reducing the thickness of the shield gate oxide layer, the Eas capability of the device is effectively improved, the reverse recovery time of the transistor is shortened, the reverse recovery capability of the transistor is improved, and the reliability is improved.

The invention provides an FRD chip detection method and platform. According to the method, a switch device and an inductive load module are controlled, a preset forward conduction working condition is established at an FRD chip, and when the FRD chip is in a forward conduction state, the switch device is controlled to switch the conduction state, so that reverse voltage is applied to the two ends of the FRD chip, and the reverse recovery process of the FRD chip is triggered. And then, synchronously acquiring the terminal voltage waveform of the FRD chip and the inductive current waveform associated with the inductive load module to obtain test data. Then, determining a reverse recovery characteristic parameter and an overvoltage characteristic parameter of the FRD chip under the inductive load working condition based on the test data, and finally, evaluating the FRD chip based on the reverse recovery characteristic parameter and the overvoltage characteristic parameter. Therefore, the technical problem that the dynamic performance of the FRD chip under the inductive load cannot be accurately evaluated under the traditional test condition is solved.

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a semiconductor device. The semiconductor structure comprises a semiconductor substrate layer; the buffer layer and the drift layer are sequentially stacked on the first surface of the semiconductor substrate layer; the doping concentration of the buffer layer is gradually reduced in the direction from the semiconductor substrate layer to the drift layer; a first doped region in the buffer layer; wherein the conduction type of the buffer layer is the same as that of the drift layer, and is opposite to that of the first doped region; the doping concentration of the drift layer is smaller than or equal to the doping concentration of the buffer layer. The semiconductor structure can effectively suppress voltage and current oscillation and overshoot phenomena, and realizes a softer reverse recovery characteristic.

The application discloses a SiC power device with local lifetime control and a manufacturing method thereof, which can be applied to the technical field of semiconductor devices. The device comprises an N-doped SiC substrate layer, an N-doped epitaxial layer grown on the substrate layer, a cell region and a termination region prepared on the epitaxial layer, and a first lifetime control region prepared between the cell region and the termination region. The first lifetime control region wraps a transition region well structure between the cell region and the termination region. In this way, by adding a local lifetime control region in the transition region, the number of minority carrier injection from the transition region to the termination region is reduced, local recombination and local reverse recovery speed are increased, and the response speed of the termination region is optimized.

The present invention effectively reduces the reverse recovery loss of a diode region in an RC-IGBT. A semiconductor device 1 comprises an IGBT region 31 and a diode region 32 on a single chip. A trench 6 (first trench) of the IGBT region 31 and a trench 6 (second trench) of the diode region 32 are both wide trenches. The diode region 32 comprises: a first semiconductor layer 20 of a second conductivity type, provided on the top side of the drift layer 2 of a first conductivity type; and a second semiconductor layer 23 of the first conductivity type and a charge carrier discharge layer 26 of the second conductivity type, provided on the back side of the drift layer 2 of the first conductivity type. The second semiconductor layer 23 and the charge carrier discharge layer 26 are arranged alternately.

The present application relates to SiC trench MOSFET super junction for enhancing reverse recovery performance and its preparation method, it includes drain, n+ substrate, n type drift region and two sources which are left-right symmetrical, n-drift region is equipped with n column region above, n column region both ends includes left-right symmetrical p1+ base region, high concentration first n+ source region and low concentration n1+ region formed super junction region, n column region top both ends includes left-right symmetrical p+ source region, p body region and high concentration second n+ source region, n column region top recess is equipped with p+ shielding region, n column region, p+ shielding region, p body region, second n+ source region jointly form the trench, the trench is equipped with a layer of gate oxide layer, the gate oxide layer is equipped with gate metal;The source is located at the left and right ends of the gate oxide layer respectively.The present application has the ability of strong reverse recovery, improve voltage resistance, reduce parasitic capacitance, improve switching speed, reduce on-resistance.

The invention discloses a trench MOSFET with reverse fast recovery and a preparation method thereof. Relates to the technical field of semiconductors. According to the trench MOSFET disclosed by the invention, the source trench and the matched structure are additionally arranged between the adjacent gate trenches, so that a new current path is constructed. During reverse follow current, all current of a traditional trench MOSFET needs to flow through a body diode, however, in the structure, a source electrode oxide layer in a source electrode trench is thin, and a source electrode and a source region are short-circuited to form a built-in MOS channel. When the device is in a reverse working state, part of follow current can flow through the built-in MOS channel and does not depend on a body diode completely, if the thickness of the source electrode oxide layer is reduced properly, even all follow current can flow through the MOS channel and does not depend on the body diode completely, and therefore the flow path and the distribution condition of the current are changed. The current channel is optimized, so that the storage and recombination time of current carriers can be effectively reduced, and the reverse recovery performance is further improved.

The invention relates to an ultrahigh-voltage fast recovery diode and a preparation method thereof, and the method comprises the steps: selecting an N-drift layer, and growing an oxide layer on the front surface of the N-drift layer; preparing a P-type anode layer on the front surface of the N-drift layer; preparing an N-type buffer layer on the back surface of the N-drift layer; preparing a plurality of P + regions which are arranged at intervals along the transverse direction on the back surface of the N-type buffer layer; and preparing an N + cathode layer on the back surface of the N-type buffer layer. According to the preparation method of the ultrahigh-voltage fast recovery diode, the N-type buffer layer is designed between the N-type drift layer and the N + cathode layer, and the plurality of P + regions are injected into the region of the N-type buffer layer at intervals to form a staggered P + N structure, so that the forward conduction voltage drop of the diode is not sacrificed while the reverse recovery softness of the diode is improved.

Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, a superjunction semiconductor device and a method of manufacturing the same include an additional structure that enables smooth current flow in a transition region and / or a ring region of the device, where the current concentrates locally during turn-on / turn-off operations of the device due to insufficient current paths compared to the cell region of the device, thereby improving reverse recovery characteristics and preventing device destruction.

The invention relates to a reverse conducting IGBT device and a preparation method thereof, electronic equipment and a vehicle, and the reverse conducting IGBT device is characterized in that a transition region is arranged between an IGBT region and a diode region of the reverse conducting IGBT device, the front surface structure of the transition region is consistent with the front surface structure of the diode region, and the back surface structure of the transition region is consistent with the back surface structure of the IGBT region. In the working mode of the diode, the anode emission efficiency is reduced, and the effect of reducing the reverse recovery current and the reverse recovery loss of the diode is achieved; in the IGBT working mode, more paths are provided for hole extraction, the turn-off speed of the IGBT is increased, and the turn-off loss of the device is reduced; meanwhile, the performance of the diode region and the IGBT region is improved, and the stability and reliability of the device are improved.

The invention provides a metal oxide semiconductor (MOS) type device integrated with an SBD and a MCD. The MOS type device integrated with the SBD and the MCD structurally comprises an epitaxial layer, a substrate and a drain electrode functional region from top to bottom in sequence, the epitaxial layer sequentially comprises an N + injection region, a body region, a current expansion layer and a drift layer from top to bottom; the source electrode trench comprises a source electrode oxide layer and a source electrode functional region; the gate trench comprises a gate oxide layer and a gate functional region; the device also comprises a P + injection region. According to the MOS type device integrating the SBD and the MCD, the SBD and the MCD are integrated into the device, the size and the cost of the device are reduced, meanwhile, the reverse recovery time can be shortened, bipolar degradation can be effectively restrained, high pressure bearing capacity is reserved, the starting voltage of the device is reduced, and great progress is made in the aspects of improving breakdown voltage and enhancing reverse performance.

A control circuit and method for reducing reverse recovery charge in a switching converter. The control circuit is used for reducing reverse recovery charge in a switching type converter, and comprises a first control signal used for switching a first transistor; a second control signal to switch the second transistor; and an auxiliary control signal to switch the auxiliary transistor; the first end and the second end of the first transistor are coupled to the first end and the second end of the auxiliary transistor in parallel. The first transistor and the second transistor are jointly coupled to a switching node for periodically switching the inductor to convert an input voltage into an output voltage. And delay time exists between the time point when the auxiliary control signal is prohibited and the time point when the first control signal is prohibited. After the second control signal is enabled, the auxiliary control signal is prohibited.

This invention discloses a silicon carbide MOSFET with integrated channel diode, comprising, from bottom to top, a drain metal layer, a SiC-N substrate, a SiC-N epitaxial region, and a SiC-N current spreading layer. Source trenches (SiC-P+ regions) are respectively located on opposite sides of the N-type current spreading layer, and a source trench is located above each SiC-P+ region. A SiC-P pillar region is located at the center of the N-type current spreading layer, and a gate trench is located above the SiC-P pillar region. This invention also discloses a method for fabricating the silicon carbide MOSFET with integrated channel diode. This invention solves the problems of excessively high reverse turn-on voltage, poor reverse recovery characteristics, short short-circuit withstand time, and high peak short-circuit current in traditional silicon carbide MOSFET structures.

A control circuit for reducing reverse recovery charge in a switching converter includes a first control signal configured to switch a first transistor, a second control signal configured to switch a second transistor, and an auxiliary control signal configured to switch an auxiliary transistor. A first terminal and a second terminal of the first transistor are coupled in parallel to a first terminal and a second terminal of the auxiliary transistor. The first transistor and the second transistor are coupled to a switching node, configured to periodically switch an inductor to convert an input voltage into an output voltage. A delay time exists between the time when the auxiliary control signal is deactivated and the time when the first control signal is deactivated. The auxiliary control signal is deactivated after the second control signal is activated.

The invention provides a driving circuit and a driving method thereof. The driving circuit comprises an upper bridge transistor, a first lower bridge transistor, a second lower bridge transistor and a control circuit. The upper bridge transistor is coupled between an input voltage and a switching node. The first lower bridge transistor is coupled between the switching node and a ground terminal. The second lower bridge transistor is coupled between the switching node and a ground terminal. The control circuit periodically and individually turns on the upper bridge transistor and the first lower bridge transistor. After the first lower bridge transistor is turned off, the control circuit continuously turns on the second lower bridge transistor until the upper bridge transistor is turned on so as to eliminate reverse recovery charges of the first lower bridge transistor.