46 results about "Reverse recovery" patented technology

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

This invention relates to the field of power system and energy management technology, and in particular to a collaborative power supply system for energy storage batteries and distributed power sources in microgrids. The invention integrates a reverse recovery charge dynamic clamping module into the gate drive circuit of an IGBT module. The reverse recovery charge dynamic clamping module includes: a di / dt sensing unit, a pulse generation unit, a negative voltage injection unit, and a gate clamping execution unit. The di / dt sensing unit collects the rate of change of current flowing through the emitter of the IGBT module in real time, and triggers the pulse generation unit when the rate of change of current exceeds a set threshold. The pulse generation unit generates a delayed control pulse to control the negative voltage injection unit to switch the output voltage to a target voltage value and maintain it for a specified time. The gate clamping execution unit locks the gate potential of the IGBT module based on the target voltage value. This invention ensures that the system maintains low electromagnetic interference, high energy efficiency conversion, and long-term operational reliability during millisecond-level seamless switching.

This invention discloses an IGBT parallel module having at least two IGBTs connected in parallel, each IGBT configured with a paired FRD; the two parallel IGBTs are designated as first and second IGBTs, and their corresponding paired FRDs are designated as first and second FRDs, respectively. A bridging FRD is also configured between the first and second FRDs; a portion of the anode pins of the bridging FRD is connected to the anode pins of the first FRD via bonding wires, and another portion of the anode pins of the bridging FRD is connected to the anode pins of the second FRD via bonding wires; when current imbalance occurs between the first and second FRDs, the bridging FRD reduces the rated current of the first and second FRDs and performs current buffering, thereby reducing the current density of each FRD; the pin connection structure of the anode of the bridging FRD makes the stray inductance of the bridging FRD greater than that of either the first or second FRD, thereby improving the softness of the reverse recovery of the first and second FRDs. This invention can prevent failure defects caused by current concentration.

This invention discloses a silicon carbide MOSFET with integrated channel diode, comprising, from bottom to top, a drain metal layer, a SiC-N substrate, a SiC-N epitaxial region, and a SiC-N current spreading layer. Source trenches (SiC-P+ regions) are respectively located on opposite sides of the N-type current spreading layer, and a source trench is located above each SiC-P+ region. A SiC-P pillar region is located at the center of the N-type current spreading layer, and a gate trench is located above the SiC-P pillar region. This invention also discloses a method for fabricating the silicon carbide MOSFET with integrated channel diode. This invention solves the problems of excessively high reverse turn-on voltage, poor reverse recovery characteristics, short short-circuit withstand time, and high peak short-circuit current in traditional silicon carbide MOSFET structures.

The application discloses a kind of selected area epitaxy GaN-on-Si HEMT direct drive single-chip integration method, belong to semiconductor device technical field.The specific inclusion includes: selecting silicon substrate and dividing GaN device area and silicon MOSFET device area;Etching recess window in GaN device area, utilize selected area epitaxy technology and grow GaN HEMT epitaxial structure in recess window;Subsequently, silicon MOSFET device and GaN MIS-HEMT device are prepared in corresponding area respectively;Finally, the drain electrode of silicon MOSFET device and the source electrode of GaN MIS-HEMT device are connected by on-chip metal interconnection process.The application realizes normally open type GaN MIS-HEMT and normally off type silicon MOSFET monolithic cascade integration, shortens the device spacing to micron level, greatly reduces parasitic inductance and capacitance, effectively suppresses switch oscillation and overshoot, reduces switch loss, and the gate of GaN MIS-HEMT device is independently extracted to realize direct drive, avoiding reverse recovery charge loss;The method of the application does not need to be bonded, and the process compatibility is good, which significantly improves the high-frequency characteristics, reliability and integration of high-performance power electronic devices.

The application discloses a thyristor control unit test system and method, and belongs to the field of power system testing. The method comprises the following steps: deciding test execution parameters of a debugging instrument based on acquired parameter information of a thyristor control unit; generating analog quantity input for thyristor control unit test through a program-controlled source based on the test execution parameters of the debugging instrument; and performing thyristor control unit test through the debugging instrument and a power load plug-in based on the analog quantity input; wherein the thyristor control unit test comprises forward normal trigger characteristic test and on-state protection and reverse recovery characteristic test; and when the thyristor control unit test is performed, test data of the thyristor control unit collected by the debugging instrument is used to generate a thyristor control unit test result. The application can realize automatic test of the thyristor control unit, and the test is efficient and convenient, and can be applied to in-plant single-plug production batch test.

This disclosure describes an electronic device (100) comprising: an NPN bipolar transistor (Q1) having a p-type base region (B1) (114, 118), an n-type emitter region (E1) (116), and an n-type collector region (C1) (110, 112) in an isolation trench region (103) of an n-type semiconductor layer (106); and a PNP bipolar transistor (Q2) having a p-type base region (B1) ... The n-type base (B2), the p-type emitter (E2) formed by a portion of the p-type base region (B1) (114, 118) of the NPN bipolar transistor (QI), and the p-type collector (C2) formed by the p-type second collector region (120, 122) in the isolation trench region (103) of the semiconductor layer (106) and spaced apart from the p-type base region (B1) (114, 118) and the n-type collector region (C1) (110, 112) of the NPN bipolar transistor (QI).

This invention, entitled "A High-Voltage, Low-Damping Oscillating Soft Recovery Diode and Its Manufacturing Method," uses an N-region as a substrate and includes an outer P+ ring at the anode, an anode P+ block, a P- buffer layer, an outer N-buffer layer at the cathode, an N-buffer layer block ring, an outer N+ ring at the cathode, an N+ region at the cathode, and a cathode P+ block. The N-region has N-buffer layer blocks and N-buffer layer rings uniformly disposed on the cathode K-side. High-density outer N+ rings, cathode N+ regions, and cathode P+ blocks are alternately disposed on the N-buffer layer ring, N-buffer layer blocks, and N-region. The N+ regions overlap and surround the N-buffer layer, and the N-buffer layer blocks surround the cathode P+ blocks. The cathode P+ blocks and cathode N+ regions are isolated by the N-buffer layer. A P-buffer layer is disposed between the N-region and the anode P+ block. The high-voltage diode produced by this invention exhibits higher reverse blocking voltage, ultra-soft reverse recovery characteristics, and lower reverse recovery damping oscillation. The outer N-buffer layer ring at the cathode improves resistance to dynamic avalanche and provides higher reliability.

The application provides a super-junction MOSFET and a manufacturing method thereof, which comprises a substrate, a buffer zone, a first conductive type column, a second conductive type column, a body region, a source region, a body contact region, a gate structure, a source and a drain, wherein the buffer zone is stacked above the substrate; the first conductive type column and the second conductive type column are juxtaposed and adjacent to the upper surface of the buffer zone, and at least one regulation layer is arranged in the second conductive type column, which comprises a second conductive type doped layer and a first conductive type doped region in the second conductive type doped layer; the body region is stacked on the second conductive type column; the source region and the body contact region are adjacent and both located on the upper surface layer of the body region; the gate structure is located on the upper surface of the first conductive type column; the source covers the upper surface of the device, and the drain covers the bottom surface of the substrate. By arranging at least one regulation layer in the second conductive type column, the reverse recovery softness factor of the device is improved, and the sudden change of the output capacitance of the device is relieved.

The embodiment of the application relates to the technical field of semiconductor technology, and discloses a fast recovery diode and a power semiconductor device, the fast recovery diode comprising: a cathode electrode configured as a cathode lead-out end of the fast recovery diode, used for realizing electrical connection of an external circuit; a cathode-side semiconductor layer comprising a composite structure layer and an N-type semiconductor layer which are sequentially stacked in a direction away from the cathode electrode, the composite structure layer comprising P+ type semiconductor islands and an N+ type semiconductor layer; a plurality of P+ type semiconductor islands are spacedly embedded in the N+ type semiconductor layer, used for optimizing reverse recovery characteristics of the device; an anode-side PN junction structure located on a side of the cathode-side semiconductor layer away from the cathode electrode; and an anode structure located on a side of the anode-side PN junction structure away from the cathode-side semiconductor layer; the fast recovery diode provided by the application avoids the problem that the FRD device is invalid due to a step of reverse recovery current in the FRD reverse recovery process.

The application relates to a semiconductor device structure and a preparation method thereof, which comprises the following steps: a substrate structure; an epitaxial structure of a first conductive type on the front surface of the substrate structure; a groove structure comprising a first groove and a second groove; a first ion implantation region of a second conductive type in the epitaxial structure and below the bottom of the first groove; a second ion implantation region of the second conductive type in the epitaxial structure and below the bottom of the second groove; an ohmic contact layer on the bottom of the first groove; and a first electrode in the first groove, in the second groove and on the exposed surface of the epitaxial structure away from the substrate structure. The semiconductor device structure of the application adopts a groove type structure, solves the problem of shallow ion implantation depth of the second conductive type in the epitaxial structure, increases the junction depth of a PN junction, improves the shielding capacity of the PN junction to the electric field of a Schottky contact surface during reverse blocking, and improves the reverse recovery speed.

The present disclosure discloses a hysteresis circuit, an emergency lighting circuit, and a lighting device. The hysteresis circuit includes a voltage detection module, an isolation coupling module, and a voltage adjusting module. By detecting the sampling voltage associated with the input voltage, in response to determining that the sampling voltage is detected to decrease to the trigger action voltage point, the corresponding level of the output signal flips until it is detected that the sampling voltage rises to the reverse recovery voltage point, and the corresponding level of the output signal is controlled to flip again.

The application discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, which comprises a first region, a well region and a second region in sequence away from a first surface; the first and second regions are arranged to be of a first conductive type, and the well region is arranged to be of a second conductive type; the first surface is provided with a gate trench and a source trench located on at least one side of the gate trench; the semiconductor body further comprises a third region and a fourth region of the second conductive type, the third region is located on a side of the well region away from the first surface and is embedded in the region of the first conductive type; the fourth region extends from the first surface to the second surface to contact the third region; a gate is located in the gate trench; a source contact structure is located in the source trench; and a source is located on the first surface and contacts the first region, the fourth region and the source contact structure. The reverse recovery time of the device is reduced, and the bipolar degradation effect of the device is improved.

A self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method, namely, using hot-wall chemical vapor deposition technology, in n + n-type 4H-SiC substrates are grown sequentially ‑ Type 4H-SiC drift region, p + A p-type 4H-SiC shielding layer and an n-type 4H-SiC carrier extension layer 1 are constructed; an n-type Si carrier extension layer 2 is grown using low-pressure chemical vapor deposition to construct a Si / 4H-SiC heterojunction; and a p-type Si bulk region and an n-type Si carrier extension layer 2 are formed using ion implantation. + Type Si source layer and n ‑ The device employs a Si channel layer; edge trenches are etched, and then a planar main gate and two auxiliary gates are fabricated using low-pressure chemical vapor deposition (LPCVD); electrodes are then deposited. In this invention, an accumulation layer channel is formed at the bottom of the main gate oxide layer, and an inversion layer channel is formed inside the auxiliary gate oxide layer, allowing electrons to transport in parallel. The auxiliary gate voltage regulates the Si / 4H-SiC heterojunction barrier to achieve tunneling, reducing specific on-resistance. During reverse recovery, this heterojunction isolates the transport paths of tail-state electrons and holes in the drift region, preventing recombination, reducing reverse recovery loss, and improving static and dynamic performance.

To suppress the electromagnetic radiation noise while suppressing the increase in loss at the time of switching. An electric circuit in which a first switching element (3a) and a first diode element (4a) are connected in antiparallel to form an upper arm, a second switching element (3b) and a second diode element (4b) are connected in antiparallel to form a lower arm, and the upper arm and the lower arm are connected in series, wherein a wiring (F1) connecting the upper arm and the lower arm is arranged in proximity to a gate wiring (F2) of the lower arm in parallel, and the direction of current flowing through the gate wiring of the lower arm is the same as the direction of reverse recovery current flowing from the first diode element of the upper arm to the lower arm.

The present case relates to an AC-DC power conversion system with zero voltage switching. The circuit technique of the present case utilizes an active soft switching unit to substantially reduce switching losses in the AC-DC power conversion system caused by the turn-on characteristics of the main switch and the reverse recovery characteristics of the rectifier. The active soft switching unit includes a series inductor, a series capacitor, a main switch, a rectifier switch, and an auxiliary switch. The series inductor connected between the main switch and the rectifier switch reduces the associated losses of the reverse recovery and further controls the current slew rate of the body diode of the rectifier switch during its turn-off period. The main switch, the rectifier switch, and the auxiliary switch all operate with ZVS.

The application relates to the technical field of semiconductors, in particular to a super-junction fast recovery diode and a manufacturing method thereof, which comprises a substrate, a buffer layer located on the substrate, a drift layer located on the buffer layer, a P-type region located on the drift layer, and a P column located in the drift layer and on the buffer layer, wherein the bottom of the P column is in contact with the upper edge of the buffer layer, and the top of the P column is not in contact with the lower edge of the P-type region. Through the structural arrangement of the super-junction fast recovery diode, the reverse withstand voltage of the device is greatly improved, the on-state voltage drop is reduced, the reverse recovery performance is enhanced, and the reverse recovery loss is reduced.

A semiconductor device and inverter circuit, belonging to the semiconductor field, includes a MOS power device and a freewheeling diode connected in anti-parallel to the MOS power device. The MOS power device is a silicon-based MOS power device and has a MOS transistor and a parasitic PN junction body diode. The MOS transistor and the parasitic PN junction body diode are integrally formed in an anti-parallel manner. The MOS power device includes a substrate, a drift layer, a well layer, a contact region, a source region, a gate insulating layer, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. By configuring the overlap area of ​​the source electrode and the contact region in the MOS power device, the current carrying capacity of the parasitic PN junction body diode is less than or equal to half of the current carrying capacity of the MOS transistor, and the current carrying capacity of the freewheeling diode is greater than or equal to the current carrying capacity of the parasitic PN junction body diode. The total current carrying capacity of the freewheeling diode and the parasitic PN junction body diode is less than or equal to the current carrying capacity of the MOS power device, thus improving the reverse recovery characteristics.

This invention provides a semiconductor device, its manufacturing method, and layout structure. A shielded gate trench transistor and a trench Schottky diode are formed in a semiconductor substrate. The trench Schottky diode's blocking effect on minority carriers reduces the overall reverse bias extraction of minority carriers in the semiconductor device, thereby reducing parameters characterizing reverse recovery performance, such as reverse charge (Qrr) and reverse current (Irr). Simultaneously, self-aligned ion implantation can be used to form the well and source regions of the shielded gate trench transistor, avoiding increased manufacturing costs.

This invention relates to a method and system for identifying reverse recovery conduction paths and predicting dynamic characteristics of SiC MOSFETs, belonging to the field of power semiconductor device testing and reliability analysis. The method includes: Step 1: Constructing a dual-pulse test circuit and acquiring waveform data; Step 2: Preprocessing the data; Step 3: Extracting feature parameters and constructing feature vectors; Step 4: Outputting the conduction path type and device degradation state; Step 5: Based on the conduction path type, combined with the total current decomposition relationship and the dynamic response characteristics of the device under different test conditions, establishing a conduction path decomposition model, and calculating the current proportions of the MOS channel conduction path, body diode conduction path, and Schottky diode conduction path; Step 6: Predicting reverse recovery parameters; Step 7: Assessing device status, predicting remaining lifetime, and assessing failure risk. This invention automates the processing of dual-pulse test data and, for the first time, achieves quantitative identification of conduction paths.

This invention discloses a method, device, and storage medium for predicting the remaining lifetime of high-power thyristors, belonging to the technical field of high-power thyristor remaining lifetime prediction. It addresses the problem of how to more comprehensively predict the health status of thyristors. The method involves collecting degradation test data of the thyristor's on-state voltage drop and reverse recovery charge; calculating an acceleration factor based on the test data; establishing a binary degradation trajectory model of the thyristor based on the degradation data of the thyristor's on-state voltage drop and reverse recovery charge; estimating the unknown parameters of the model using the Markov chain Monte Carlo method; and evaluating the remaining lifetime of the thyristor using the lifetime prediction model. This invention uses two-dimensional data of the thyristor's on-state voltage drop and reverse recovery charge to evaluate the thyristor's lifetime and models their correlation. The resulting thyristor lifetime prediction results can comprehensively reflect the health status of the thyristor, overcoming the difficulty of accurately predicting the thyristor's lifetime due to a small number of failure samples, and improving the accuracy of thyristor lifetime prediction.

This invention discloses a dual-gate trench MOSFET with a shielded gate electrode in a stepped trench. Each cell includes a first MOSFET with a single-step gate trench, or integrates a first MOSFET and a super-barrier rectifier, or a first MOSFET and a second MOSFET. The single-step gate trench contains a shielded gate electrode. The top trench width of the single-step gate trench is smaller than the bottom trench width, achieving a reduction in the device cell size. The improved structure of this invention effectively reduces the specific on-resistance and reverse recovery time of the device.

This invention provides a composite semiconductor device with low forward voltage drop and a method for driving the same, which can reduce losses during reverse recovery switching. [Solution] A composite semiconductor device comprising: a first diode in which the impurity concentration in the second anode region is higher than that in the first anode region of the first diode; a crystal defect density in the crystal defect region provided within the drift region of the second diode is lower than that in the crystal defect region provided within the drift region of the first diode; and a switch provided to operate the first diode and the second diode at different timings.

This invention discloses a power converter and its control method. The power converter includes a PFC circuit, an auxiliary switching circuit, and a control device. The PFC circuit is connected to the auxiliary switching circuit, and the control device is connected to both the PFC circuit and the auxiliary switching circuit. The control device is used to generate a drive signal for the auxiliary switching transistor in the auxiliary switching circuit based on the drive signal of the switching transistor in the PFC circuit, so that the output voltage excites the auxiliary inductor in the auxiliary switching circuit. The auxiliary switching circuit is used to control the auxiliary switching transistor to turn off for a period of time after it is turned on, so that the current through the freewheeling transistor and the excitation transistor in the PFC circuit is less than or equal to zero before the magnetizing transistor in the PFC circuit is turned on. This invention enables soft switching of the high-frequency power transistor in the PFC circuit and reduces reverse recovery through the auxiliary switching circuit, achieving zero-voltage turn-on of the high-frequency excitation switching transistor, which greatly reduces the losses caused by reverse recovery and hard turn-on in existing solutions.

A kind of trench MOSFET with high-speed switch. It relates to the field of semiconductor technology.The utility model trench MOSFET by adding source trench and supporting structure between adjacent gate trenches, build new current path.In reverse freewheeling, the current of traditional trench MOSFET needs to be all flowed through body diode, and in the structure, the source oxide layer in source trench is thinner, and the source and source region are short-circuited to form built-in MOS channel.When the device is in reverse working state, part of freewheeling current can flow through this built-in MOS channel, no longer completely rely on body diode, if the thickness of source oxide layer is appropriately reduced, even the whole freewheeling current can flow through MOS channel, completely not rely on body diode, so as to change the current flow path and distribution situation.This optimization of current channel can effectively reduce the storage and recombination time of carriers, and then improve the reverse recovery performance.

This invention discloses a split-gate trench metal-oxide-semiconductor field-effect transistor and its fabrication method, belonging to the field of semiconductor technology. The transistor includes: a drain metal, a drift region, a current spread region, a body region, a trench, a split-gate structure, a gate metal, a source region, and a source metal. The trench has a sawtooth or wavy structure in the horizontal direction, sequentially penetrating the body region, the current spread region, and extending into the drift region. The split-gate structure includes a first source polysilicon, a second source polysilicon, and a gate polysilicon. Trench openings in the source region are etched to the second source polysilicon, electrically connecting the source metal to the second source polysilicon. This invention, through its sawtooth trench design, increases the process window of the source contact hole, reduces the requirements for photolithography precision, lowers the on-state voltage drop, increases the contact area between the contact hole and the second source polysilicon, and shortens the reverse recovery time.