383 results about "Reverse recovery" patented technology

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

To provide a semiconductor device having a transistor part and a diode part, in which a reverse recovery loss is reduced.SOLUTION: A semiconductor device includes: an interlayer insulating film 38 provided over a semiconductor substrate 10; an emitter electrode 52 being a front surface electrode provided over the semiconductor substrate; contact parts where the front surface electrode and mesa parts 61 to 64 are connected in contact holes 54 of the interlayer insulating film; and a lifetime adjustment region 206 provided on a front surface side of the semiconductor substrate. The contact parts have a first contact part 77 provided in a transistor part, and a second contact part 87 provided in a diode part. The first contact part is disposed over the second contact part.SELECTED DRAWING: Figure 3A

The invention belongs to the technical field of power semiconductor device life prediction, and particularly relates to a SiC MOSFET life prediction method based on gate oxide layer aging. The method comprises the following steps: firstly, acquiring a real threshold voltage sequence under different working conditions through a SiC MOSFET accelerated aging test, and preprocessing the real threshold voltage sequence; then, a life prediction model is constructed based on the conditional generative adversarial network, and the life prediction model comprises a generator, a common discriminator, a conditional discriminator, a coding network and a reverse recovery network; enabling the working condition as a condition label and the preprocessed real threshold voltage sequence to sequentially pass through a coding network and a reverse recovery network to obtain a real threshold voltage sequence embedded with the working condition; using the working condition as a condition label and a randomly generated Gaussian noise sequence to pass through a generator to obtain an analog threshold voltage sequence embedded with the working condition; inputting the real threshold voltage sequence and the simulation threshold voltage sequence with the embedded working conditions into a common discriminator and a condition discriminator at the same time for discrimination; and finally, training the life prediction model, and generating a threshold voltage sequence under an expected working condition by using a trained generator. According to the method, the service life of the SiC MOSFET under different working conditions can be predicted offline, and the method is more applicable.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

Operating a double-sided double-base bipolar junction transistor. At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly, into an upper collector-emitter of a double-sided double-base bipolar junction transistor (DSDB-BJT), through the DSDB-BJT, out through a lower collector-emitter of the DSDB-BJT, and then through a lower terminal of the switch assembly; and then ceasing conduction of the forward load current. The ceasing conduction of the forward load current may be by: coupling a lower base of the DSDB-BJT to the lower terminal; and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce reverse recovery current through the lower base.

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

The utility model provides a silicon carbide VDMOS with high drain voltage impact resistance. A drift layer is connected to a silicon carbide substrate; a current sharing layer and a plurality of masking layers are arranged in the drift layer, the masking layers are located above the current sharing layer, and the multiple masking layers are uniformly arranged at intervals; the N-type region is connected to the drift layer; the P-type well region is connected to the N-type region, the P-type well region is connected to the drift layer, and an N-type source region is arranged in the P-type well region; the insulating dielectric layer is connected with the drift layer, and is connected to the P-type well region and the N-type source region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the N-type region, the P-type well region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; the drain voltage impact resistance of the device is improved, the gate-source capacitance of the device is reduced, the switching speed of the device is improved, the switching loss of the device is reduced, the body diode conduction loss of the device can be reduced, and the reverse recovery speed of the device is improved.

The invention relates to a fast recovery diode and a manufacturing method thereof. The fast recovery diode comprises a substrate; the first epitaxial layer is located on one side of the substrate, at least one floating region is formed in the first epitaxial layer, the doping type of the first epitaxial layer is the same as that of the substrate, and the doping type of the floating region is different from that of the first epitaxial layer; the active layer is located on the side, away from the substrate, of the first epitaxial layer, the active layer comprises an anode region and a terminal region, the anode region and the terminal region are both in contact with the first epitaxial layer, the terminal region is arranged around the anode region, and the doping types of the anode region and the floating region are the same; the isolation layer is located on the side, away from the substrate, of the active layer, the isolation layer comprises a contact hole, and the contact hole exposes part of the anode region; the first metal layer is located on the side, away from the substrate, of the isolation layer, and the first metal layer makes contact with the anode region through the contact hole; therefore, the reverse recovery speed of the fast recovery diode with the positive temperature coefficient is improved.

The invention relates to a rapid estimation method and device for MMC loss in an electromagnetic transient model, and a medium. The method comprises the following steps: S1, constructing a Thevenin equivalent model of an MMC; s2, on the basis of an MMC Thevenin equivalent model, discretizing a sub-module capacitor based on a numerical integration method to establish an on-state loss model of the sub-module; s3, correcting to obtain the turn-on loss and turn-off loss of the IGBT and the reverse recovery loss of the diode; s4, in one simulation step, on-state loss is obtained through calculation based on an on-state loss model, the total switching frequency is obtained through calculation according to port data of the Thevenin equivalent model, and switching loss is obtained through combination of on-state loss and off-state loss of an IGBT and reverse recovery loss and switching frequency of a diode; and S5, taking the sum of the on-state loss and the switching loss as total loss. Compared with the prior art, the method has the advantages that real-time updating in the simulation step can be realized, the calculation complexity is controllable, and the overhead is remarkably reduced while the engineering precision is ensured.

The invention discloses a bidirectional power electronic switch, a hybrid DC circuit breaker and a control method. The bidirectional power electronic switch comprises a diode bridge module, a buffer circuit, a voltage limiting circuit and an impedance adjusting circuit. The impedance adjusting circuit is connected in parallel with two ends of the diode bridge module; the buffer circuit is connected in parallel with a breaking electronic switch in the diode bridge module; the voltage limiting circuit is connected in parallel with two ends of the breaking electronic switch; the diode bridge module controls the breaking electronic switch to switch current according to a breaking instruction of the power system; when the breaking electronic switch is locked, the buffer circuit suppresses the voltage and current changes of the breaking electronic switch in the switching process, the voltage limiting circuit limits the overvoltage level of the breaking electronic switch, and the impedance adjusting circuit reduces the oscillation frequency. The impedance adjusting circuit reduces the oscillation frequency, reduces the requirement for the reverse recovery speed of the diode, reduces the stress of the diode bridge type module, and enables a conventional common diode to be not liable to be damaged.

The invention discloses an FCE diode and a manufacturing method thereof. The cathode metal is provided with a trench isolation region, cathode N + regions and cathode P + regions, the cathode N + regions and the cathode P + regions are transversely and alternately arranged, the trench isolation region isolates the cathode N + regions from the cathode P + regions, and the thickness of the trench isolation region exceeds 2 microns of the cathode N + regions and the cathode P + regions And then a plasma storage region, a field stop region, a base region, an anode P region and anode metal are sequentially arranged. The thickened trench isolation region is indispensable for improving the current density uniformity near the cathode, and can weaken low-frequency oscillation and reduce conduction voltage drop; the thickened plasma storage region can weaken low-frequency oscillation, improve the current density uniformity near the anode and reduce reverse recovery energy under severe or extreme conditions; the two measures can also ensure that the base region is greatly thinned on the premise of enlarging the safe working region, so that the loss is reduced. By optimizing and compromising the structural parameters of each area, the FCE diode can achieve the beneficial effects of self-clamping, low loss, uniform current density, no high-frequency oscillation, slight low-frequency oscillation and wide safe working area.

The invention belongs to the field of semiconductor devices, provides a gallium nitride high-electron-mobility transistor integrated with a Schottky diode and a preparation method of the gallium nitride high-electron-mobility transistor, and aims to solve the problem that a conventional gallium nitride high-electron-mobility transistor (GaN HEMT) lacks a body diode. According to the invention, monolithic integration of the SBD and the GaN HEMT is realized through structural design, a low-impedance path is provided for reverse current, and the integration mode not only retains the original high performance characteristic of a GaN device, but also additionally endows the GaN device with reverse conduction and reverse recovery capabilities; moreover, through the structural design, the SBD can be synchronously completed on the basis of the existing GaN HEMT process, a special process or new equipment is not needed, and the cost is effectively controlled while the performance improvement is ensured; compared with an external interconnection diode scheme, parasitic inductance caused by lead bonding is eliminated, the voltage overshoot and ringing phenomena in the switching process are remarkably reduced, high-frequency switching application is facilitated, and switching loss can be greatly reduced.

The utility model relates to the technical field of MOS semiconductors, and discloses a trench gate super junction VDMOS device, comprising a VDMOS device composed of a plurality of VDMOS cells, the VDMOS device comprising a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and a heavily doped N well layer, and the N well layer is isolated from the diffusion layer through the P well layer; wherein the P-well layer comprises a lightly doped P-well layer I, a heavily doped P-well layer I and a heavily doped P-well layer II; the diffusion layer forms a first lightly doped diffusion layer, a second lightly doped diffusion layer and a third lightly doped diffusion layer through ion implantation of phosphorus elements with different concentrations. According to the utility model, the heavily-doped P-well layer I is formed by ion implantation between adjacent VDMOS cells, and the lightly-doped layer has a lower charge conduction effect, so that when the switching tube is conducted, due to the constraint of the lightly-doped layer and the heavily-doped P-well layer I, the injection of unbalanced carriers is reduced, and reverse recovery charges are reduced.

A process for monitoring a degradation state of an electrical interconnection (15) in a power module assembly (100), comprises capturing a detection signal that is sensitive to a reverse recovery current originating from a diode (14) of the power module assembly. The reverse recovery current is triggered by a turning-on switching operation of a switch (11) in a tested half-bridge branch (1) that comprises said diode, switch and interconnection. The invention process may be combined optionally with another monitoring process based on a turning-off switching operation of the switch, for monitoring a degradation state of another electrical interconnection within the same half-bridge branch. Complete interconnection monitoring for said half-bridge branch is thus possible.

The invention relates to the technical field of data processing, in particular to a high-frequency diode conduction loss characteristic test system, which comprises an acquisition module, a first judgment module, a second judgment module, a first determination module, a second determination module, an adjustment module and an output module. According to the method, multiple key data are collected, rapid screening is carried out according to forward voltage and reverse recovery charges, then, hidden defects of abnormal dynamic relevance of parameters are analyzed and identified by introducing shell temperature, and finally, a high-loss diode is obtained; the trend abnormity is identified by using the space-time distribution characteristics of the high-loss diode, and the loss reason is accurately detected through the voidage fluctuation mode; and meanwhile, based on a self-adaptive adjustment mechanism fed back by the test accuracy, a test report is finally output, so that the problems of low identification accuracy of the high-loss diode and low detection accuracy of loss reasons caused by excessive dependence on static parameters and incapability of adapting to complex and changeable working conditions are effectively solved.

The invention relates to the technical field of power semiconductor devices, and discloses a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction control diode and a method. A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source electrode contact region and the P-type well region and goes deep into the trench MOSFET region of the first N-type epitaxial layer. According to the invention, the junction-controlled freewheeling diode is integrated at the side of the shield grid, so that the conduction voltage drop of the diode during freewheeling is reduced, and the reverse recovery time is greatly shortened. A high-turn-on-voltage diode is additionally arranged at the bottom of the shielding grid, the turn-on voltage is bipolar conduction, self-turn-on conduction is achieved under extreme working conditions such as surge, and the reliability of the device is improved. And the shielding grid electrode can form an electric field shielding effect during reverse voltage withstanding, so that electric field clamping at the bottom of the true grid electrode is realized.

The invention discloses a hybrid self-switching bidirectional wireless switched reluctance motor driving system provided and realized by the invention. An independent demagnetization loop is arranged on the motor side, rapid demagnetization is allowed, and energy recovery is achieved. The system wirelessly drives a multi-phase SRM through a single power transfer channel using a single resonant frequency to reduce coupling between multiple power channels. When the WPT system is in forward power, the LCC-S compensation network is adopted to drive the motor load, and the advantage of constant voltage gain when the load changes is achieved; the LCC-LCC / S hybrid self-switching compensation network is adopted to realize charging of a battery load, and has a constant voltage / constant current characteristic; and when the WPT system has negative power, the LCC-LCC compensation network is adopted to realize reverse recovery of energy, and energy interconnection between the motor and the power grid is realized. In addition, an SR motor does not need to be specially designed, and the system has the remarkable advantages of phase current balance, flexible transmission distance, high integration level, maintenance-free property and the like.

The invention discloses a local platinum doping method for a fast soft recovery diode, and relates to the technical field of semiconductor manufacturing. According to the local platinum doping method for the fast soft recovery diode, hydrogen ions and helium ions are injected to form prefabricated atom vacancy defects, platinum atoms are induced to gather and stay in a prefabricated vacancy defect area, and local platinum atom doping is achieved. The performance advantages of traditional global platinum doping life control and local hydrogen / helium ion life control on the silicon-based fast recovery diode are organically combined, and prefabricated vacancy defects are flexibly formed at different depths through hydrogen ions and helium ions, so that precise local doping of platinum atoms is realized; meanwhile, the fast soft recovery diode has the performance advantages of good reverse recovery characteristic, high softness factor, low reverse recovery voltage change rate, good long-term reliability, low electric leakage, high device junction temperature and the like.

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

This invention relates to the field of power system and energy management technology, and in particular to a collaborative power supply system for energy storage batteries and distributed power sources in microgrids. The invention integrates a reverse recovery charge dynamic clamping module into the gate drive circuit of an IGBT module. The reverse recovery charge dynamic clamping module includes: a di / dt sensing unit, a pulse generation unit, a negative voltage injection unit, and a gate clamping execution unit. The di / dt sensing unit collects the rate of change of current flowing through the emitter of the IGBT module in real time, and triggers the pulse generation unit when the rate of change of current exceeds a set threshold. The pulse generation unit generates a delayed control pulse to control the negative voltage injection unit to switch the output voltage to a target voltage value and maintain it for a specified time. The gate clamping execution unit locks the gate potential of the IGBT module based on the target voltage value. This invention ensures that the system maintains low electromagnetic interference, high energy efficiency conversion, and long-term operational reliability during millisecond-level seamless switching.

An electric circuit in which a first switching element and a first diode element are connected in antiparallel to form an upper arm and a second semiconductor element and a second diode element are connected in antiparallel to form a lower arm, and the upper arm and the lower arm are connected in series. A gate current path in one of the upper and lower arms and a reverse recovery path in the other one of the upper and lower arms are disposed close enough and extend at least partially in parallel to each other, so as to generate mutual inductance by the reverse recovery current flowing through the reverse recovery path and the gate current flowing through the gate current path.

This invention discloses an IGBT parallel module having at least two IGBTs connected in parallel, each IGBT configured with a paired FRD; the two parallel IGBTs are designated as first and second IGBTs, and their corresponding paired FRDs are designated as first and second FRDs, respectively. A bridging FRD is also configured between the first and second FRDs; a portion of the anode pins of the bridging FRD is connected to the anode pins of the first FRD via bonding wires, and another portion of the anode pins of the bridging FRD is connected to the anode pins of the second FRD via bonding wires; when current imbalance occurs between the first and second FRDs, the bridging FRD reduces the rated current of the first and second FRDs and performs current buffering, thereby reducing the current density of each FRD; the pin connection structure of the anode of the bridging FRD makes the stray inductance of the bridging FRD greater than that of either the first or second FRD, thereby improving the softness of the reverse recovery of the first and second FRDs. This invention can prevent failure defects caused by current concentration.

The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a substrate; a drift layer; a base layer; a trench; an oxide layer; a plurality of first trenches are provided in a fast recovery diode region, the first trenches including a first trench portion and a second trench portion, the first trench portion being located on a side of the second trench portion closer to the first main surface, the oxide layer being provided on the inner wall of the second trench portion; polysilicon; the oxide layer on the inner wall of the second trench portion separates the polysilicon in the second trench portion from the base layer, the polysilicon in the first trench portion being in contact with the base layer; a dielectric layer; and an emitter metal layer, the emitter metal layer at least partially passing through the dielectric layer and in contact with the base layer, the emitter metal layer being electrically connected to the polysilicon. Thus, carriers can flow between the polysilicon in the first trench portion and the base layer, further improving dynamic avalanche withstand, reducing reverse recovery current, and shortening reverse recovery time.

The utility model discloses a totem pole PFC circuit, circuit board, controller and air conditioner, including first control bridge arm, follow current bridge arm and first inductor, the first control bridge arm includes first switch tube and second switch tube that connect in series, first switch tube and second switch tube adopt IGBT, the two ends of first switch tube are antiparallel with first diode, and the two ends of second switch tube are antiparallel with second diode. Two ends of the second switch tube are reversely connected in parallel with a second diode; the follow current bridge arm comprises a third diode and a fourth diode which are connected in series, and the connection point of the third diode and the fourth diode is connected to one end of the AC power supply; one end of the first inductor is connected to the other end of the AC power supply, and the other end of the first inductor is connected to a connection point of the first switch tube and the second switch tube; under a preset test condition, reverse recovery characteristic parameters of the first diode and the second diode are smaller than a preset value, and the preset value is determined according to test parameters in the preset test condition; and the reliability of the totem-pole PFC circuit in practical application can be effectively improved.

The invention provides a super junction semiconductor power device which comprises a heavily doped first conductive type substrate, and a first conductive type epitaxial layer is arranged on the heavily doped first conductive type substrate; a groove is formed in the first conductive type epitaxial layer; second conductive type doped monocrystalline silicon is filled in the groove to form a second conductive type columnar epitaxy; first conductive type columnar epitaxy and second conductive type columnar epitaxy which are alternately distributed are formed in the first conductive type epitaxial layer; the doping concentration of the second conductive type columnar epitaxy is greater than that of the first conductive type columnar epitaxy; a plurality of heavily doped first conductive type impurity injection regions extending into the first conductive type columnar epitaxy are distributed on the side walls of the two sides of the second conductive type columnar epitaxy; according to the invention, the soft reverse recovery characteristic can be obtained, the electromagnetic radiation in the reverse recovery process of the device is reduced, and meanwhile, the voltage-resistant stability of the device is improved.

A process for monitoring a degradation state of an electrical interconnection (15) in a power module assembly (100), comprises capturing a detection signal that is sensitive to a reverse recovery cunent originating from a diode (14) of the power module assembly. The reverse recovery current is triggered by a turning-on switching operation of a switch (11) in a tested half-bridge branch (1) that comprises said diode, switch and interconnection. The invention process may be combined optionally with another monitoring process based on a turning-off switching operation of the switch, for monitoring a degradation state of another electrical interconnection within the same half-bridge branch. Complete interconnection monitoring for said half-bridge branch is thus possible.

A method for reducing or eliminating current and voltage transients in a device including: providing the device, wherein the device comprises a transistor with a gate; and controlling the gate, wherein the gate is turned off to a non-zero value in a presence of the positive current flow and wherein the gate is turned on in a presence of the negative current flow; reducing the negative current flow; and reducing or eliminating current and voltage transients in the device.

The present invention relates to a deep trench MOSFET-like Schottky diode and a manufacturing method thereof. The deep trench MOSFET-like Schottky diode includes: a substrate; an epitaxial layer located on the upper surface of the substrate; a plurality of deep trenches located in the epitaxial layer, with source polysilicon and gate polysilicon disposed in the deep trenches; a well region located on the upper surface of the epitaxial layer; a source region located on the upper surface of the well region, characterized in that it further includes: a first base region disposed in the well region between two adjacent deep trenches and having the same conductivity type as the well region; a second base region located below the first base region, the second base region having the same conductivity type as the first base region and a doping concentration lower than that of the first base region; and a metal electrode penetrating through the first base region and the second base region. The present invention can reduce the time and charge required for the reverse recovery of the diode.

The invention discloses a semiconductor device and an electronic apparatus, and the semiconductor device comprises a semiconductor substrate which comprises an insulated gate bipolar transistor region and a fast recovery diode region, and a collector layer is at least partially located in the insulated gate bipolar transistor region; the short circuit region is located in the fast recovery diode region; the rated current of the insulated gate bipolar transistor area is set to be I1, the rated current of the fast recovery diode area is set to be I2, and I1 and I2 meet the relational expression that I2 is smaller than or equal to I1 / 3. Therefore, the rated current of the fast recovery diode region can be small, and when the semiconductor device is used as a power chip in a PFC circuit, the area of the fast recovery diode region can be reduced, so that the whole semiconductor device is more miniaturized, the cost is reduced, the arrangement of the semiconductor device is convenient, the reverse recovery loss can be reduced, and the reliability of the semiconductor device is improved. And the heat dissipation performance can be improved.