571 results about "Reverse recovery" patented technology

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a current sharing layer, a body region, a P-type well region and an N-type source region are formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; a barrier layer is formed again, and etching and deposition are carried out to form a gate dielectric layer; the preparation method comprises the following steps: forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, removing the barrier layer, and completing the preparation. The gate reliability of the device can be effectively improved, and the follow current loss and reverse recovery speed of a body diode can be effectively improved.

The invention relates to an enhanced gallium nitride high-mobility transistor and a preparation method thereof. The transistor sequentially comprises a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer from bottom to top, the source electrode and the drain electrode are respectively in ohmic contact with the two-dimensional electron gas, and the grid electrode and the p-GaN layer are in Schottky contact, so that the two-dimensional electron gas below the grid electrode is exhausted to realize normal closing; an electrode is arranged in a region between the grid electrode and the drain electrode, a thin-layer medium is arranged below the electrode, and the thin-layer medium and the electrode form an equivalent MIS grid structure; and the electrode is electrically connected with the source electrode. The switching time of the device is determined by the switching speed of the p-GaN HEMT composed of S-G1-D. Compared with a traditional Si MOS cascade structure, the device has the advantages of being fast in switching and free of reverse recovery charges. And meanwhile, the withstand voltage of the device is determined by a depletion mode MIS GaN HEMT consisting of S-G2-D, and the p-GaN grid does not bear high voltage, so that the device has the advantage of high reliability.

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

To provide a semiconductor device having a transistor part and a diode part, in which a reverse recovery loss is reduced.SOLUTION: A semiconductor device includes: an interlayer insulating film 38 provided over a semiconductor substrate 10; an emitter electrode 52 being a front surface electrode provided over the semiconductor substrate; contact parts where the front surface electrode and mesa parts 61 to 64 are connected in contact holes 54 of the interlayer insulating film; and a lifetime adjustment region 206 provided on a front surface side of the semiconductor substrate. The contact parts have a first contact part 77 provided in a transistor part, and a second contact part 87 provided in a diode part. The first contact part is disposed over the second contact part.SELECTED DRAWING: Figure 3A

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, a semiconductor body of the semiconductor device is set as a first conductive type, a first surface of the semiconductor body is provided with a gate trench, and a trench gate structure is located in the gate trench. The semiconductor body further comprises a first region of the first conduction type, a well region of the second conduction type and a second region of the second conduction type, and the second region and at least part of the first surface are connected with a source electrode of the semiconductor device to form Schottky contact. The Schottky contact reduces the conduction voltage drop, reverse recovery time and reverse recovery energy consumption of the semiconductor device, enhances the conduction performance and surge current resistance of the body diode, avoids the problem that holes enter a drift layer in the follow current process, reduces the risk of double-click degradation of the device, avoids an external follow current diode, and improves the reliability of the device. Therefore, the circuit design complexity and the system cost are reduced.

The invention belongs to the technical field of power semiconductor device life prediction, and particularly relates to a SiC MOSFET life prediction method based on gate oxide layer aging. The method comprises the following steps: firstly, acquiring a real threshold voltage sequence under different working conditions through a SiC MOSFET accelerated aging test, and preprocessing the real threshold voltage sequence; then, a life prediction model is constructed based on the conditional generative adversarial network, and the life prediction model comprises a generator, a common discriminator, a conditional discriminator, a coding network and a reverse recovery network; enabling the working condition as a condition label and the preprocessed real threshold voltage sequence to sequentially pass through a coding network and a reverse recovery network to obtain a real threshold voltage sequence embedded with the working condition; using the working condition as a condition label and a randomly generated Gaussian noise sequence to pass through a generator to obtain an analog threshold voltage sequence embedded with the working condition; inputting the real threshold voltage sequence and the simulation threshold voltage sequence with the embedded working conditions into a common discriminator and a condition discriminator at the same time for discrimination; and finally, training the life prediction model, and generating a threshold voltage sequence under an expected working condition by using a trained generator. According to the method, the service life of the SiC MOSFET under different working conditions can be predicted offline, and the method is more applicable.

The invention discloses a diffusion capacitance-based reverse recovery model turn-on loss calculation method and system, and the method comprises the steps: extending the junction capacitance range of a SiC MOSFET through combining the diffusion capacitance and a three-capacitor model, and can more accurately describe the reverse recovery characteristic of a medium-voltage SiC MOSFET, and achieve the simulation precision of the model on the actual device behavior. And a solid foundation is provided for subsequent analysis and optimization. By solving the linearized reverse recovery model, the method can obtain voltage and current waveforms in the reverse recovery process of the SiC MOSFET. The waveforms are key data for evaluating the turn-on loss and directly reflect energy conversion and loss conditions of a device in the turn-on and turn-off process, and the method can further calculate the heat loss of the medium-voltage SiC MOSFET in the turn-on process according to the reversely recovered voltage and current waveforms.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

Operating a double-sided double-base bipolar junction transistor. At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly, into an upper collector-emitter of a double-sided double-base bipolar junction transistor (DSDB-BJT), through the DSDB-BJT, out through a lower collector-emitter of the DSDB-BJT, and then through a lower terminal of the switch assembly; and then ceasing conduction of the forward load current. The ceasing conduction of the forward load current may be by: coupling a lower base of the DSDB-BJT to the lower terminal; and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce reverse recovery current through the lower base.

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

The utility model provides a silicon carbide VDMOS with high drain voltage impact resistance. A drift layer is connected to a silicon carbide substrate; a current sharing layer and a plurality of masking layers are arranged in the drift layer, the masking layers are located above the current sharing layer, and the multiple masking layers are uniformly arranged at intervals; the N-type region is connected to the drift layer; the P-type well region is connected to the N-type region, the P-type well region is connected to the drift layer, and an N-type source region is arranged in the P-type well region; the insulating dielectric layer is connected with the drift layer, and is connected to the P-type well region and the N-type source region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the N-type region, the P-type well region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; the drain voltage impact resistance of the device is improved, the gate-source capacitance of the device is reduced, the switching speed of the device is improved, the switching loss of the device is reduced, the body diode conduction loss of the device can be reduced, and the reverse recovery speed of the device is improved.

The invention provides a driving method, a driving circuit of an amplification module and electronic equipment. The method comprises the following steps: when a power tube is conducted, outputting a first conduction current to a grid electrode of the power tube; after the gate-source voltage of the power tube rises to the threshold voltage, the first conduction current is reduced to the second conduction current, so that the reverse recovery current of the body diode corresponding to the power tube is reduced; after the gate-source voltage of the power tube is increased from the threshold voltage to the Miller voltage, the second conduction current is increased to third conduction current until the power tube is completely conducted; and when the power tube is turned off, the grid electrode of the power tube outputs a first turn-off current until the power tube is completely turned off. In the conduction process of the power tube, after the gate source voltage of the power tube rises to the threshold voltage, the first conduction current is reduced to the second conduction current, so that the reverse recovery current of a body diode corresponding to the power tube is reduced, overshoot of the power tube in the conduction process is avoided, and the conduction safety of the power tube is improved.

The invention relates to a fast recovery diode and a manufacturing method thereof. The fast recovery diode comprises a substrate; the first epitaxial layer is located on one side of the substrate, at least one floating region is formed in the first epitaxial layer, the doping type of the first epitaxial layer is the same as that of the substrate, and the doping type of the floating region is different from that of the first epitaxial layer; the active layer is located on the side, away from the substrate, of the first epitaxial layer, the active layer comprises an anode region and a terminal region, the anode region and the terminal region are both in contact with the first epitaxial layer, the terminal region is arranged around the anode region, and the doping types of the anode region and the floating region are the same; the isolation layer is located on the side, away from the substrate, of the active layer, the isolation layer comprises a contact hole, and the contact hole exposes part of the anode region; the first metal layer is located on the side, away from the substrate, of the isolation layer, and the first metal layer makes contact with the anode region through the contact hole; therefore, the reverse recovery speed of the fast recovery diode with the positive temperature coefficient is improved.

The invention discloses an RC-IGBT structure with low reverse recovery loss and a preparation method thereof, and belongs to the technical field of power devices.When the RC-IGBT structure is reversely conducted, electrons injected into an n + short circuit region can directly flow to an n + ohmic contact region in an n-type carrier storage region after sequentially passing through an n field stop layer, an n-drift region and a P well region, so that the electrons can be directly injected into the n + ohmic contact region in the n-type carrier storage region; therefore, the electron density below the anode region of the integrated diode in the RC-IGBT structure is reduced, the hole injection efficiency of the anode region is further reduced, the reverse recovery speed of the integrated diode is improved, reverse recovery charges are reduced, and the preparation process is simple.

The invention discloses a semiconductor device, a preparation method of the semiconductor device, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors. The semiconductor body comprises a first region of a first conduction type, a well region of a second conduction type and a second region of the second conduction type, and the second region and at least part of the first surface are connected with a source electrode of the semiconductor device to form Schottky contact. The semiconductor device also includes a plurality of first structures disposed in a second conductivity type. Schottky contact reduces conduction voltage drop, reverse recovery time and reverse recovery energy consumption of the semiconductor device, the problem that holes enter a drift layer in the follow current process is avoided, the risk of double-click degradation of the device is reduced, and an external follow current diode is avoided. In addition, the plurality of first structures improve the overall reverse characteristic and gate oxide reliability of the device, so that the long-term reliability of the device is ensured.

The invention relates to a rapid estimation method and device for MMC loss in an electromagnetic transient model, and a medium. The method comprises the following steps: S1, constructing a Thevenin equivalent model of an MMC; s2, on the basis of an MMC Thevenin equivalent model, discretizing a sub-module capacitor based on a numerical integration method to establish an on-state loss model of the sub-module; s3, correcting to obtain the turn-on loss and turn-off loss of the IGBT and the reverse recovery loss of the diode; s4, in one simulation step, on-state loss is obtained through calculation based on an on-state loss model, the total switching frequency is obtained through calculation according to port data of the Thevenin equivalent model, and switching loss is obtained through combination of on-state loss and off-state loss of an IGBT and reverse recovery loss and switching frequency of a diode; and S5, taking the sum of the on-state loss and the switching loss as total loss. Compared with the prior art, the method has the advantages that real-time updating in the simulation step can be realized, the calculation complexity is controllable, and the overhead is remarkably reduced while the engineering precision is ensured.

The invention discloses a bidirectional power electronic switch, a hybrid DC circuit breaker and a control method. The bidirectional power electronic switch comprises a diode bridge module, a buffer circuit, a voltage limiting circuit and an impedance adjusting circuit. The impedance adjusting circuit is connected in parallel with two ends of the diode bridge module; the buffer circuit is connected in parallel with a breaking electronic switch in the diode bridge module; the voltage limiting circuit is connected in parallel with two ends of the breaking electronic switch; the diode bridge module controls the breaking electronic switch to switch current according to a breaking instruction of the power system; when the breaking electronic switch is locked, the buffer circuit suppresses the voltage and current changes of the breaking electronic switch in the switching process, the voltage limiting circuit limits the overvoltage level of the breaking electronic switch, and the impedance adjusting circuit reduces the oscillation frequency. The impedance adjusting circuit reduces the oscillation frequency, reduces the requirement for the reverse recovery speed of the diode, reduces the stress of the diode bridge type module, and enables a conventional common diode to be not liable to be damaged.

A first contact hole at the top of a source region is directly composed of a material layer of a front metal layer filled in an opening of the first contact hole, the front metal layer is made of AlSiCu, and the content of Si in the AlSiCu reaches a saturation value; the AiSiCu of the first contact hole directly forms ohmic contact with the source region and the semiconductor material of the first epitaxial layer of the second conductive type well, and by utilizing the characteristic that the content of Si in the AlSiCu reaches a saturation value, the sharp convex defect is prevented from being formed when the A1Cu directly contacts with the semiconductor material of the first epitaxial layer; by utilizing the characteristic that the resistivity of AlSiCu is greater than that of AlCu, the forward conduction voltage drop of the body diode is increased, and the reverse recovery characteristic of the device is improved. The reverse recovery charge can be reduced, and the reverse recovery characteristic of the device can be improved.

The invention provides a trench type MOSFET device integrated with a junction control diode and electronic equipment, and relates to the technical field of semiconductor devices. The P-type epitaxial layer, the first P-type masking layer and the second P-type masking layer are grounded, a better electric field shielding effect can be obtained during reverse voltage withstanding, and voltage jump caused by floating of the P-type epitaxial layer, the first P-type masking layer and the second P-type masking layer can be avoided in the switching process, so that degradation of the switching characteristic of the device is avoided. Moreover, a junction-controlled fly-wheel diode region is led out between the two trench MOSFET regions, and the conduction voltage drop of the integrated junction-controlled fly-wheel diode is lower than that of a body diode of the device, so that the conduction of the body diode is shielded; moreover, the junction-controlled fly-wheel diode is a unipolar device, does not have a minority carrier storage effect, is short in reverse recovery time, can reduce the switching loss of the device, and improves the performance of the trench type MOSFET device.

An example apparatus includes: a first and second capacitor; a first and second inductor; a first switch having a first and second terminal, the first terminal coupled to the first capacitor, and the second terminal coupled to the first and second inductor; a second switch having a third and fourth terminal, the third terminal coupled to the second terminal, the fourth terminal coupled to the second capacitor; a third switch having a fifth and sixth terminal, the fifth terminal coupled to the first terminal, the sixth terminal coupled to the second inductor; and a diode having a seventh and eighth terminal, the seventh terminal coupled to the sixth terminal, the eighth terminal coupled to the fourth terminal.

The invention provides a semiconductor power device with a wide safe operation area and a preparation method thereof, and the device comprises a first groove and a second groove which are respectively formed in different areas of an epitaxial layer; a source polysilicon layer is formed at the bottom of the trench, a third isolation layer, a second isolation layer and a first isolation layer are sequentially formed on the outer side of the source polysilicon layer, an isolation oxide layer and a gate polysilicon layer are sequentially formed on the source polysilicon layer, and a gate oxide layer is formed on the outer side of the gate polysilicon layer; the thickness of the first isolation oxide layer is greater than that of the second isolation oxide layer, and the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. The method has the beneficial effects that the isolation oxide layers with different thicknesses are formed in the device active region division regions, so that the gate-drain capacitance is reduced, and the device switching frequency is improved; meanwhile, the gate oxide layer adopts a single layer to realize different thicknesses in different areas, so that the threshold voltages of the cells in different areas are different, and the safe working area of the power device is widened; and a good compromise between the forward conduction capability and the reverse recovery capability is realized.

The invention discloses an FCE diode and a manufacturing method thereof. The cathode metal is provided with a trench isolation region, cathode N + regions and cathode P + regions, the cathode N + regions and the cathode P + regions are transversely and alternately arranged, the trench isolation region isolates the cathode N + regions from the cathode P + regions, and the thickness of the trench isolation region exceeds 2 microns of the cathode N + regions and the cathode P + regions And then a plasma storage region, a field stop region, a base region, an anode P region and anode metal are sequentially arranged. The thickened trench isolation region is indispensable for improving the current density uniformity near the cathode, and can weaken low-frequency oscillation and reduce conduction voltage drop; the thickened plasma storage region can weaken low-frequency oscillation, improve the current density uniformity near the anode and reduce reverse recovery energy under severe or extreme conditions; the two measures can also ensure that the base region is greatly thinned on the premise of enlarging the safe working region, so that the loss is reduced. By optimizing and compromising the structural parameters of each area, the FCE diode can achieve the beneficial effects of self-clamping, low loss, uniform current density, no high-frequency oscillation, slight low-frequency oscillation and wide safe working area.

The invention discloses a buck-boost circuit, a frequency converter, electric equipment and a control method. The buck-boost circuit comprises a buck module, the input end of which is connected with a DC power supply and the output end of which is connected with a load; the input end of the boosting module is connected with the direct-current power supply, and the output end is connected with a load; and the change-over switch is arranged between the step-down module and the step-up module and is used for controlling one of the step-down module and the step-up module to be switched on according to the output voltage of the direct-current power supply and the target direct-current bus voltage. According to the invention, the voltage stress of the switching device can be reduced, thereby reducing the switching loss and the reverse recovery time of the diode, achieving the reduction of the heating of the switching tube, breaking through the frequency limitation of the switching tube, widening the switching frequency range of the switching tube, and widening the output voltage range.

The invention provides a planar gate VDMOS with low reverse recovery interference and a preparation method thereof. A barrier layer is formed above a silicon carbide substrate provided with a drain metal layer, the barrier layer is etched to form a through hole, and ion implantation is performed on the silicon carbide substrate to form a plurality of buffer regions; removing the barrier layer, and performing epitaxial growth on the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, and a variable doping region, a P-type well region, a P-type source region and an N-type source region are formed; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the method comprises the following steps: forming a buffer region in a device, re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that the buffer region is constructed in the device, the rising edge of reverse recovery overshoot of the device can be effectively reduced, and the external interference of the device is reduced.

The invention belongs to the field of semiconductor devices, provides a gallium nitride high-electron-mobility transistor integrated with a Schottky diode and a preparation method of the gallium nitride high-electron-mobility transistor, and aims to solve the problem that a conventional gallium nitride high-electron-mobility transistor (GaN HEMT) lacks a body diode. According to the invention, monolithic integration of the SBD and the GaN HEMT is realized through structural design, a low-impedance path is provided for reverse current, and the integration mode not only retains the original high performance characteristic of a GaN device, but also additionally endows the GaN device with reverse conduction and reverse recovery capabilities; moreover, through the structural design, the SBD can be synchronously completed on the basis of the existing GaN HEMT process, a special process or new equipment is not needed, and the cost is effectively controlled while the performance improvement is ensured; compared with an external interconnection diode scheme, parasitic inductance caused by lead bonding is eliminated, the voltage overshoot and ringing phenomena in the switching process are remarkably reduced, high-frequency switching application is facilitated, and switching loss can be greatly reduced.

The utility model relates to the technical field of MOS semiconductors, and discloses a trench gate super junction VDMOS device, comprising a VDMOS device composed of a plurality of VDMOS cells, the VDMOS device comprising a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and a heavily doped N well layer, and the N well layer is isolated from the diffusion layer through the P well layer; wherein the P-well layer comprises a lightly doped P-well layer I, a heavily doped P-well layer I and a heavily doped P-well layer II; the diffusion layer forms a first lightly doped diffusion layer, a second lightly doped diffusion layer and a third lightly doped diffusion layer through ion implantation of phosphorus elements with different concentrations. According to the utility model, the heavily-doped P-well layer I is formed by ion implantation between adjacent VDMOS cells, and the lightly-doped layer has a lower charge conduction effect, so that when the switching tube is conducted, due to the constraint of the lightly-doped layer and the heavily-doped P-well layer I, the injection of unbalanced carriers is reduced, and reverse recovery charges are reduced.

A process for monitoring a degradation state of an electrical interconnection (15) in a power module assembly (100), comprises capturing a detection signal that is sensitive to a reverse recovery current originating from a diode (14) of the power module assembly. The reverse recovery current is triggered by a turning-on switching operation of a switch (11) in a tested half-bridge branch (1) that comprises said diode, switch and interconnection. The invention process may be combined optionally with another monitoring process based on a turning-off switching operation of the switch, for monitoring a degradation state of another electrical interconnection within the same half-bridge branch. Complete interconnection monitoring for said half-bridge branch is thus possible.

The invention relates to the technical field of data processing, in particular to a high-frequency diode conduction loss characteristic test system, which comprises an acquisition module, a first judgment module, a second judgment module, a first determination module, a second determination module, an adjustment module and an output module. According to the method, multiple key data are collected, rapid screening is carried out according to forward voltage and reverse recovery charges, then, hidden defects of abnormal dynamic relevance of parameters are analyzed and identified by introducing shell temperature, and finally, a high-loss diode is obtained; the trend abnormity is identified by using the space-time distribution characteristics of the high-loss diode, and the loss reason is accurately detected through the voidage fluctuation mode; and meanwhile, based on a self-adaptive adjustment mechanism fed back by the test accuracy, a test report is finally output, so that the problems of low identification accuracy of the high-loss diode and low detection accuracy of loss reasons caused by excessive dependence on static parameters and incapability of adapting to complex and changeable working conditions are effectively solved.

The invention relates to the technical field of power semiconductor devices, and discloses a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction control diode and a method. A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source electrode contact region and the P-type well region and goes deep into the trench MOSFET region of the first N-type epitaxial layer. According to the invention, the junction-controlled freewheeling diode is integrated at the side of the shield grid, so that the conduction voltage drop of the diode during freewheeling is reduced, and the reverse recovery time is greatly shortened. A high-turn-on-voltage diode is additionally arranged at the bottom of the shielding grid, the turn-on voltage is bipolar conduction, self-turn-on conduction is achieved under extreme working conditions such as surge, and the reliability of the device is improved. And the shielding grid electrode can form an electric field shielding effect during reverse voltage withstanding, so that electric field clamping at the bottom of the true grid electrode is realized.

According to the trench-type super-junction field effect transistor and the preparation method thereof provided by the invention, an air gap exists in a lower conductive column region of a conductive column, and the doping concentration of the lower conductive column is smaller than that of an upper conductive column, so that the resistance of the lower conductive column of the conductive column is larger than that of the upper conductive column; when the device is turned off, that is, when majority carriers are compositely extracted, the lower conductive column region is affected by a larger resistance value, and the moving speed is slowed down, so that the reverse recovery current peak is reduced when the device is turned off, and especially when minority carrier lifetime control of the device is improved, the reverse recovery softness of the super junction diode is improved, and the service life of the super junction diode is prolonged. And the switching loss and the current oscillation are reduced. And meanwhile, the height of the lower conductive column is smaller than that of the upper conductive column, so that the specific on-resistance of the device can be reduced or even avoided, and the influence on the conductive efficiency, the power loss, the switching speed, the voltage endurance capability and the like of the device caused by the specific on-resistance can be reduced or even avoided.