822 results about "Junction temperature" patented technology

The invention discloses a temperature control and noise reduction method for an analog optical module, and relates to the technical field of data processing. The method comprises the following steps: collecting and preprocessing an original temperature signal, environment temperature time sequence data and an optical wavelength original detection value of an optical module; improving the LSTM model, constructing a junction temperature dynamic prediction model, and outputting prediction data; a pre-trained BP neural network is utilized to calculate the temperature compensation amount according to the real-time wavelength offset, and a PPO reinforcement learning algorithm is adopted to optimize with the temperature stability, the wavelength offset and the TEC power consumption as multiple targets to obtain an optimal PID parameter mapping table; and finally, predicting, compensating and optimizing parameters are fused, and control output for driving the TEC is generated through a multi-mode intelligent decision. The problems of insufficient control precision and response lag are effectively solved, cooperative high-precision control over the junction temperature and the emission wavelength of the laser is achieved, transmission noise is remarkably reduced, and meanwhile system energy consumption and the self-adaptive capacity are considered.

The invention relates to the technical field of elevator control and fault diagnosis, and discloses an elevator inverter fault pre-diagnosis and fault-tolerant control system and method based on digital twinning, and the system comprises a high-fidelity digital twinning body building module which is used for building a digital twinning body of an elevator inverter, the digital twin integrates an electric-thermal-stress coupling model, a device-level aging model, a parasitic parameter influence model and a driving circuit and protection logic model; wherein the electric-thermal-stress coupling model is used for simulating loss, junction temperature fluctuation and thermal stress circulation of a power device, and the device-level aging model is used for representing a time-varying degradation rule of device parameters. Through deep fusion of a digital twin technology, fault diagnosis and fault-tolerant control, a closed-loop system of'perception-pre-diagnosis-decision-control 'is constructed, the safety, reliability and economical efficiency of the elevator inverter are comprehensively improved, and the method has important significance in promoting transformation of the elevator industry to intelligent and unmanned maintenance.

The invention discloses a CPLD-driven IGBT short-circuit current dynamic monitoring method and system, and relates to the technical field of power electronics, and the method comprises the specific steps of S100 real-time data acquisition, S200 dynamic threshold calculation, S300 short-circuit state judgment, S400 rapid protection execution, and S500 fault data recording and uploading. Accurate and prospective judgment of the short circuit state of the IGBT is achieved, two stress parameters including the direct-current bus voltage and the junction temperature serve as independent variables, when the bus voltage rises, the voltage stress borne by the IGBT in the turn-off period is increased, meanwhile, the current peak at the short circuit moment is more remarkable, early warning is conducted in advance by dynamically lowering the threshold value, and therefore the short circuit state of the IGBT is accurately judged. According to the mechanism, the monitoring system does not simply respond to the occurred overcurrent, but can pre-judge the safety boundary of the device under the current working condition, so that intervention is implemented before the current really reaches a dangerous peak value, and a protection blind area under a severe working condition is effectively avoided.

The invention relates to the technical field of chip test engineering control, in particular to an active temperature control method and system for a chip aging tester, and the method comprises the steps: analyzing a test process according to test task parameters, and evaluating the expected thermal load change rate of a test chip, so as to dynamically generate a chip target junction temperature control curve; based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through a junction temperature closed-loop control algorithm, the furnace temperature compensation amount is calculated through a feedforward compensation algorithm in combination with the test state parameters, and the ideal furnace temperature is obtained according to the theoretical furnace temperature and the furnace temperature compensation amount; the actual temperature control quantity is obtained according to the basic temperature adjusting quantity and the temperature control compensation quantity, a preset chip target junction temperature control curve can be tracked more accurately, transient and steady state errors caused by test program switching and environment fluctuation can be more effectively restrained, and control over the chip junction temperature with higher precision and faster response is achieved.

The invention discloses a high-precision power supply output correction method based on a digital pre-distortion technology, and relates to the technical field of power electronics, and the method comprises the steps: integrating an electricity-heat-magnetism real-time combined observer, and inputting parameters including a power supply output voltage, a current, a power device junction temperature, a magnetic element surface temperature, an environment temperature, and an input voltage ripple; using a hierarchical memory depth pre-distortion compensator to generate an anti-phase pre-distortion signal containing long time domain thermal constant compensation and short time domain capacitance energy storage compensation based on modeling engine output; based on a double-ring adaptive updating module, an inner ring updates electrical parameters, including on resistance and dead time, by taking a switching period as a reference, and an outer ring updates thermomagnetic parameters, including thermal resistance and a magnetic core saturation point, in a minute-level period; and the DAC is connected in series with a pre-distortion signal output end through an anti-interference execution channel, and comprises a noise shaping DAC and a driving stage for delay matching. According to the invention, through an electric-thermal-magnetic three-field combined observation architecture, the limitation of traditional single physical field monitoring is broken through.

The invention relates to a chip integrated heat dissipation system and a preparation method thereof, and belongs to the technical field of heat dissipation of semiconductor devices. The chip integrated heat dissipation system comprises a nano-diamond transition layer attached to a chip. A micro-column array supporting layer is arranged on one side, far away from the chip, of the nano-diamond transition layer; the micro-column array supporting layer is in contact with one surface of the diamond film, and the other surface of the diamond film is attached to the three-dimensional micro-channel heat dissipation layer. The invention also provides a preparation method of the chip integrated heat dissipation system. The chip integrated heat dissipation system provided by the invention has the advantage of efficient heat dissipation, and through the combination of the three-dimensional structure and the high heat conduction characteristic of diamond, the heat dissipation power density is remarkably improved, the junction temperature of the chip is reduced, and the heat dissipation requirement of a high-power device is met. The heat dissipation performance reliability is high, the thermal stress is eliminated through the gradient structure design, the interlayer binding force is improved, and the stable performance is still kept after multiple thermal cycles. And the preparation process is good in compatibility and convenient for large-scale production.

The invention provides an LED lamp adaptive speed regulation heat dissipation method and system based on real-time junction temperature monitoring. The method comprises the following steps: S100, acquiring a PWM signal or an analog signal of an LED driving command signal in real time; s200, on the basis of the change of the driving instruction signal, feedforward prediction is carried out by using a dynamic thermal inertia mapping model, and a feedforward fan control quantity is generated; s300, LED junction temperature is monitored in real time through a forward voltage method, and feedback fan control quantity is generated through a feedback controller according to the deviation between the real-time junction temperature and the target junction temperature; and S400, synthesizing the feedforward control quantity and the feedback control quantity to generate a fan PWM control signal, outputting the fan PWM control signal to a fan driving circuit, and adjusting the rotating speed of the cooling fan. According to the method, driving signals and junction temperature information are processed in parallel, and feedforward and feedback control is combined, so that self-adaptive accurate regulation and control are realized, thermal load change is quickly responded, system lag is effectively inhibited, and LED heat dissipation performance is optimized.

The invention discloses a rapid thermal simulation method and system for a semiconductor power assembly, and relates to the technical field of semiconductors, and the method comprises the steps: collecting a voltage V (t) signal and a current I (t) signal of the semiconductor power assembly in real time through a voltage and current sampling circuit, constructing a power pulse input sequence A, and carrying out the hot carrier accumulation analysis according to the power fluctuation change amplitude; introducing a transient thermal resistance function Zth (t), fitting the transient thermal resistance function Zth (t) with a hot carrier pulse response index Mcx after numerical integration to analyze junction temperature change caused by power pulse, and evaluating an equivalent junction temperature dynamic change rate; when the analysis result is that the thermal drift out-of-control trend exists, thermal risk analysis is carried out, and thermal risk state assessment is generated; the simulation model optimizes thermal model parameters and outputs thermal control suggestions through a rollback correction path, and the working state of the semiconductor power assembly is automatically adjusted. According to the method, real-time monitoring and effective prevention and control of thermal runaway can be realized, and the reliability and safety of the semiconductor power assembly are improved.

The invention discloses an LED display screen brightness uniformity correction method and system based on current feedback, and relates to the technical field of brightness correction.The method comprises the steps that firstly, a vertical blanking period time sequence empty window is utilized, high-low double-amplitude detection current is injected into LED pixels, and voltage responses in different excitation states are obtained on the premise that normal display is not interfered; then, constructing a state decoupling model based on a reference I-V-T characteristic spectrum, and deeply analyzing coupled electrical signals into independent real-time junction temperature and aging factors by using differential sensitivity characteristics of voltage to temperature and aging; and then, on the basis of the physical state parameters, reverse compensation operation is performed in combination with an original gray instruction and a reference L-I brightness model, and target driving current capable of counteracting thermal quenching and aging attenuation is dynamically deduced. In this way, the correction problem caused by deep coupling of temperature drift and device aging can be effectively solved, and therefore self-adaptive high-precision brightness uniformity correction in the full life cycle of the display screen is achieved.

The invention relates to the technical field of novel illumination, and discloses a wide-voltage light source intelligent control method integrated with a step-down regulation strategy, which comprises the following steps: establishing a mapping table of a voltage interval and a basic compensation slope; indexing a basic slope according to the real-time input voltage; extracting a load voltage direct current component representing the LED junction temperature to generate a thermal drift correction coefficient; dynamically reducing the target slope to match the natural attenuation characteristic of the inductive current; according to the invention, the junction temperature is reversely deduced through the voltage signal, a parameter self-calibration closed loop of a physical level is constructed, the phase margin of a control loop of a whole temperature range is locked under the condition of zero newly-added hardware cost, the problem of dynamic response hysteresis under a high-temperature working condition is solved, and the reliability of the system is improved. And the optical consistency of precise illumination is ensured.

The invention discloses a magnetofluid type silicon controlled rectifier radiator and a heat dissipation control method thereof. The radiator comprises a silicon controlled rectifier, a magnetic fluid chamber is attached to the outer side of the silicon controlled rectifier, the magnetic pole array is installed in the magnetic fluid chamber, and cooling fins are assembled outside the magnetic fluid chamber. When alternating current is introduced into the cavity where the magnetic fluid liquid chamber is located, the alternating current and the magnetic field interact to generate Lorentz force, the Lorentz force drives the magnetic fluid to form directional eddy current so as to achieve convective heat exchange on the silicon controlled rectifier, and heat absorbed by the magnetic fluid and air are subjected to heat exchange through the cooling fins. Junction temperature out-of-control caused by local hot spots of the silicon controlled rectifier can be solved, secondary damage of mechanical vibration of a heat dissipation system to welding spots is eliminated, and the highest junction temperature area of the silicon controlled rectifier is focused and cooled according to needs.

The invention discloses a silicon carbide power module packaging structure with low thermal resistance and low stress, and belongs to the technical field of semiconductor devices. The packaging structure comprises a metal substrate; the insulating ceramic layer is arranged on the metal substrate; the circuit layer is arranged on the insulating ceramic layer; the lower surface of the silicon carbide chip is connected with the circuit layer through a first interface layer; the composite heat dissipation stress buffer layer is arranged on the upper surface of the silicon carbide chip through a second interface layer; the copper clamp is connected with the upper surface of the composite heat dissipation stress buffer layer through a third interface layer; and the composite heat dissipation stress buffer layer is made of a copper-graphite composite material. According to the invention, the junction temperature of the silicon carbide chip can be greatly reduced, the overall thermal resistance is reduced, the surface stress of the chip is reduced, the warping phenomenon of the chip in the working process is effectively improved, and the long-life reliability of the power module under the long-term thermal cycle working condition is ensured.

The invention provides a network construction transient control method for a string type network construction type energy storage converter, which comprises the following steps of: identifying a power grid control instruction, and issuing a network construction operation control instruction and selecting a network construction type after judging a network construction requirement; in response to the networking operation control instruction, starting a thermal management system and executing a function screening control strategy; on the basis of the real-time electrical parameters and thermal parameters acquired by the information acquisition system, network construction over-temperature prediction is executed, and predicted junction temperature and predicted loss under the network construction working condition are obtained; according to the result of the network construction over-temperature prediction, whether network construction operation parameters need to be optimized is judged, if yes, a parameter optimization control instruction is generated, and if not, network construction function operation monitoring is started; and on the basis of the parameter optimization control instruction, virtual impedance is adjusted to reduce the output voltage and the output current of the converter so as to control the loss and the junction temperature, and the adjustment of the virtual impedance is calculated based on the difference value between the predicted junction temperature and the threshold junction temperature.

The invention discloses a graphene integrated electrode LED epitaxial structure and a chip preparation method. The epitaxial structure sequentially comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type limiting layer, a non-doped quantum well structure, a p-type spacer layer, a p-type electron barrier layer and a p-type GaP ohmic contact layer from bottom to top. The preparation method comprises the steps of epitaxial structure growth, p-type ITO transparent conductive layer preparation, bonding and substrate removal, mesa structure preparation, passivation isolation, graphene interconnection layer preparation and n-type electrode preparation. Graphene is used for replacing a traditional n-type GaAs ohmic contact layer and an ITO electrode, the problems of poor red light absorption, poor heat dissipation and mechanical brittleness of a traditional structure are solved, the red light transmittance of the chip is improved, the junction temperature under 3 currents is greatly reduced, the chip can bear tensile strain larger than 20%, the chip is suitable for flexible scenes, and the chip is suitable for high-performance large-scale production of red light Micro LEDs.

The invention relates to the technical field of power electronics, in particular to a photovoltaic inverter heat dissipation adjustment control system. Comprising a multi-mode state prediction module which is used for receiving environment data collected in real time and historical working state data of an inverter and predicting predicted junction temperatures in one or more time steps in the future; the collaborative optimization decision module is used for receiving the predicted junction temperature and obtaining an optimal control parameter combination and an expected steady-state junction temperature; the feed-forward control execution module is used for receiving the optimal control parameter combination and setting the optimal fan rotating speed in the optimal control parameter combination as a reference set value of the cooling system rotating speed controller; the feedback correction module is used for obtaining a fan rotating speed correction value; and the instruction synthesizing and sending module is used for sending the final target rotating speed instruction to a bottom-layer speed controller of the fan. According to the system, the problems of temperature overshoot and frequent start and stop of a heat dissipation system caused by traditional passive response type control are avoided, and the stability of system operation is improved.

The invention relates to an IGBT module junction temperature estimation method and system, and the method comprises the following steps: obtaining a performance curve set of an IGBT module under different working conditions, and carrying out the fitting optimization, and obtaining an optimal performance curve set; constructing a transient thermal resistance curve model according to a transient thermal resistance principle, and constructing a second-order Foster thermal network model based on the transient thermal resistance curve model; performing Laplace transformation and discretization processing based on a backward difference method on the second-order Foster thermal network model to obtain a junction temperature estimation model; collecting a phase current instantaneous value, and calculating the total power loss of the IGBT module in real time in combination with the optimal performance curve set; and finally, the junction temperature of the IGBT module is obtained in real time by using the total power loss of the IGBT module obtained through real-time calculation and the junction temperature estimation model, and junction temperature estimation is completed. According to the method, the effect of improving the power loss precision of the IGBT module is achieved by optimizing the performance curve, and then the junction temperature estimation precision is improved.

The invention discloses a packaging substrate with a temperature detection function, a power semiconductor module and a manufacturing method thereof, and the packaging substrate with the temperature detection function comprises an integrated ceramic insulating layer which is provided with a first surface and a second surface which are opposite to each other; the temperature sensor comprises a ceramic insulating layer, a sensor mounting groove, an independent temperature sensor chip, an insulating filling body and a three-dimensional interconnection structure, and is configured to lead an electric signal of the temperature sensor chip to an external bonding pad on the second surface or the side surface of the ceramic insulating layer, the packaging substrate has the advantages that high-precision and quick response measurement of junction temperature of a power chip can be achieved, temperature rise decoupling deviation is eliminated, excellent high-voltage electrical isolation reliability is ensured while direct thermal coupling is achieved, the dielectric breakdown risk is avoided, the manufacturing method is flexible, the reliability of a power semiconductor module is improved, and the manufacturing cost is reduced. The comprehensive cost is reduced, and the long-term stability of temperature monitoring can be ensured while the rapid and accurate electrothermal response characteristic of the sensing unit is ensured.

The invention belongs to the technical field of junction temperature measurement of converter power electronic devices, and particularly relates to a converter power device junction temperature real-time estimation method. In order to overcome one or more defects of insufficient measurement precision, repeated parameter adjustment and incapability of adapting to system parameter changes of an existing junction temperature prediction method, the invention adopts the following technical scheme: the converter power device junction temperature real-time estimation method comprises the following steps: obtaining device loss at a current sampling moment according to real-time operation parameters, and obtaining shell temperature information; as the input of an adaptive Kalman filter, the adaptive Kalman filter obtains an estimated junction temperature according to a thermal impedance model prediction method and device loss, and the adaptive Kalman filter also performs adaptive estimation on a measurement noise covariance matrix and a process noise covariance matrix; and the estimated junction temperature of the model is fed back and corrected in real time in combination with the measured junction temperature. The method has the advantages that the Kalman filter is improved in a self-adaptive mode, and the adaptability to system operation parameter changes is enhanced.

The invention discloses a heat dissipation enhanced semiconductor packaging method, which comprises the following steps of: performing deep silicon etching to form a vertical through hole; insulation and metallization are carried out; thinning the wafer; performing hybrid bonding and stacking of multiple layers of chips; a heat dissipation design is adopted to form a vertical heat dissipation path; a three-dimensional thermal through hole network: adding pure copper thermal through holes in a non-functional area; performing microfluid cooling integration; molding and packaging; and thermal performance verification: verifying that the junction temperature can be controlled within 85 DEG C through infrared thermal imaging and finite element simulation. The TSV with the depth-to-width ratio of 10: 1 can be realized by adopting the Bosch process; a three-dimensional integrated TSV array supporting HBM and other high-speed memories is embedded into diamond or graphene heat dissipation columns, a low-heat-resistance vertical heat dissipation path is formed by combining a three-dimensional pure copper heat through hole network, and local hot spots are effectively dispersed; the high-thermal-conductivity epoxy molding compound and the embedded copper block enhance the overall mechanical strength and thermal diffusivity, so that the product can dissipate heat efficiently, and the overall area is not easy to influence.

The invention relates to the field of rail transit, and discloses an online monitoring system adapted to a SiC power device recycling scene, and the system comprises the steps: collecting key operation parameters of a SiC power device in real time, and when the collected parameters exceed a preset warning threshold value, judging whether the subsequent failure trend prediction needs to be carried out or not; constructing a device performance change curve based on the collected operation parameters, analyzing the curve type and the fluctuation trend, judging whether the device has a potential failure risk or not, and judging whether key monitoring or load regulation and control need to be performed on a specific module or not by combining the parallel operation state of the device and a historical abnormal fluctuation event; the influence degree of the potential failure trend is determined by analyzing the relevance among on-resistance sudden change, junction temperature fluctuation, welding layer cavity expansion and bonding interface aging, and according to the influence degree of the potential failure trend and a warning threshold value, an online early warning signal is output and a regulation and control instruction is executed. The method has the advantage of finding the potential failure trend in advance.

The invention discloses a leakage current testing device and method for a chip. The leakage current testing device comprises a chip testing seat, an interface module and a control module, a temperature control unit and a current acquisition unit are integrated on the chip test seat; the interface module is in signal connection with the chip testing seat and is used for acquiring real-time temperature and real-time current parameters of the chip to be tested and feeding back the real-time temperature and the real-time current parameters to the control module; the control module is used for comparing the real-time temperature with a preset temperature interval, and obtaining a leakage current parameter of the to-be-tested chip based on the real-time current parameter when the real-time temperature is in the preset temperature interval. According to the invention, the working power of the temperature control unit can be controlled based on the real-time temperature of the chip, so that the real-time temperature of the chip is in the preset temperature interval, and when the real-time temperature of the chip is stabilized in the preset temperature interval, the leakage current parameter of the chip is obtained based on the real-time current parameter of the chip. Leakage current changes of the chip at different junction temperatures can be tested with low cost and high efficiency, and engineering application and system design of the chip are optimized.

The invention provides an IGBT junction temperature prediction model construction method and system, and relates to the technical field of power electronic device thermal management, and the method comprises the steps: obtaining an initial data set representing the transient thermal response relation between an IGBT chip and an NTC temperature measurement point in an IGBT power module where the IGBT chip is located; training a neural network model based on the initial data set, and learning and representing a nonlinear function relationship between time and thermal impedance; inputting a preset new time sequence into the trained neural network model, and generating a time-continuous and noise-suppressed optimized thermal impedance data set; and based on the data set, performing parameter fitting on a preset lumped parameter thermal network model to identify thermal resistance and thermal capacity parameters of the model so as to complete construction of the junction temperature prediction model. According to the method, the neural network is used as a data optimization tool in a physical model parameter identification process, and accurate and convenient online prediction of the IGBT junction temperature is realized only by using the temperature signal of the NTC temperature measurement point of the module.

The invention discloses a method for constructing a correlation mathematical model of time-phased overcurrent capability and electric-thermal limit parameters of a power device of a high-voltage direct-hanging network-constructing energy storage system. Based on the short-time overload capacity requirement of the energy storage system, obtaining a selection range of an alternating current operation point; the alternating current operation point is selected in the range; calculating current flowing through a power device in a converter valve bridge arm of a direct-hanging converter of the energy storage system; calculating the junction temperature of the power device under the alternating current operation point; checking whether the current flowing through the power device and the junction temperature meet an electric-thermal limit constraint condition or not; and classifying the alternating current operation points according to the short-time overload capacity requirement, and further obtaining the active and reactive current safe operation range of the high-voltage direct-hanging grid-constructing type energy storage system.

The invention discloses a heterogeneous device hybrid ANPC converter junction temperature equalization method. The method comprises the following steps: S1, optimizing junction temperatures among ANPC devices; s2, if the maximum junction temperature appears in the hybrid device, entering S3; s3, optimizing the internal junction temperature of the hybrid device; the PWM rotation strategy of the ANPC converter and the hybrid device switch time sequence switching strategy are combined, the junction temperature between devices is relatively balanced by adjusting the switch loss distribution of the converter, the power output capacity of the converter is improved, and it is guaranteed that the converter can operate safely and reliably under different working conditions.

The invention provides an output peak current capability identification method, system and device and a medium, and relates to the technical field of motor controllers, and the method comprises the steps: obtaining a power loss function of a power unit in a power module; constructing an initial junction temperature observer according to thermal resistance network nodes of the power module; acquiring peak current of the power module under different preset boundary conditions through a power module test, wherein each preset boundary condition comprises a preset value of each peak current output capability influence factor of the power module; performing test correction on the initial junction temperature observer based on the power loss function and the peak current of the power module under different preset boundary conditions to obtain a target junction temperature observer; the peak current of the power module under the real boundary condition is obtained based on the power loss function and the target junction temperature observer, the current output capacity of the motor controller can be maximized on the premise that the junction temperature of the power unit does not exceed the safety threshold value, and the performance potential of the motor controller is brought into full play.

The invention discloses a preparation method of heat-conducting silica gel for packaging a power module chip, which comprises the following steps of: optimizing diamond micro-powder filling, surface etching and particle size compounding, so that the heat conductivity coefficient of the prepared heat-conducting silica gel can reach 3.8-4.5 W / (m.K) which is far higher than that of common silica gel (generally less than or equal to 3.0 W / (m.K)); meanwhile, the specific surface area of the diamond and the interface bonding force between the diamond and silica gel are improved through surface etching, the interface thermal resistance is reduced, a more efficient heat conduction path is formed, the packing stacking density is maximized through particle size compounding, air gaps are reduced, and a more stable and communicated heat conduction network is constructed; the SiC device is high in power density and high in switching speed, and the chip junction temperature is the key to restrict performance and reliability. The material can quickly and uniformly transfer heat of a chip to a heat dissipation substrate, obviously reduce junction temperature and temperature gradient in a module, and improve power density and long-term reliability.

The invention relates to a heat dissipation analysis and optimization method for an IGBT module, and the method comprises the steps: obtaining the electrical parameters and working conditions of the IGBT module, and calculating the total power loss during the operation of the IGBT module based on the electrical parameters and working conditions. Based on the total power loss and the physical structure of the IGBT module, a thermal resistance network model of a semiconductor junction region and a cooling environment and a Cauer type thermal impedance model based on dynamic characteristics are established. Inputting the total power loss into the thermal resistance network model and the Cauer type thermal impedance model, calling a finite element simulation algorithm to solve a temperature distribution field of the IGBT chip, and determining the total equivalent thermal resistance. And when the junction temperature or the total equivalent thermal resistance of the IGBT chip does not meet the set index, positioning the heat dissipation bottleneck and generating a heat dissipation optimization strategy. And executing a heat dissipation optimization strategy, and updating the thermal resistance network model and the Cauer type thermal impedance model after executing the heat dissipation optimization strategy so as to update the temperature distribution field and the total equivalent thermal resistance.

The invention provides a three-phase low-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) packaging integrated power module. A driving assembly, a direct-current bus capacitor and other modules are integrated in an aluminum shell package. The three DBC substrates respectively bear U-phase bridge arms, V-phase bridge arms and W-phase bridge arms, an upper bridge arm and a lower bridge arm of each phase are formed by a plurality of parallel MOSFET chips, drain electrodes of the chips are directly welded to a DBC upper copper layer, grid electrodes of the chips are connected with an upper-layer driving circuit board through copper columns, source electrodes of the chips are led out to a direct-current input terminal or an alternating-current output terminal through bonding wires, and a double-layer conductive structure is formed. A plurality of direct-current bus capacitors which are arranged above the aluminum shell in parallel are adjacently coupled with the DBC substrate, so that low-impedance energy buffering is realized; the alternating current output terminal is sleeved on the current sensor, detects the phase current and outputs the phase current through the signal terminal; and a thermistor is mounted on a copper layer on each DBC to monitor the junction temperature of the chip and provide over-temperature protection. The direct-current input terminal, the alternating-current output terminal, the power terminal and the signal terminal are integrally embedded in the aluminum shell and are directly butted with an external busbar and a controller, and additional sampling and driving boards are not needed.

The invention discloses an IGBT module junction temperature prediction method and system based on an LSTM thermal neural network, and belongs to the technical field of IGBT application. Comprising the following steps: analyzing the unsteady state heat transfer characteristics of multiple layers of materials in the IGBT module, and constructing a discrete heat transfer (DHT) equation; a training data set containing temperature response data under different power loss conditions is generated through finite element FEM simulation; constructing an LSTM thermal neural network junction temperature prediction model embedded into a physical layer, wherein the physical layer comprises a sub-neural network to extract a mapping relation between input features and thermal resistance and thermal capacity; and training the model by using the training data set, and converting the DHT equation as a physical constraint into a model parameter dynamic constraint condition, thereby realizing prediction of the junction temperature of the IGBT module under different operation conditions. According to the method, the physical heat transfer process and the LSTM network are fused, limitation of an existing method is overcome, accurate and rapid prediction of the junction temperature of the IGBT module is achieved, and reliability and economical efficiency of thermal management of the IGBT module are effectively improved.

The invention discloses a direct current motor drive circuit layout optimization method based on thermal simulation, and relates to the technical field of circuit layout optimization. The method comprises the following steps: modeling circuit thermal characteristics, defining a thermal resistance network of a power device, considering a heat conductivity coefficient of a PCB, constructing an electric-thermal coupling model, setting boundary conditions, loading current and voltage, solving a temperature field by using a Joule law and a Fourier equation, defining layout variables, establishing an objective function containing junction temperature, temperature difference and cost, and performing iterative optimization by using a genetic algorithm. And thermal simulation optimization of the layout of the driving circuit is realized. The temperature field is accurately predicted, the heat management efficiency is improved, and the optimization period is shortened; thermal coupling influence is reduced, chip stability is guaranteed, multi-working-condition verification is reliable, heat dissipation is consistent with simulation, cost can be reduced, and safety and service life of a motor system are improved.