The application relates to the technical field of
chip packaging, and particularly discloses a full-bridge packaging structure and a packaging method for multiple chips in parallel. The packaging structure comprises a heat dissipation bottom plate, a
copper-coated
ceramic substrate, power
semiconductor chips, bonding wires, driving resistors, thermistors, positive and negative
copper bars, pouring glue, a shell and wiring terminals. The
copper-coated
ceramic substrate is welded on the heat dissipation bottom plate, the power
semiconductor chips, the thermistors and the wiring terminals are welded on the
DBC substrate, and the surface electrodes of the power
semiconductor chips are electrically connected with the
DBC substrate through the bonding wires. The packaging structure provided by the application realizes a compact, compatible, multiple-
chip parallel, high-reliability, low-stray-
inductance and current-sharing packaging module through reasonable
DBC substrate
layout optimization, the
driving circuit adopts a
Kelvin structure, the
negative feedback influence of common-source parasitic
inductance on the
driving circuit is reduced, and the switching speed is improved. The corresponding method enables the packaging structure to be realized at low cost and with reliable
processing quality.