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5608 results about "Secondary layer" patented technology

Subcutaneous glucose electrode

A small diameter flexible electrode designed for subcutaneous in vivo amperometric monitoring of glucose is described. The electrode is designed to allow “one-point” in vivo calibration, i.e., to have zero output current at zero glucose concentration, even in the presence of other electroreactive species of serum or blood. The electrode is preferably three or four-layered, with the layers serially deposited within a recess upon the tip of a polyamide insulated gold wire. A first glucose concentration-to-current transducing layer is overcoated with an electrically insulating and glucose flux limiting layer (second layer) on which, optionally, an immobilized interference-eliminating horseradish peroxidase based film is deposited (third layer). An outer (fourth) layer is biocompatible.
Owner:THERASENSE

Biocompatible implant and use of the same

InactiveUS20060252981A1Good biological affinityStrong enoughImpression capsEye implantsRough surfaceBiological body
The present invention provides an implant capable of being cellularized in treatment of an injured organ or tissue in organisms. The present inventors found that a biocompatible implant comprising a biological molecule and a support is capable of being cellularized. The implant can be used instead of conventional implants which essentially comprise cells. The present invention provides a biocompatible implant comprising A) a biological molecule and B) a support. The present invention also provides A) a first layer having a rough surface, B) a rough surface; B) a second layer having a strength which allows the support to resist in vivo shock. The first layer is attached to the second layer via at least one point.
Owner:CARDIO

Semiconductor device and method for manufacturing the same

A semiconductor device 100 is provided with a multiplex through plug 111 that fills an opening extending through the silicon substrate 101. The multiplex through plugs 111 comprises a column-shaped and solid first through electrode 103, a first insulating film 105 that covers the cylindrical face of the first through electrode 103, a second through electrode 107 that covers the cylindrical face of the first insulating film 105 and a second insulating film 109 that covers the cylindrical face of the second through electrode 107, and these have a common central axis. The upper cross sections of the first insulating film 105, the second through electrode 107 and the second insulating film 109 are annular-shaped.
Owner:TESSERA ADVANCED TECH

Semiconductor device and method of fabricating the same

A semiconductor device equipped with the dual damascene structure that is provided, which suppresses the propagation delay of signals effectively without using any complicated processes. The device is comprised of (i) a semiconductor substrate having a lower wiring layer and electronic elements; (ii) a first interlayer dielectric layer formed on the substrate; (iii) a second interlayer dielectric layer formed on the first interlayer dielectric layer, the second interlayer dielectric layer being made of carbon-containing SiO2; (iv) a third interlayer dielectric layer formed on the second interlayer dielectric layer; (v) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer, the fourth interlayer dielectric layer being made of carbon-containing SiO2; (vi) the first and second interlayer dielectric layers having a via hole penetrating therethrough; (vii) the third interlayer dielectric layer having a recess overlapping with the via hole, the recess being formed to communicate with the via hole; (viii) a metal plug formed in the via hole to be contacted with the lower wiring layer or the electronic elements in the substrate; (ix) a metal wiring layer formed in the recess; and (x) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer to cover the metal wiring layer.
Owner:NEC CORP

PECVD oxide-nitride and oxide-silicon stacks for 3D memory application

A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.
Owner:APPLIED MATERIALS INC

Fabrication method of sub-resolution pitch for integrated circuits

A method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a semiconductor substrate, forming a first layer over the semiconductor substrate, forming a second layer over the first layer, patterning the second layer to form a plurality of second layer patterns, patterning the first layer to form a plurality of first layer patterns, performing a tone reversal to form a reversed tone for the second layer patterns, and etching the first layer patterns using the reversed tone as a mask, wherein the etched first layer patterns have a final pitch size, and wherein the final pitch is smaller than the minimum pitch.
Owner:MACRONIX INT CO LTD

Semiconductor storage device

A non-volatile semiconductor storage device has: a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series; and a capacitor element area including capacitor elements. Each of the memory strings includes: a plurality of first conductive layers laminated on a substrate; and a plurality of first interlayer insulation layers formed between the plurality of first conductive layers. The capacitor element area includes: a plurality of second conductive layers laminated on a substrate and formed in the same layer as the first conductive layers; and a plurality of second interlayer insulation layers formed between the plurality of second conductive layers and formed in the same layer as the first interlayer insulation layers. A group of the adjacently-laminated second conductive layers is connected to a first potential, while another group thereof is connected to a second potential.
Owner:KK TOSHIBA

Coated tablet formulation and method

A coated tablet formulation is provided which includes a medicament such as the DPP4-inhibitor, saxaglipitin or its HCl salt, which is subject to intra-molecular cyclization, which formulation includes a tablet core containing one or more fillers, and other conventional excipients, which tablet core includes a coating thereon which may include two or more layers, at least one layer of which is an inner seal coat layer which is formed of one or more coating polymers, a second layer of which is formed of medicament which is the DPP4-inhibitor and one or more coating polymers, and an optional, but preferable third outer protective layer which is formed of one or more coating polymers. A method for forming the coated tablet is also provided.
Owner:ASTRAZENECA AB

Deposited semiconductor structure to minimize N-type dopant diffusion and method of making

In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.
Owner:SANDISK TECH LLC

Dielectric layer for semiconductor device and method of manufacturing the same

InactiveUS6844604B2Improving interface characteristicReduce maintenanceTransistorSolid-state devicesDevice materialInterface layer
A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.
Owner:SAMSUNG ELECTRONICS CO LTD

Balancing multiple computer models in a call center routing system

Systems and methods are disclosed for routing callers to agents in a contact center utilizing a multi-layer processing approach to matching a caller to an agent. A first layer of processing may include two or more different computer models or methods for scoring or determining caller-agent pairs in a routing center. The output of the first layer may be received by a second layer of processing for balancing or weighting the outputs and selecting a final caller-agent match. The two or more methods may include conventional queue based routing, performance based routing, pattern matching algorithms, affinity matching, and the like. The output or scores of the two or more methods may be processed be the second layer of processing to select a caller-agent pair and cause the caller to be routed to a particular agent.
Owner:AFINITI LTD

Method of pitch dimension shrinkage

Roughly described, a patterned first layer is provided over a second layer which is formed over a substrate. In a conversion process, first layer material is consumed at feature sidewalls to form third layer material at the feature sidewalls. The width of third layer material at each of the sidewalls is greater than the width of first layer material consumed at the respective sidewall in the conversion process. The second layer is patterned using the third layer material as mask. A fourth layer of material is formed over the substrate, and planarized or otherwise partially removed so as to expose the top surfaces of the features in the first layer through the fourth layer. The exposed first layer material is removed to expose portions of the second layer through the fourth layer, and the second layer is further patterned using the fourth layer material as a mask.
Owner:MACRONIX INT CO LTD
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