1087 results about "Interface layer" patented technology

Disclosed herein are bonded structures and methods of forming the bonded structures. In some embodiments, the bonded structures include a first element having an inorganic dielectric surface, a second element having an organic dielectric surface, an interface layer between the first and second elements and bonded to the inorganic and organic dielectric surfaces. The method of forming the bonded structure includes providing the first and second elements, exposing the inorganic dielectric surface to a silane coupling agent to form the interface layer, contacting the organic dielectric surface to the interface layer, and heating the first element, second element, and interface layer to bond the first element to the second element.

The invention discloses a cross-platform equipment alarm information acquisition method, and particularly relates to the field of information acquisition, the method adapts to different platform equipment through a standardized interface layer, the interface layer comprises an equipment connection protocol library and a unified data conversion unit, and an original log of the equipment is analyzed in real time based on a preset alarm rule template; extracting key information and generating an alarm event object; converting the alarm key information into an alarm event in a unified format, and adding equipment identification metadata; alarm events are asynchronously transmitted to a central processing server by utilizing a high-reliability message queue, and the transmission reliability is guaranteed by adopting various mechanisms; performing duplicate removal, priority classification and persistent storage on the alarm events in the central server, and ensuring data consistency by adopting a hierarchical storage architecture; the whole processing link is provided with perfect monitoring indexes, and automatic capacity expansion and contraction are achieved.

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

Support structures are used in certain additive fabrication processes to permit fabrication of a greater range of object geometries. For additive fabrication processes with materials that are subsequently sintered into a final part, an interface layer is formed between the object and support in order to inhibit bonding between adjacent surfaces of the support structure and the object during sintering.

The invention discloses a silicon carbide power module packaging structure with low thermal resistance and low stress, and belongs to the technical field of semiconductor devices. The packaging structure comprises a metal substrate; the insulating ceramic layer is arranged on the metal substrate; the circuit layer is arranged on the insulating ceramic layer; the lower surface of the silicon carbide chip is connected with the circuit layer through a first interface layer; the composite heat dissipation stress buffer layer is arranged on the upper surface of the silicon carbide chip through a second interface layer; the copper clamp is connected with the upper surface of the composite heat dissipation stress buffer layer through a third interface layer; and the composite heat dissipation stress buffer layer is made of a copper-graphite composite material. According to the invention, the junction temperature of the silicon carbide chip can be greatly reduced, the overall thermal resistance is reduced, the surface stress of the chip is reduced, the warping phenomenon of the chip in the working process is effectively improved, and the long-life reliability of the power module under the long-term thermal cycle working condition is ensured.

The invention discloses a method for characterizing physical properties of a single-layer graphene / semiconductor heterojunction. The method comprises the following steps: providing a physical property model about a single-layer graphene-semiconductor heterojunction, wherein influence factors comprise the change of Fermi level of single-layer graphene after the heterojunction is formed and the influence of an interface state on a formation position of a contact potential difference; extracting heterojunction electrical characteristics by using a Kelvin probe force microscope; the interface layer spacing is obtained; and importing the heterojunction electrical characteristics and the interface interlayer spacing into a physical characteristic model, and analyzing to obtain physical characteristics. According to the new theoretical model and the method for realizing the nondestructive characterization of the physical characteristics of the heterojunction by using the Kelvin probe microscope based on the theoretical model, the influence of the change of the Fermi level of the single-layer graphene and the interface state on the formation position of the contact potential difference is fully considered; key interface physical properties, especially built-in potential and depletion region characteristics which are crucial to device performance, can be accurately analyzed.

The invention discloses a polyanion halide solid electrolyte material as well as a preparation method and application thereof. The chemical formula of the halide solid electrolyte material is Li < 3 > YCl < 6-2x > Br < x > I < x >, wherein 0 < x < 3. The chemical formula of the halide solid electrolyte material is Li < 3 > YCl < 5.8 > Br < 0.1 > I < 0.1 >, Li < 3 > YCl < 5.6 > Br < 0.2 > I < 0.2 >, Li < 3 > YCl < 5.4 > Br < 0.3 > I < 0.3 >, Li < 3 > YCl < 5.2 > Br < 0.4 > I < 0.4 >, Li < 3 > YCl < 5.0 > Br < 0.5 > I < 0.5 >, Li < 3 > YCl < 4.8 > Br < 0.6 > I < 0.6 >, Li < 3 > YCl < 4.6 > Br < 0.7 > I < 0.7 >, Li < 3 > YCl < 4.4 > Br < 0.8 > I < 0.8 >, Li < 3 > YCl < 4.2 > Br < 0.9 > I < 0.9 >, Li < 3 > YCl < 4.0 > The invention provides a series of Li3YCl6-2xBrxIx by taking economical and efficient Li3YCl6 as a main body and combining with an anion mixing strategy, the Li3YCl6-2xBrxIx has high ionic conductivity of 1.98 mS cm <-1 > and low activation energy of 0.257 eV, and has good compatibility with a Li4Ti5O12 (LTO) positive electrode and a Li-In alloy negative electrode. The construction of the anion mixed state not only can reduce the binding effect of an anion frame on Li < + > migration and improve the ionic conductivity, but also can soften anion crystal lattices and reduce the activation energy. More importantly, due to the introduction of I <->, a LiI self-limiting passivation interface layer is generated in situ, so that the stability of a Li interface is enhanced.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

In accordance with some embodiments of the present disclosure, a memory device is provided. The memory device may include a first electrode, a ferroelectric layer fabricated on the first electrode, and a second electrode fabricated on the ferroelectric layer. The ferroelectric layer includes a plurality of ferroelectric films and a plurality of interface layers stacked alternately. Each of the ferroelectric films comprises at least one ferroelectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2), scandium-doped aluminum nitride (Al1-xScxN), titanates (BaTiO3), niobates (LiNbO3), tantalates (NaTaO3), etc. Each of the interface layers comprises at least one dielectric material that is more chemically stable than the ferroelectric material, such as aluminum oxide.

The invention provides a running method based on a V8 high-performance small game running kernel and the running kernel. The running kernel comprises an API interface layer, a bridging layer and a native layer. The primary layer comprises a V8 kernel module, a C + + module and an Android module; the V8 kernel module is bound with a C + + module by adopting an object binding technology, and the V8 kernel module is associated with an API (Application Program Interface) of a corresponding type associated with the Android module through a JNI (Java Network Interface) mapping technology. The running method based on the V8 high-performance small game running kernel and the running kernel are achieved completely without depending on a browser WebView, have the advantages of being open, light, strong, efficient, smooth in running, smooth in rendering, high in starting speed, stable in running and the like, and meet the running requirement of a small game.

The invention discloses a preparation method of a composite micro-groove super-hydrophobic low-ice-adhesion photo-thermal film. The preparation method comprises the following steps: (1) constructing a low-elasticity-modulus photo-thermal composite sponge substrate through a solvothermal method; (2) uniformly coating the surface of a substrate with a polydimethylsiloxane (PDMS) precursor solution by adopting an aerosol-assisted deposition technology, and carrying out thermocuring to form a functional composite interface layer; and (3) constructing a multi-stage scallop surface-imitating micro-nano groove composite structure on the surface of the interface layer by using a femtosecond laser micro-nano processing technology. The prepared film has super-hydrophobicity, the surface of the film is in a Cassie-Baxter wetting state with a 164-degree contact angle and a 1-degree rolling angle, and the film has a surface self-cleaning function. Under the icing condition, the adhesion strength of an ice layer of the system is obviously reduced to 2.57 kPa, the static delay icing time is effectively prolonged to 1587 s, and the system has the photo-thermal response characteristic and can realize rapid icing ablation under the standard solar irradiance; the preparation method has the characteristics of high process controllability, environment friendliness and the like, and is suitable for large-scale continuous production.

The invention provides a sodium ferric phosphate pyrophosphate-based composite material as well as a preparation method and application thereof, and relates to the technical field of sodium ion battery electrode materials. The composite material is of a core-shell structure and sequentially comprises a base material, a heterogeneous interface layer and a coating layer from inside to outside, the chemical formula of the base material is Na4Fex( PO4) 2P2O7, the heterogeneous interface layer is iron-based phosphide nanoparticles distributed on the surface of the base material, and the coating layer is a carbon layer; the iron-based phosphide is prepared from at least one of FeP and Fe2P; 3 < = x < = 4; iron-based phosphide nanoparticles are generated on the surface of the ferric sodium phosphate pyrophosphate material through in-situ reduction, a tightly-combined heterogeneous interface network is formed, the electron and ion transmission performance of the material is remarkably improved, and the rate performance is improved; the preparation method is simple and easy to implement on a large scale.

The invention provides a diaphragm and a preparation method thereof, and a lithium ion battery, the diaphragm comprises a base membrane, a composite ceramic coating and an interface layer, the composite ceramic coating contains inorganic ceramic particles and organic microcapsule particles, the organic microcapsule particles comprise a core material with a melting point range of 55-65 DEG C and a polymer shell coating the surface of the core material, and the polymer shell is coated on the surface of the core material. The polymer shell is selected from at least one of polyurethane, polyurea, polyamide and polycarbonate, the interface layer is formed by depositing an interface modification polymer on the surface of the composite ceramic coating, and the interface modification polymer is selected from at least one of polycatechol derivatives, polyaniline, polyvinyl pyridine, polyacrylic acid and polyacrylamide. The core material in the organic microcapsule particles is melted when heated to trigger hole closing at the initial stage of thermal runaway at 60-80 DEG C, the hole closing rate can reach 92%, the hole closing response time is shortened by 30%, and the porous structure of the interface layer can enhance the liquid absorption rate.

The invention discloses a hierarchical abstraction method and system for computing resources, and relates to the technical field of resource abstraction. The hierarchical abstraction method for the computing resources comprises the following steps: constructing a three-level abstraction architecture system; wherein the three-level abstract architecture system comprises a service interface layer, an equipment function abstraction layer and a hardware adaptation layer; horizontal function decoupling is adopted in the equipment function abstraction layer, hardware operation is abstracted into a plurality of independent function modules, and each function module provides a unified abstraction interface for the service interface layer in a dynamic link library form; and defining a device description structural body in the device function abstraction layer. The invention solves the following technical problems in the existing service system: interface isomerism, non-uniform drive interface specifications of hardware platforms, and need to develop a special adaptive code for each hardware; the resource coupling degree is high, business logic and hardware operation codes are deeply coupled, and business layer codes need to be modified during hardware switching.

The invention discloses a composite interface layer, a preparation method thereof and an all-solid-state battery, belongs to the technical field of all-solid-state batteries, and solves the problems that the all-solid-state battery needs to operate under relatively high restraint pressure, and the battery performance is quickly reduced. The composite interface layer comprises a functional layer and a stress buffer layer, the functional layer comprises the following components in percentage by mass: 10%-50% of a ceramic fast lithium ion conductor, 20%-70% of an elastic polymer A and 0.1%-30% of a lithium salt A, the Poisson ratio of the functional layer is 0.01-0.3, and the Young modulus of the functional layer is 0.1-2 GPa; the stress buffer layer comprises the following components in percentage by mass: 65%-90% of an elastic polymer B, 1%-15% of a plasticizer and 0.1%-20% of lithium salt B, the Poisson ratio of the stress buffer layer is 0.2-0.5, and the Young modulus of the stress buffer layer is 0.01-0.5 GPa; and the elastic polymer B contains dynamic reversible chemical bonds.

The invention relates to a p-type niobium oxide dipole-based metal-oxide-semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor device manufacturing. According to the technical scheme, the MOS device is provided. A gate dielectric stack of the MOS device sequentially comprises an interface layer, a high-k dielectric layer and a p-type electric dipole layer containing niobium oxide from bottom to top. According to the preparation method, the dipole layer is deposited by adopting an atomic layer deposition process, and then atoms in the dipole layer are driven to be diffused to the interface of the high-k dielectric layer and the interface layer through high-temperature rapid annealing treatment so as to form effective electric dipoles. Compared with the prior art, the high dielectric constant characteristic is utilized, the threshold voltage can be positively regulated and controlled to a larger extent, meanwhile, the increase of EOT is remarkably inhibited, and good interface quality is kept.

The invention provides a software and hardware integrated intelligent terminal power transaction system and method, relates to the technical field of power market transaction, and solves the technical problems of data potential safety hazards and insufficient real-time performance caused by dependence on an external platform in a power transaction process in the prior art. The system specifically comprises a hardware architecture and a software function module, the hardware architecture comprises a processor, a redundant power supply, a storage device, a network interface, a security encryption chip and a display interface; the software function module comprises a core function layer, an interface layer and a security layer; wherein the core function layer is used for being responsible for processing and controlling the whole flow of power transaction; the interface layer is used for carrying out standardized and ordered external data interaction; and the security layer is used for guaranteeing the security of the terminal from multiple dimensions of communication, transaction, data and operation and maintenance. The method is used for electricity market transaction.

A hybrid bonding structure, a manufacturing method thereof, and a semiconductor device. The hybrid bonding structure includes a dielectric layer, including a first dielectric layer and a second dielectric layer which are bonded; a bonding interface layer between the first dielectric layer and the second dielectric layer; a metal structure in the dielectric layer; and a diffusion barrier layer in the dielectric layer, the diffusion barrier layer isolating the bonding interface layer. The hybrid bonding structure can improve device performance.

The embodiment of the invention provides a resistive random access memory device and a manufacturing method and an operation method thereof. The resistive random access memory device comprises a substrate structure and a memory stack structure, the storage stack structure is arranged on one side of the substrate structure and comprises a first electrode, a second electrode, a resistance change reaction layer and an interface layer, the resistance change reaction layer is located between the first electrode and the second electrode and is configured to be converted from a first resistance state to a second resistance state when a level higher than that of the first electrode is applied to the second electrode, and the interface layer is configured to be connected with the first resistance state. When a level higher than that of the second electrode is applied to the first electrode, the resistance change reaction layer is converted from the second resistance state to the first resistance state, and the resistance of the resistance change reaction layer in the first resistance state is higher than that in the second resistance state; the interface layer is located between the first electrode and the resistive reaction layer and serves as an oxygen diffusion barrier layer. By arranging the interface layer, the erasing resistance and the device performance of the resistive random access memory device can be improved.

A semiconductor device may include an active pattern on an active region of a substrate, a channel pattern on the active pattern and including first, second, and third semiconductor patterns that are stacked to be spaced apart from each other, a gate electrode on the channel pattern, and a gate dielectric layer between the channel pattern and the gate electrode. The gate dielectric layer may include an interface layer, and first, second, and third high-k dielectric layers that are sequentially stacked on the interface layer. The first high-k dielectric layer may include a first dipole element, and the second high-k dielectric layer may include a second dipole element.

The invention belongs to the technical field of energy storage devices, and particularly relates to a high-pressure and high-temperature resistant battery diaphragm, a battery and a preparation method thereof. The diaphragm comprises a base membrane and a functional coating coated on at least one side of the base membrane, the coating comprises a bonding layer, a reinforcing layer and an interface layer which are sequentially distributed, the reinforcing layer comprises a two-dimensional vermiculite nanosheet, the transverse size of the two-dimensional vermiculite nanosheet is 0.5-10 microns, and the thickness of the two-dimensional vermiculite nanosheet is 1-5 nm, so that the thickness of the two-dimensional vermiculite nanosheet is 1-5 nm. Through the two-dimensional vermiculite nanosheets, the puncture strength of the strengthened layer is improved by 140%, and zero deformation is achieved under the pressure of 10 MPa; the strengthening layer blocks heat conduction, and the shrinking percentage at 250 DEG C is smaller than 5%; the contact angle of the electrolyte is reduced to 8 degrees by the interface layer, so that the ion mobility is improved; the cost of the vermiculite ore raw material is only 1 / 5 of that of aluminum oxide.

The invention provides a solid-state battery and a preparation method thereof, a battery device, a power utilization device and an energy storage device, the solid-state battery comprises a positive electrode, a negative electrode, an electrolyte and an interface layer, and the interface layer comprises the following components in percentage by mass: 50wt%-70wt% of light-cured resin, 10wt%-20wt% of an inorganic nano filler, 15wt%-25wt% of an ionic conductor material, 0.1 wt%-6wt% of an additive and 1wt%-2wt% of a photoinitiator; the additive comprises scandium salt and tin salt, and the molar ratio of the scandium salt to the tin salt is 1: (1.2-1.8); in the interface layer, the inorganic nanofiller is of a core-shell structure, the inorganic nanofiller comprises a plurality of ionic conductive ceramics parallel to one another and an iron-containing magnetic substance located on at least part of the surface of the ionic conductive ceramics, the ionic conductive ceramics are of a rod-shaped structure, and the included angle between the inorganic nanofiller and the surface where the negative electrode is located is 60-120 degrees.

The invention belongs to the technical field of photovoltaic solar materials, and discloses a method for modifying a calcium iron ore solar cell by a small molecule buried interface, which is used for solving the problems of low photoelectric conversion efficiency and poor stability of a perovskite solar cell. Halogenated monothiadiazole or halogenated polythiadiazole molecules are used as a buried interface layer and are led between the hole transport layer and the perovskite layer. The interface layer generates uniform film covering on the hole transport layer, so that non-covalent bond interaction is formed, and spreading and expansion of a perovskite precursor solution are facilitated. N atoms in the BSC and the BFS are combined with Pb < 2 + > to passivate the bottom surface defect of the perovskite, and F atoms in the BFS can form hydrogen bonds with FAI, so that the electronic performance of the perovskite thin film is influenced. Due to good film quality and interface contact, non-radiative recombination between interfaces is effectively inhibited, carrier transport of the device is improved, and therefore the efficiency and stability of the perovskite solar cell device are enhanced.

The invention discloses an Internet of Things equipment access authentication method and system based on edge computing. The method comprises the following steps: equipment sends an access request, and an edge node analyzes a protocol to generate a feature fingerprint; the cloud executes first-level protocol white list verification and second-level certificate and feature fingerprint verification, matches an authentication strategy according to environmental parameters and issues a token; the edge node executes localized authentication, monitors the state in real time and dynamically adjusts the strategy; and after the authentication is passed, synchronizing information to the cloud to complete registration. The system comprises an equipment access layer, an edge computing layer, an authentication management layer and an interactive interface layer, the edge layer analyzes protocols such as DALI and BACnet, and the management layer constructs a three-dimensional strategy mapping table and supports graphical configuration and machine learning optimization strategy libraries. According to the Internet of Things equipment access authentication method and system based on edge computing, low-delay and high-flexibility access of multi-protocol equipment is achieved, the real-time performance, expansibility and safety are improved, and the method and system are suitable for intelligent buildings, industrial Internet of Things and other scenes.

The invention relates to an epitaxial growth method of a gallium oxide material, a gallium oxide epitaxial structure and an ultraviolet detector. The epitaxial growth method of the gallium oxide material comprises the following steps: providing a substrate; forming an aluminum nitride layer on the substrate; epitaxially growing at least one composite interface layer on the aluminum nitride layer, wherein the composite interface layer comprises an aluminum oxide layer and an indium oxide layer which are stacked in sequence; and epitaxially growing a gallium oxide layer on the composite interface layer. Therefore, the dislocation density and thermal stress in the gallium oxide layer can be reduced, and the quality and performance of the gallium oxide epitaxial structure can be improved. When the prepared gallium oxide epitaxial structure is applied to a photoelectric detector, the performance and the reliability of the device can be remarkably improved.

The invention discloses a verification platform, method, device and equipment based on a UVM. The verification platform comprises a function main body sequencer which is realized through an expansion interface sequencer, an input agent which is used for driving an input port of a DUT, a function main body packer which is used for converting an interface data packet format into a function main body data packet format, and an interface output agent which is used for monitoring a response signal of an output port of the DUT, the function main body reference model is used for outputting an expected function main body data packet by the function main body data packet; and the function main body comparison scoreboard is used for comparing the expected function main body data packet with the actual function data packet to generate a verification result. According to the verification platform, decoupling between the verification content of the function body and the interface function is realized; only the interface verification component needs to be replaced when a protocol is changed, and the high-level function component does not need to be modified; and when the function module is newly added, the existing interface layer can be directly reused, so that the verification efficiency and the reusability of the verification component are improved.

The invention provides a dynamic adaptation method and system for a multi-mode power supply compatible charging pile system, and the method comprises the steps: building a multi-protocol physical layer compatible connection between a charging pile and a power supply module through a multi-communication interface layer, and receiving a data frame inputted by the charging pile; analyzing a baud rate, a check bit and an instruction set of the data frame, and identifying a charging pile protocol type and a power module protocol type; querying a matching mapping relationship between the charging pile protocol type and the power supply module protocol type in the dynamic adaptation matrix; if the matching mapping relation exists, data field conversion is executed, and a target protocol frame is generated; and if the matching mapping relation does not exist, starting a machine learning process, creating a temporary mapping rule, and effectively solving the problems of poor compatibility and high manual configuration cost of the charging pile and the power supply module in a traditional protocol mode through the modes of protocol analysis, intelligent matching and dynamic learning.

The invention discloses a photosensitive pixel unit and an image sensor. The photosensitive pixel unit comprises a semiconductor substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the N-type semiconductor layer is positioned above the dielectric layer, is in ohmic contact with the signal reading electrode through the opening part, and sequentially comprises a nanocrystalline particle layer, a metal oxide semiconductor thin film layer and an interface layer which is arranged between the nanocrystalline particle layer and the metal oxide semiconductor thin film layer and has two-dimensional electron gas characteristics from bottom to top; the photoelectric conversion layer is located above the N-type semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

The invention discloses a flame-retardant PC (polycarbonate) composite material based on high-temperature interface crosslinking and an in-situ reinforcement process thereof. The composite material comprises polycarbonate resin, reinforced fibers with a thermal response interface, a flame-retardant synergist and a processing aid. The core is that a thermal response interface layer and a sacrificial protection layer are sequentially constructed on the surface of the reinforced fiber, the thermal response interface layer is formed by grafting a silane coupling agent containing peroxide bonds through covalent bonds, and the sacrificial protection layer is a low-melting-point coating material. According to the design, the material has the temperature-triggered intelligent response characteristic; in daily processing and use, the protective layer ensures that an interface is stable and the binding force is slowly repaired; under the condition of high-temperature fire, the interface layer is quickly triggered to form carbon through crosslinking, so that the flame-retardant efficiency is remarkably improved, and melt dripping and a candlewick effect are effectively inhibited. The high mechanical strength, the long-acting durability and the intrinsic flame-retardant safety of the material are synchronously realized, and the material is suitable for the high-requirement fields of electronic appliances, new energy automobiles and the like.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.