1345 results about "Interface layer" patented technology

Disclosed herein are bonded structures and methods of forming the bonded structures. In some embodiments, the bonded structures include a first element having an inorganic dielectric surface, a second element having an organic dielectric surface, an interface layer between the first and second elements and bonded to the inorganic and organic dielectric surfaces. The method of forming the bonded structure includes providing the first and second elements, exposing the inorganic dielectric surface to a silane coupling agent to form the interface layer, contacting the organic dielectric surface to the interface layer, and heating the first element, second element, and interface layer to bond the first element to the second element.

The invention discloses a self-assembled monomolecular layer material with an asymmetric intermediate core and a preparation method and application thereof, and belongs to the field of solar cells. The self-assembled monomolecular layer material is formed by combining an asymmetric intermediate core with anchoring groups such as phosphonic acid and sulfonic acid, has good hydrophobicity and high light transmittance, can be used as a hole transport layer material, and is used for preparing organic solar cells and perovskite solar cells with p-i-n structures, the organic solar cell achieves the maximum energy conversion efficiency of 18.9%, shows excellent environmental stability, still keeps 95% or above of the initial performance after being stored in air for 480 h, and is far superior to a traditional device based on a PEDOT: PSS interface layer. By designing and developing a series of self-assembled monomolecular layer materials with asymmetric intermediate cores, the energy conversion efficiency and environmental stability of the solar cell can be remarkably improved.

The invention discloses a cross-platform equipment alarm information acquisition method, and particularly relates to the field of information acquisition, the method adapts to different platform equipment through a standardized interface layer, the interface layer comprises an equipment connection protocol library and a unified data conversion unit, and an original log of the equipment is analyzed in real time based on a preset alarm rule template; extracting key information and generating an alarm event object; converting the alarm key information into an alarm event in a unified format, and adding equipment identification metadata; alarm events are asynchronously transmitted to a central processing server by utilizing a high-reliability message queue, and the transmission reliability is guaranteed by adopting various mechanisms; performing duplicate removal, priority classification and persistent storage on the alarm events in the central server, and ensuring data consistency by adopting a hierarchical storage architecture; the whole processing link is provided with perfect monitoring indexes, and automatic capacity expansion and contraction are achieved.

To provide a multilayer electronic component having excellent reliability by preventing penetration of external moisture or plating solution.SOLUTION: According to one embodiment of the present invention, there is provided a multilayer electronic component which includes: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; an external electrode including a base electrode layer connected to the internal electrode; and an interface layer disposed between an end of the dielectric layer and the base electrode layer. The interface layer includes a first glass containing Ba, Zn, and Si, and the base electrode layer includes a second glass containing Ba and Si. When an average molar ratio (Ba / Si) of Ba to Si contained in the first glass is M1 and an average molar ratio (Ba / Si) of Ba to Si contained in the second glass is M2, M1 and M2 satisfy M1 / M2≥1.5.SELECTED DRAWING: Figure 5

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

The invention relates to the technical field of photoelectricity, and discloses a full-spectrum LED epitaxial wafer, a preparation method thereof and an LED chip, the epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, an N-type GaN layer, a multispectral light-emitting well layer and a P-type GaN layer; the multispectral light-emitting well layer comprises a first light-emitting well layer, a second light-emitting well layer and a third light-emitting well layer which are stacked in sequence, the first light-emitting well layer comprises a plurality of groups of InxGa (1-x) N quantum well layers, AlaGa (1-a) N interface layers and first GaN quantum barrier layers which are stacked in sequence, the second light-emitting well layer comprises a plurality of groups of InyGa (1-y) N quantum well layers, AlbGa (1-b) N interface layers and second GaN quantum barrier layers which are stacked in sequence, and the third light-emitting well layer comprises a plurality of groups of InzGa (1-z) N quantum well layers, AlcGa (1-c) N interface layers and third GaN quantum barrier layers which are stacked in sequence. According to the full-spectrum LED epitaxial wafer provided by the invention, the luminous efficiency and the color rendering index of a full-spectrum chip can be improved.

The invention belongs to the technical field of semiconductor devices, and discloses a novel semiconductor nonvolatile memory and a preparation method and application thereof. The memory comprises a substrate, a bottom electrode, an amorphous oxide interface layer, a ferroelectric dielectric layer and a top electrode which are sequentially arranged from bottom to top, the preparation method comprises the steps of (1) cleaning the substrate, (2) depositing the bottom electrode, (3) forming the amorphous oxide interface layer, (4) depositing the ferroelectric medium layer, and forming the ultrathin ferroelectric medium layer with uniform composition and good ferroelectricity on the amorphous MoO3 interface layer, (5) patterning and depositing the top electrode, and (6) performing rapid thermal annealing treatment. The memory is applied to a three-dimensional stacked nonvolatile memory array or construction of a back gate type ferroelectric transistor structure. According to the invention, the formation of a non-ferroelectric phase is effectively inhibited, the preferred orientation arrangement of the ferroelectric phase is promoted, the polarization intensity is enhanced, and the ferroelectric performance of the device is improved. The material has the advantages of low thermal budget, high process compatibility and excellent ferroelectric performance.

The invention provides a 3C-SiC composite epitaxial structure and device structure based on 4H-SiC, and the composite epitaxial structure comprises a 4H-SiC substrate, an N-type doped epitaxial layer, a P-type doped buried layer, a carrier tunneling region, and a 3C-SiC epitaxial layer. The N-type doped epitaxial layer is arranged on the 4H-SiC substrate; the 3C-SiC epitaxial layer is subjected to secondary epitaxy or bonded on the surface of the N-type doped epitaxial layer; a carrier tunneling region is formed on a contact interface layer of the 3C-SiC epitaxial layer and the N-type doped epitaxial layer; and the P-type doped buried layer ions are implanted into the upper region of the N-type doped epitaxial layer. The structure can effectively solve the problems that in the prior art, when 4H-SiC serves as a substrate to prepare a SiC-MOS device, improvement of interface state density and channel electron mobility is limited, the conduction capacity of the device is poor, and the electrical performance and the long-term reliability are poor. The composite epitaxial structure and the device structure are high in device conduction capability and good in electrical performance and long-term reliability.

The invention relates to the technical field of additive and subtractive manufacturing, in particular to a full-laser additive and subtractive composite manufacturing method and a full-laser additive and subtractive composite manufacturing device, and according to the method, a current layer is machined by switching pulse laser and continuous laser, and additive and subtractive treatment is conducted on the current layer. According to the additive and subtractive treatment, the distribution of an interface morphology material and an internal structure of a current layer can be changed, and a formed interface layer can regulate and control the flowing state and the internal stress of a molten pool in the subsequent additive process, so that the effects of inducing and refining structure growth are achieved; according to the method, forming of a more precise fine structure can be achieved through cooperation of layer-by-layer material increasing and material decreasing, continuous laser and pulse laser are compositely utilized in the method, the manufacturing precision, the surface quality and the internal quality of an additive manufacturing part can be effectively improved, and the part has the advantage of being good in mechanical property. The device comprises an optical system, the optical system comprises a pulse laser module and a continuous laser module, and the pulse laser module and the continuous laser module are arranged to operate independently or simultaneously.

An interface structure characterization method, comprising: constructing a solid-liquid equilibrium system; acquiring interfacial atomic number density distribution of the solid-liquid equilibrium system; and acquiring interface layers on the basis of the interfacial atomic number density distribution. Compared with previous qualitative characterization methods, characterization parameters of interface structure changes are developed on the basis of computation results of radial distribution functions in interface layers, and the parameters can quantitatively characterize the change characteristics of the interface structure, avoiding the situation where the interface structure can only be qualitatively characterized; the present application can be used for quantitatively characterizing interface structures, can characterize differences in interface structures caused by lattice periodic fields when crystals of different orientations come into contact with melts, structural adjustments needed from melts to crystal melts, and change processes from melts to crystal structures (sudden or gradual changes).

The invention provides a mixed bonding surface planarization process method of a wafer and chemical mechanical polishing equipment. The method comprises the following steps: controlling a grinding head to adsorb a first wafer to be subjected to surface planarization treatment, and grinding the first wafer on a first grinding pad to remove a copper film above a groove of the first wafer so as to obtain a second wafer; controlling the grinding head to move to a second grinding pad, and grinding the second wafer on the second grinding pad so as to remove the dielectric layer of the second wafer, the barrier layer above the dielectric layer and copper with the same thickness as the dielectric layer in the groove, and obtaining a third wafer with an exposed interface layer; controlling the grinding head to move to a third grinding pad, and grinding the third wafer on the third grinding pad, so that the surface height of the interface layer is the same as the surface height of the copper in the groove, and obtaining the wafer with the flattened surface; wherein the hardness of the third polishing pad is smaller than the hardness of the first polishing pad and the hardness of the second polishing pad. According to the invention, the wafer with a flat and smooth surface can be obtained.

The invention provides a high-strength low-stress continuous SiC fiber reinforced Ti3Al composite material as well as a preparation method and application thereof, and belongs to the technical field of aeronautical materials. The Mo interface layer with the thermal expansion coefficient matched with that of SiC and Ti3Al is introduced to the interface of the SiC / Ti3Al composite material, so that the stable transition of the thermal expansion coefficient is realized, the interface stress is dispersed, the interface bonding strength is further improved, and the stability of the material performance is guaranteed; meanwhile, an Nb element is introduced into a Ti3Al matrix to refine Ti3Al grains and optimize a microstructure, so that the strength and toughness of the material are enhanced, and a Ti3Al / Nb composite structure is constructed to relieve stress concentration and improve the tensile strength, so that the material failure is effectively prevented.

Support structures are used in certain additive fabrication processes to permit fabrication of a greater range of object geometries. For additive fabrication processes with materials that are subsequently sintered into a final part, an interface layer is formed between the object and support in order to inhibit bonding between adjacent surfaces of the support structure and the object during sintering.

The invention relates to a preparation method and application of an organic-inorganic artificial composite solid electrolyte interface layer, and belongs to the technical field of lithium metal batteries. The organic polymer, the black phosphorene, the conductive carbon black and other inorganic substances are uniformly mixed to construct the organic-inorganic artificial composite interface layer, and the organic-inorganic artificial composite interface layer can induce uniform lithium deposition, reduce the local current density caused by nonuniformity and roughness of the surface of the copper current collector, reduce the lithium nucleation barrier, and improve the lithium ion battery performance. Meanwhile, the affinity of deposited lithium and a current collector is enhanced, the interface impedance of the negative-electrode-free lithium metal battery is remarkably reduced, and the lithium dendrite growth of a lithium metal negative electrode is inhibited; the cathode-free lithium metal battery assembled by adopting the copper current collector modified by the organic-inorganic artificial composite interface layer shows long cycle stability, good rate capability and remarkable safety performance, and has a wide commercial application prospect.

Disclosed is a wearable device. The wearable device includes a substrate layer. The substrate layer is configured to support a battery array comprising a plurality of battery cells, wherein least a first battery cell is electrically coupled to a second battery cell using a conductive interconnect. The wearable device also includes an interface layer coupled to the substrate layer. The interface layer is electrically coupled the battery array via a translayer interconnect. The interface configured to adhere the substrate to a body and to provide electrical stimulation to the body.

The invention discloses a silicon carbide power module packaging structure with low thermal resistance and low stress, and belongs to the technical field of semiconductor devices. The packaging structure comprises a metal substrate; the insulating ceramic layer is arranged on the metal substrate; the circuit layer is arranged on the insulating ceramic layer; the lower surface of the silicon carbide chip is connected with the circuit layer through a first interface layer; the composite heat dissipation stress buffer layer is arranged on the upper surface of the silicon carbide chip through a second interface layer; the copper clamp is connected with the upper surface of the composite heat dissipation stress buffer layer through a third interface layer; and the composite heat dissipation stress buffer layer is made of a copper-graphite composite material. According to the invention, the junction temperature of the silicon carbide chip can be greatly reduced, the overall thermal resistance is reduced, the surface stress of the chip is reduced, the warping phenomenon of the chip in the working process is effectively improved, and the long-life reliability of the power module under the long-term thermal cycle working condition is ensured.

The invention discloses a method for characterizing physical properties of a single-layer graphene / semiconductor heterojunction. The method comprises the following steps: providing a physical property model about a single-layer graphene-semiconductor heterojunction, wherein influence factors comprise the change of Fermi level of single-layer graphene after the heterojunction is formed and the influence of an interface state on a formation position of a contact potential difference; extracting heterojunction electrical characteristics by using a Kelvin probe force microscope; the interface layer spacing is obtained; and importing the heterojunction electrical characteristics and the interface interlayer spacing into a physical characteristic model, and analyzing to obtain physical characteristics. According to the new theoretical model and the method for realizing the nondestructive characterization of the physical characteristics of the heterojunction by using the Kelvin probe microscope based on the theoretical model, the influence of the change of the Fermi level of the single-layer graphene and the interface state on the formation position of the contact potential difference is fully considered; key interface physical properties, especially built-in potential and depletion region characteristics which are crucial to device performance, can be accurately analyzed.

The invention discloses a polyanion halide solid electrolyte material as well as a preparation method and application thereof. The chemical formula of the halide solid electrolyte material is Li < 3 > YCl < 6-2x > Br < x > I < x >, wherein 0 < x < 3. The chemical formula of the halide solid electrolyte material is Li < 3 > YCl < 5.8 > Br < 0.1 > I < 0.1 >, Li < 3 > YCl < 5.6 > Br < 0.2 > I < 0.2 >, Li < 3 > YCl < 5.4 > Br < 0.3 > I < 0.3 >, Li < 3 > YCl < 5.2 > Br < 0.4 > I < 0.4 >, Li < 3 > YCl < 5.0 > Br < 0.5 > I < 0.5 >, Li < 3 > YCl < 4.8 > Br < 0.6 > I < 0.6 >, Li < 3 > YCl < 4.6 > Br < 0.7 > I < 0.7 >, Li < 3 > YCl < 4.4 > Br < 0.8 > I < 0.8 >, Li < 3 > YCl < 4.2 > Br < 0.9 > I < 0.9 >, Li < 3 > YCl < 4.0 > The invention provides a series of Li3YCl6-2xBrxIx by taking economical and efficient Li3YCl6 as a main body and combining with an anion mixing strategy, the Li3YCl6-2xBrxIx has high ionic conductivity of 1.98 mS cm <-1 > and low activation energy of 0.257 eV, and has good compatibility with a Li4Ti5O12 (LTO) positive electrode and a Li-In alloy negative electrode. The construction of the anion mixed state not only can reduce the binding effect of an anion frame on Li < + > migration and improve the ionic conductivity, but also can soften anion crystal lattices and reduce the activation energy. More importantly, due to the introduction of I <->, a LiI self-limiting passivation interface layer is generated in situ, so that the stability of a Li interface is enhanced.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

In accordance with some embodiments of the present disclosure, a memory device is provided. The memory device may include a first electrode, a ferroelectric layer fabricated on the first electrode, and a second electrode fabricated on the ferroelectric layer. The ferroelectric layer includes a plurality of ferroelectric films and a plurality of interface layers stacked alternately. Each of the ferroelectric films comprises at least one ferroelectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2), scandium-doped aluminum nitride (Al1-xScxN), titanates (BaTiO3), niobates (LiNbO3), tantalates (NaTaO3), etc. Each of the interface layers comprises at least one dielectric material that is more chemically stable than the ferroelectric material, such as aluminum oxide.

The invention discloses an alloy interface layer for a solid-state sodium-ion battery and a preparation method and application of the alloy interface layer. By means of a vacuum thermal evaporation method, a nano Bi artificial interface layer is constructed on the surface of solid electrolyte Na3Zr2Si2PO12, the most appropriate film thickness is found through experimental comparison to serve as an intermediate layer precursor, and on the basis, a Na negative electrode directly covers a plating layer to generate a corresponding nano-scale Na-Bi alloy intermediate layer in situ. The method is easy and convenient to operate and wide in application, has very high universality, can freely control the film forming rate and thickness, is wide in material selection range, and provides a wider idea for subsequent Na3Zr2Si2PO12 negative electrode interface modification.

A layered thermite composite includes alternating layers of metal oxide and reducing metal deposited upon a substrate. A fuzzy interface layer between each metal oxide layer and reducing metal layer includes reducing metal, reducing metal oxide, and metal oxide at least partially intermixed therein. The fuzzy interface layer forms while moving between chambers in a multi-chamber deposition process which minimizes exposure of the reducing metal to oxygen while moving between chambers. The fuzzy interface layer is not expected to grow in thickness after deposition. The combination of the relative thinness of the fuzzy interface layer as well as the presence of reactants as well as reducing metal oxide maintains the sensitivity of the layered thermit structure to mechanical ignition if the structure is used within a primer.

Support structures are used in certain additive fabrication processes to permit fabrication of a greater range of object geometries. For additive fabrication processes with materials that are subsequently sintered into a final part, an interface layer is formed between the object and support in order to inhibit bonding between adjacent surfaces of the support structure and the object during sintering.

The invention provides a running method based on a V8 high-performance small game running kernel and the running kernel. The running kernel comprises an API interface layer, a bridging layer and a native layer. The primary layer comprises a V8 kernel module, a C + + module and an Android module; the V8 kernel module is bound with a C + + module by adopting an object binding technology, and the V8 kernel module is associated with an API (Application Program Interface) of a corresponding type associated with the Android module through a JNI (Java Network Interface) mapping technology. The running method based on the V8 high-performance small game running kernel and the running kernel are achieved completely without depending on a browser WebView, have the advantages of being open, light, strong, efficient, smooth in running, smooth in rendering, high in starting speed, stable in running and the like, and meet the running requirement of a small game.

The invention relates to the technical field of photovoltaic cell preparation, and discloses a preparation process of a lower coated perovskite layer, and the process comprises the steps: obtaining a state effective value of an FTO glass film surface before the preparation of a lower interface layer, the preparation of a perovskite layer and the preparation of an upper interface layer; if the state effective value of the FTO glass film surface meets the preset requirement, carrying out a subsequent process for preparing a lower coated perovskite layer; the subsequent process comprises the steps of C60 layer evaporation, SnO2 layer preparation, P2 lineation, back electrode layer preparation, P3 lineation and edge cleaning. If the state effective value of the FTO glass film surface does not meet the preset requirement, carrying out circulating treatment on a preorder process for preparing the lower coated perovskite layer; the preorder process comprises the steps of glass cleaning, hole transport layer preparation, P1 scribing and Mark point scribing; wherein the preparation of the lower interface layer, the preparation of the perovskite layer and the preparation of the upper interface layer are carried out by adopting lower coating film preparation equipment, so that the yield of the preparation of the lower coating film perovskite layer is effectively ensured.

The invention discloses a preparation method of a composite micro-groove super-hydrophobic low-ice-adhesion photo-thermal film. The preparation method comprises the following steps: (1) constructing a low-elasticity-modulus photo-thermal composite sponge substrate through a solvothermal method; (2) uniformly coating the surface of a substrate with a polydimethylsiloxane (PDMS) precursor solution by adopting an aerosol-assisted deposition technology, and carrying out thermocuring to form a functional composite interface layer; and (3) constructing a multi-stage scallop surface-imitating micro-nano groove composite structure on the surface of the interface layer by using a femtosecond laser micro-nano processing technology. The prepared film has super-hydrophobicity, the surface of the film is in a Cassie-Baxter wetting state with a 164-degree contact angle and a 1-degree rolling angle, and the film has a surface self-cleaning function. Under the icing condition, the adhesion strength of an ice layer of the system is obviously reduced to 2.57 kPa, the static delay icing time is effectively prolonged to 1587 s, and the system has the photo-thermal response characteristic and can realize rapid icing ablation under the standard solar irradiance; the preparation method has the characteristics of high process controllability, environment friendliness and the like, and is suitable for large-scale continuous production.

The invention discloses a high-safety solid-state lithium metal battery which comprises a negative electrode, a solid-state electrolyte and a positive electrode and further comprises a heterogeneous interface layer located between the negative electrode and the solid-state electrolyte, and the heterogeneous interface layer is of a double-layer composite structure composed of a passivation layer and a polymer / semiconductor. The passivation layer is at least one of a nitride layer, an oxide layer, a nitrogen chemical layer, a carbon-based layer, a phosphate layer, a fluoride layer and a metal-based protection layer. The heterogeneous interface layer is introduced between the lithium metal negative electrode and the solid electrolyte, so that the physical contact between the lithium metal negative electrode and the solid electrolyte can be effectively improved, the growth of lithium dendrites can be prevented, the interface reaction between the lithium metal and the solid electrolyte can be reduced, and the problem of fire and combustion caused by thermal runaway at high temperature can be effectively inhibited; and the stability, safety and cycle performance of the solid-state lithium metal battery at room temperature and high temperature are enhanced.

The invention provides a sodium ferric phosphate pyrophosphate-based composite material as well as a preparation method and application thereof, and relates to the technical field of sodium ion battery electrode materials. The composite material is of a core-shell structure and sequentially comprises a base material, a heterogeneous interface layer and a coating layer from inside to outside, the chemical formula of the base material is Na4Fex( PO4) 2P2O7, the heterogeneous interface layer is iron-based phosphide nanoparticles distributed on the surface of the base material, and the coating layer is a carbon layer; the iron-based phosphide is prepared from at least one of FeP and Fe2P; 3 < = x < = 4; iron-based phosphide nanoparticles are generated on the surface of the ferric sodium phosphate pyrophosphate material through in-situ reduction, a tightly-combined heterogeneous interface network is formed, the electron and ion transmission performance of the material is remarkably improved, and the rate performance is improved; the preparation method is simple and easy to implement on a large scale.

The invention provides a diaphragm and a preparation method thereof, and a lithium ion battery, the diaphragm comprises a base membrane, a composite ceramic coating and an interface layer, the composite ceramic coating contains inorganic ceramic particles and organic microcapsule particles, the organic microcapsule particles comprise a core material with a melting point range of 55-65 DEG C and a polymer shell coating the surface of the core material, and the polymer shell is coated on the surface of the core material. The polymer shell is selected from at least one of polyurethane, polyurea, polyamide and polycarbonate, the interface layer is formed by depositing an interface modification polymer on the surface of the composite ceramic coating, and the interface modification polymer is selected from at least one of polycatechol derivatives, polyaniline, polyvinyl pyridine, polyacrylic acid and polyacrylamide. The core material in the organic microcapsule particles is melted when heated to trigger hole closing at the initial stage of thermal runaway at 60-80 DEG C, the hole closing rate can reach 92%, the hole closing response time is shortened by 30%, and the porous structure of the interface layer can enhance the liquid absorption rate.

The invention discloses a preparation method of an intrinsic passivation structure, the intrinsic passivation structure and a battery, the intrinsic passivation structure comprises a base layer, the surface of which is provided with a first interface layer; the first intrinsic layer is arranged on the first interface layer, and a second interface layer is arranged on the surface of the first intrinsic layer; the second intrinsic layer is arranged on the second interface layer, and a third interface layer is arranged on the surface of the second intrinsic layer; and the doped microcrystalline silicon layer is arranged on the surface of the third interface layer. According to the invention, the surfaces of the base layer, the first intrinsic layer and the second intrinsic layer are treated, so that the contact between the intrinsic amorphous silicon and the crystalline silicon substrate is effectively improved, the generation of nano twin crystals is inhibited, the passivation effect is enhanced, and the minority carrier lifetime is prolonged.