79 results about "Virtual Processor" patented technology

In communication with components of a cloud platform, namely a software-defined network constructed to overlay at least one public cloud network, a controller features a virtual processor and a data store. The data store includes network address translation (NAT) processing logic configured to determine whether a control plane message from tenant resources is associated with a network address overlapping condition, which represents a first network address included in the control plane message overlaps a network address range relied upon by either (a) at least one of the components of the cloud platform or (b) a component associated with other tenant resources. The NAT processing logic is further configured to alter routing data stores that maintain routing information for each of the components of the cloud platform to substitute the first network address with a first virtual network address for subsequent data message routing.

The invention relates to a discrete device batch test system and test method based on cascade control. The test system comprises a test end, a tested end, an automatic test module, a communication end and an industrial personal computer. A virtual processor is introduced into the test end, and a test mode is changed from a manual mode to an automatic mode; establishing a relay cascade test circuit with a cascade control function to realize rapid switching between devices to be tested; test frequencies of a test end and a tested end are synchronized by using a communication protocol, so that issuing of a test instruction and switching of a to-be-tested device can be always carried out orderly; the modular, batch and automatic testing of discrete devices can be realized, the testing efficiency is effectively improved, and the economic benefit is improved.

The invention relates to the technical field of computer security, in particular to a security isolation management system based on virtualization, which comprises a virtual machine intrusion behavior monitoring module, a Hypervisor monitoring system call frequency and a network connection request of a target virtual machine, and obtaining an intrusion behavior feature matching event. According to the method, the system calling frequency and the network connection request are monitored in real time when the target virtual machine runs, the intrusion behavior characteristics are captured, the targeted alarm instruction is generated, the memory of the target virtual machine is subjected to copy-on-write snapshot when the threat behavior is triggered, and the memory state at the intrusion moment is completely stored; establishing a new virtual processor context, and dynamically redirecting a network socket associated with an attack session to realize immediate isolation and transparent shunting of intrusion behaviors; and further, taking the data entering the memory as a taint source starting point, and tracking a flow path of a data taint among a register, a memory address and a process file handle.

The embodiment of the invention discloses a task processing method and device based on a virtual processor, a medium and equipment, and the method comprises the steps: generating an interrupt request signal by a virtual timer under the condition that a physical processor corresponding to a virtual machine is in a first mode; the physical processor obtains the interrupt request signal and injects virtual interrupt information corresponding to the interrupt request signal into a virtual processor corresponding to the virtual machine; the virtual processor responds to the virtual interrupt information and executes a processing task corresponding to the virtual interrupt information, and the virtual processor represents processor resources distributed for the virtual machine in the physical processor. According to the embodiment of the invention, the performance overhead generated by storing and recovering the context information of the system timer can be avoided or reduced.

A direct mode is provided for virtualization to enable simultaneous operation of different operating systems. A compatibility layer operates as a translator between instructions for the kernel of the host operating system running on device hardware and a guest operating system running in a virtual machine. A single layer of scheduling is employed via a host scheduler to support more optimal scheduling for the guest code. This approach supports running unmodified applications for the guest OS in the virtual machine. Memory management streamlines file write operations in which write operation parameters are mapped directly between one or more threads and virtual processors executing them. The direct mode for virtualization also enables streamlining message passing. It can also enable enhanced security between processes from different operating systems.

The embodiment of the invention relates to the technical field of quantum computing and quantum processor resource management, and provides a neutral atom quantum processor virtualization scheduling method based on a capability block, which comprises the following steps: receiving and analyzing a quantum algorithm task, and extracting a structural feature set; converting the structural feature set into an algorithm capability portrait based on a feature and capability mapping rule; obtaining a capability block resource pool comprising a plurality of capability blocks and block capability portraits thereof; carrying out capability matching on the algorithm capability portrait and the block capability portrait, and judging a coverage relation; determining a candidate capability block based on the coverage relationship and performing feasibility judgment; performing cross-region combination search on the candidate capability block set to construct a candidate block combination; performing cost evaluation on each candidate block combination; and selecting a target block combination based on the combination cost, constructing a virtual processor description object and outputting the virtual processor description object to an execution layer. Therefore, implementation and expandability of a complex quantum algorithm on a large-scale neutral atom quantum processor are realized.

The embodiment of the invention provides a physical machine processor scheduling method, device, system, product and storage medium, the physical machine comprises a physical processor, the physical processor corresponds to a scheduling queue, the method comprises the following steps: switching a running host machine operating system from a root mode to a virtualization mode, and in the virtualization mode, the host machine operating system is switched to a virtual mode; creating at least one virtual processor; generating a scheduling object and adding the scheduling object to a scheduling queue of the physical processor; and in a process of selecting a running task for the physical processor based on the scheduling queue of the physical processor, if the scheduling object is selected, selecting a target virtual processor from the at least one virtual processor, and scheduling the physical processor to run the target virtual processor.

The embodiment of the application provides a kind of bus controller's verification device, method and system.The verification device includes: virtual processor and verification module;Virtual processor includes the virtual bus controller to be measured;Wherein, virtual processor and the virtual bus controller to be measured are hardware description file;Virtual processor is used to send bus control instruction to verification module by communication module according to the verification demand issued by host computer;Verification module is used to carry out bus data frame transmission with the virtual bus controller to be measured by bus transceiver according to bus control instruction;Host computer is used to verify the virtual bus controller to be measured according to the bus data frame received by the virtual bus controller to be measured.The scheme can verify the prototype of bus controller, can detect the error in design stage, and developer can modify the design of bus controller according to the verification result, reduce the cost and time loss caused by failure in later period.

A server includes physical compute nodes. Each physical compute node includes a host and physical management resources. The physical management resources include a physical management processor. The server includes a distributed hypervisor to provide a distributed application operating environment that is hosted by the physical management resources. The distributed hypervisor to allocate, from the physical management processors, virtual processors for the distributed application operating environment to execute applications to manage the physical compute nodes. The distributed hypervisor includes a plurality of hyper-kernels that are associated with respective physical compute nodes. Each hyper-kernel is hosted on the physical management resources of the associated physical compute node.

A method is disclosed for updating a host compute layer (HCL) in a virtual machine (VM) host computer system. The method involves determining the availability of an update for the HCL of a guest VM operating on the VM host system. A message is sent to the HCL to persist the HCL's operating state, including pausing the execution of the guest operating system (OS) and then persisting the operating state. Subsequently, the virtual processor (VP) system associated with the guest VM is stopped, a register is set to a power-on or reset value, and updated HCL code is copied into the memory space of the HCL. The VP system is then resumed, booting the updated HCL, which restores the operating state and resumes the execution of the guest OS.

Embodiments of the present disclosure provide a processor time scheduling and container creation method, a device, a medium, and a program product. In the embodiments of the present disclosure, in order to implement flexible processor bandwidth control in a secure container, by means of extending a virtual processor core allocated to a conventional secure container, a constraint requiring one-to-one correspondence between usage duration (Quota) in the conventional secure container and virtual processor cores is broken, and the secure container can use the extended virtual processor core to consume unconsumed duration accumulated by a historical scheduling cycle under a high load, so that flexible processor bandwidth control is implemented, thereby meeting burst load demand and improving service quality of the secure container.

The invention discloses a software protection method based on a virtual machine encryption mode and a storage medium, and the method comprises the steps: encrypting to-be-protected data through a key to obtain encrypted data, the to-be-protected data comprising an executable code, a configuration file and a resource file of to-be-protected software; constructing a virtual machine execution environment in the equipment memory, wherein the virtual machine execution environment comprises a virtual processor, a virtual memory space and a virtual register; loading the encrypted data to a virtual memory space, and configuring a virtual processor; after the protected software is started, performing anti-debugging monitoring, and if a debugging behavior is monitored, executing an anti-debugging operation; during the running period of the to-be-protected software, the MAC address of the equipment is obtained regularly, and the legality of the equipment is verified; and when a preset self-destruction triggering condition is met, executing a self-destruction operation. According to the method, various security threats can be effectively resisted, and software code and data security is protected.

Hierarchical virtualization creates a child client partition that shares a hypervisor with a parent client partition. The hypervisor receives, from a first client partition operating at the hypervisor, a request to create a second client partition as a child of the first client partition. The hypervisor identifies a configuration specification for the second client partition, the configuration specification including (1) an identification of a memory portion allocated to the first client partition, the memory portion to be mapped into the second client partition; and (2) a configuration of a virtual processor to be utilized by the second client partition. The hypervisor creates a second client partition based on the configuration specification.

The embodiment of the invention provides a calling method and device for an interrupt communication system between para-virtualization processors, electronic equipment and a readable storage medium. The method comprises the steps that interrupt characteristics between the para-virtualization processors are configured for virtual processors; if the virtual processor starts the interrupt characteristic between the para-virtualization processors, setting an interrupt call function for the virtual processor so as to call the interrupt call function when an interrupt request is sent; and in response to calling of the interrupt calling function, directly updating the interrupt descriptor corresponding to the target virtual processor so as to enable the target virtual processor to process the interrupt request. According to the embodiment of the invention, by setting the interrupt calling function, when the interrupt request is subsequently transmitted, the interrupt descriptor of the target virtual processor is directly updated so as to process the interrupt request without intervention of a virtual machine monitor, so that the number of times that the virtual machine returns to the host machine state from the client machine state is reduced, and the performance of the virtual machine is improved.

The invention provides a processor calling method, device and equipment, the method is applied to computing equipment, a plurality of processors are arranged in the computing equipment and correspond to virtual processors, and the method comprises the steps that virtual processor information of the virtual processors is sent to a target application through a fusion layer, the virtual processor information comprises the number of virtual processors and the size of a virtual video memory corresponding to the virtual processors, and the size of the virtual video memory is the sum of the sizes of video memories of the processors; and intercepting a calling request of the target application to the virtual processor through the fusion layer, and calling the plurality of processors to process the calling request. And the resource utilization rate of a plurality of processors in the computing equipment is improved.

A system and method for virtual processor customization based upon the particular workload placed upon the virtual processor by one or more execution contexts within a given program or process. The customization serves to optimize the virtual processor architecture based upon a determination as to the size and / or type or virtual execution registers optimally suited for supporting a given execution context. This results in a time-variant processor architecture which not only provides optimized computational attributes, but also affords a high degree of inherent process security.

Systems and methods for servicing a virtualization stack without disrupting a virtual machine (VM) include detecting a servicing operation for a component of a virtualization stack supporting the VM. Upon detecting an interrupt from a virtual processor (VP) of a partition associated with the VM during the servicing operation, it is determined that the interrupt is a root interrupt type. In response to the interrupt being the root interrupt type, the method includes holding the interrupt at a hypervisor and suspending one or more VPs of the partition. Following completion of the servicing operation, the partition's VP(s) are resumed, and the interrupt is released to a root partition.

The invention relates to the technical field of virtual processor scheduling, in particular to a high-real-time virtual processor scheduling method for a multi-core processor. Comprising the steps that virtual processor threads of a host machine user space are scheduled according to a time slice rotation mechanism based on priorities, each virtual processor thread executes tasks in a correspondingly distributed time slice, and when the virtual processor threads are marked to be in a blocked state, the virtual processor threads are moved to a corresponding thread blocking queue, the virtual processor threads which are blocked due to time slice exhaustion are moved into a common thread blocking queue; the virtual processor threads which are blocked due to non-time slice depletion are moved into a real-time thread blocking queue. By introducing the high-real-time virtual processor scheduling method, the performance and the reliability of the embedded real-time operating system are remarkably improved, it is ensured that real-time tasks can also respond in time in a high-load environment, and therefore the strict real-time requirement is met.

The invention discloses a file data processing method and device, equipment, a medium and a product, and relates to the technical field of data processing, the method is executed by a file server, the file server comprises at least one candidate physical processor, and each candidate physical processor is provided with at least two candidate virtual processors. The method comprises the steps of determining a target file data type according to a target file data volume of to-be-processed file data; determining a target virtual processor from the candidate virtual processors according to the target file data type and candidate processor labels corresponding to the candidate virtual processors; and forwarding the file data processing request to the target virtual processor, and processing the to-be-processed file data according to the file data processing request through the target virtual processor. The parallel task throughput of the file server and the resource utilization rate of the file server are improved, high-concurrency file data processing requests can be effectively dealt with, and the file data processing efficiency is improved.

The invention provides a processor control method and device and a server, and the method can comprise the steps: determining a target physical core corresponding to a current virtual processor which is a virtual processor in a virtual machine; obtaining virtual configuration information of the current virtual processor, wherein the virtual configuration information is generated based on user configuration; and updating operation parameters of the target physical core according to the virtual configuration information. And the utilization rate of the physical processor is improved.

The disclosed embodiments provide a virtual machine load detection method, apparatus, electronic device, and storage medium. The method comprises obtaining a virtual processor thread corresponding to a target virtual machine, where the virtual processor thread is an exclusive thread of the target virtual machine; obtaining a first occupancy duration of the virtual processor thread in guest mode within a first detection cycle, wherein the virtual processor thread in guest mode is used to execute the task request of the target virtual machine, and the first occupancy duration represents the length of time the virtual processor thread is in a state of executing the task request of the target virtual machine; and obtaining the operating load of the target virtual machine based on the first occupancy duration and the proportion within the first detection cycle. This method solves the problem of being unable to perform out-of-band detection of virtual machine load for virtual machines with exclusive threads, while also improving the accuracy of load detection.

Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.

The present invention discloses a method, apparatus, device, medium and product for processing file data, relating to the field of data processing technology. The method is executed by a file server, the file server includes at least one candidate physical processor, and each candidate physical processor is respectively provided with at least two candidate virtual processors. The method comprises: determining a target file data type according to the target file data volume of the file data to be processed; determining a target virtual processor from each candidate virtual processor according to the target file data type and the candidate processor label corresponding to each candidate virtual processor; forwarding a file data processing request to the target virtual processor, and processing the file data to be processed according to the file data processing request by the target virtual processor. The present invention improves the parallel task throughput of the file server, as well as the resource utilization rate of the file server, can effectively cope with high-concurrency file data processing requests, and improves the efficiency of file data processing.

The invention provides an embedded device-oriented all-digital virtual simulation verification system, which belongs to the technical field of digital data processing and comprises a virtual processor, a peripheral, a memory, an input / output module, a simulation control module and a result analysis module. Modules such as a virtual processor can be customized according to different embedded device characteristics so as to support various devices. The virtual processor module comprises a unit simulation processor such as an instruction set; the virtual peripheral module is provided with a timer and other unit simulation peripherals; the virtual memory module is provided with RAM and ROM unit simulation memories; the virtual input and output module comprises unit analog interfaces such as keys; the simulation control module realizes system control and equipment interaction; the result analysis module analyzes the result and generates a report. According to the method, the problems of low simulation precision, poor expandability and low interactivity in the prior art are solved, the simulation precision is improved, the expandability and the interactivity are enhanced, and the method is of great significance to development and verification of embedded equipment.

A method includes: executing, on a host computer including a host processor and host memory, a hypervisor managing a virtual machine including a virtual processor and virtual machine memory, the virtual machine executing a guest program stored in the virtual machine memory, the guest program including machine instructions; disabling, by the hypervisor, execute permissions on a first page of the virtual machine memory; and handling, by the hypervisor, a first abort triggered when the virtual processor executes an instruction in the first page of the virtual machine memory having an execute permission disabled including: replacing, by the hypervisor, one or more instructions in the first page of the virtual machine memory; disabling read and write permissions and enabling an execute permission in a first entry of a page table corresponding to the first page of the virtual machine memory; and resuming execution of the guest program on the virtual processor.

Embodiments of the present disclosure disclose a computing device, and are applied to the field of computing devices. In the present disclosure, a virtual interrupt obtained by a host machine is mapped to a physical interrupt of a physical layer, and a virtual interrupt identifier corresponding to the physical interrupt is transferred to a virtual processor by using the physical layer. When a hardware layer transparently transmits the virtual interrupt identifier to the virtual processor, the virtual processor does not need to exit. This decreases a delay caused by exit of the virtual processor when software implements virtual interrupt routing.

A method includes: executing, on a host computer including a host processor and host memory, a hypervisor managing a virtual machine including a virtual processor and virtual machine memory, the virtual machine executing a guest program stored in the virtual machine memory, the guest program including machine instructions; disabling, by the hypervisor, execute permissions on a first page of the virtual machine memory; and handling, by the hypervisor, a first abort triggered when the virtual processor executes an instruction in the first page of the virtual machine memory having an execute permission disabled including: replacing, by the hypervisor, one or more instructions in the first page of the virtual machine memory; disabling read and write permissions and enabling an execute permission in a first entry of a page table corresponding to the first page of the virtual machine memory; and resuming execution of the guest program on the virtual processor.

Embodiments of the present disclosure provide a method and an apparatus for scheduling a virtual machine thread includes: determining, by a load balancing scheduler, processor affinity of a first virtual central processing unit (VCPU) thread on a virtual processor of a virtual machine in response to receiving a scheduling instruction for the first VCPU thread; determining, based on the processor affinity of the first VCPU thread, a second hyper-threading logical processor in the target physical processor as processor affinity of a second VCPU thread in the virtual processor; scheduling, based on the processor affinity of the first VCPU thread, the first hyper-threading logical processor to run the first VCPU thread; and scheduling, based on the processor affinity of the second VCPU thread, the second hyper-threading logical processor to run the second VCPU thread.

A virtual processor is provided that can be mapped to a plurality of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with additional interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines whether to route the interrupt request to one of the subset of physical processors or to one of the additional interrupt distributors based on cached virtual processor mapping information. When a rejection response is received in response to the interrupt request being routed to one of the additional interrupt distributors, an update to the cached virtual processor mapping information is requested based on shared virtual processor mapping information and the re-sent interrupt request is sent to another interrupt distributor determined based on the shared virtual processor mapping information.

Aspects of the present disclosure relate to hypervisor upgrades for real-time virtual machines. More specifically, a method of the present disclosure includes initiating, at a computing device, a second instance of a management user space component of a hypervisor associated with a virtual machine, wherein a virtual processor associated with the virtual machine is operating in association with a first instance of the management user space component. The method includes initiating a migration of a state of the first instance of the management user space component to the second instance of the management user space component. The method includes attaching the second instance of the management user space component to a kernel component, wherein a state of the virtual processor is maintained by the kernel component.