115 results about "Thread (computing)" patented technology

The invention belongs to the field of parallel computing architecture optimization, and relates to a matrix multiplication acceleration method and system based on dynamic computing resource mapping, and the method comprises the steps: constructing a dynamic topology model driven by tensor dimension features, and generating a thread block distribution mode according to matrix parameters and GPU hardware information; constructing a multi-dimensional resource scheduling strategy library, dynamically selecting an optimal thread block distribution strategy from the multi-dimensional resource scheduling strategy library, and generating a binding relationship between the thread blocks and the data blocks; calculating collaborative access logic of thread blocks and storage hierarchies based on block parameters and dynamic mapping function optimization; distributed calculation is carried out, calculation and data transmission are parallelized through pipelining and a double-buffering mechanism, and result aggregation across calculation units is completed synchronously through atomic operation and a barrier. According to the method, discontinuous memory access conflicts can be effectively reduced, the execution efficiency of the calculation instruction and the utilization rate of the cache space are improved, the parallel calculation process of accelerating and optimizing the general matrix multiplication is realized, and the data processing efficiency is improved.

The invention discloses a processor, a graphics card, equipment and a resource allocation method and device, and belongs to the technical field of computer resource management. The processor comprises a thread group assembling unit, a thread group scheduling execution unit and at least two processing units, the thread group assembling unit is used for assembling the tasks into one or more thread groups based on the attribute information of the tasks in a task assembling stage; and allocating computing resources for one or more thread groups with the thread group granularity, wherein each thread group is allocated with a processing unit; the thread group scheduling execution unit is used for scheduling one or more thread groups to the processing unit corresponding to each thread group for execution according to a unified scheduling rule, and the unified scheduling rule is a scheduling rule shared by different types of tasks; and the at least two processing units are used for executing the scheduled thread groups. And the computing resources are allocated according to the thread group granularity, so that the execution efficiency of the processor is improved.

The invention provides an artificial intelligence chip and an operation method thereof. The artificial intelligence chip comprises a tensor core, a tensor transmitting unit, a general computing core, a general transmitting unit and a thread block segmentation unit. In response to operation of the thread block segmentation unit in the first operation mode, the thread block segmentation unit distributes a thread bundle to the general-purpose transmission unit, and the general-purpose transmission unit transmits an instruction to the tensor core and the general-purpose computing core. In response to operation of the thread block segmentation unit in the second operation mode, the thread block segmentation unit distributes a tensor thread bundle involving tensor calculation to the tensor transmitting unit, the tensor transmitting unit transmits a tensor calculation instruction to the tensor core, the thread block segmentation unit distributes a non-tensor thread bundle not involving tensor calculation to the general transmitting unit, and the general transmitting unit transmits a non-tensor thread bundle involving tensor calculation to the general transmitting unit. And the general transmitting unit transmits the non-tensor calculation instruction to the general calculation core.

The invention relates to the technical field of artificial intelligence chips, and discloses a data processing method and device, a processor and electronic equipment. Determining a first jump step length required for rearranging the block data based on the block size of the input data in the first dimension; secondly, performing jump reading on the block data according to a first jump step length, rearranging and loading read input elements into a thread private register so as to realize transposition storage of the block data in the thread private register, and mapping a thread direction on a second dimension so as to obtain a data basis of convolution correlation calculation; convolution correlation calculation is executed based on the transposed data in the thread private register and the weight data in the thread private register, repeated data reading in the calculation process is reduced during sliding window calculation, and an operator is converted into calculation performance bottleneck operation from memory access performance bottleneck operation.

The invention provides a thread block scheduling module, a general-purpose computing graphic processing unit, equipment and a product, and relates to the technical field of data process.The method comprises the steps that an operation data analysis unit conducts data analysis on all first thread blocks of a computing task issued by a host, and second thread blocks sharing data with all the first thread blocks are determined; the mapping relation between the first thread block and the second thread block is written into a thread block data mapping table of the queue management unit; the resource management unit is used for recording available resources and used resources of each streaming multiprocessor and information of a thread block currently allocated to each streaming multiprocessor; and the thread block allocation unit is used for allocating the thread blocks of the first target thread block to the corresponding stream multiprocessors according to the thread block data mapping table of the first target thread block under the condition of detecting that any stream multiprocessor recorded by the resource management unit has idle available resources.

The invention discloses a heterogeneous computing scheduling method and device based on a proxy thread, computer equipment and a storage medium, the scheduling method comprises the steps that a working thread group and the proxy thread are created, the working thread group comprises at least one working thread, and a lockless communication queue is established to connect the working thread group and the proxy thread; in response to the received to-be-processed task of the execution unit, the working thread submits an operation request of the to-be-processed task to the proxy thread through the lock-free communication queue; in response to successful submission of the operation request, performing local data calculation by the working thread, and entering dormancy if the local data calculation is completed; in response to the operation request received by the proxy thread, the proxy thread submits the operation request to an execution unit and polls whether the to-be-processed task is processed or not; in response to completion of processing of the to-be-processed task, the proxy thread wakes up a corresponding working thread through a callback function and returns a processing result; by means of the method, the high concurrency performance and the compatibility of heterogeneous equipment can be remarkably improved.

According to the SpMM optimization method and device oriented to the GPU-like architecture, on the premise that the standard CSR storage format is not changed, dual load balancing in the thread bundles and between the thread bundles can be achieved, and computing power waste caused by row length difference of a traditional row-split strategy is eliminated. The method comprises the following steps: (1) inputting a sparse matrix A; (2) calculating the number of non-zero elements in the longest row of the sparse matrix A; (3) judging whether rows with more than 64 non-zero elements exist in the sparse matrix A or not, and if yes, executing the step (4); if not, executing the step (6); (4) binning operation: dividing matrix rows into three categories according to the number of non-zero elements; (5) each category is processed by a corresponding computing kernel, a short traveling box calls a short traveling box kernel to compute, a middle traveling box calls a middle traveling box kernel to compute, and a long traveling box calls a long traveling box kernel to compute; skipping to the step (7); (6) calling kernel calculation in the short-row box; and (7) writing back a result.

The invention provides a method for executing convolution operation in a vector operation unit, computing equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: loading a first matrix of convolution operation to a thread local register; loading the second matrix of the convolution operation to a thread bundle scalar register of the vector operation unit through the thread local register; multiplying and adding two elements of one sub-matrix of the first matrix read from the thread local register and two corresponding elements of the second matrix read from the thread bundle scalar register through a multiply-add instruction to obtain a result of the multiply-add instruction, wherein the multiply-add instruction is used for multiplying and adding two elements of one sub-matrix of the first matrix read from the thread local register and two corresponding elements of the second matrix read from the thread bundle scalar register; and adding a result of the multiply-add instruction and a product of a third element of the sub-matrix read from the thread local register and a third corresponding element of the second matrix read from the thread bundle scalar register to obtain one element of a result matrix of the convolution operation.

The invention provides a lightweight deployment method and system of a large model on edge computing equipment. According to the method, the acceleration capability portrait is constructed by extracting the hardware instruction set architecture type of the target edge device and the number of parallel computing units. Based on the instruction type, the large model weight is grouped, divided and pre-calculated through a unified lookup table vectorization engine, and a pre-calculation vector matched with the target instruction set is generated; and according to the number of the parallel units and the instruction-level parallel capability, compiling the pre-calculation vector to generate an adaptive parallel table look-up instruction block, distributing execution threads with the same number as the parallel units, and eliminating data dependence conflicts. And finally, loading the instruction block to a shared memory area, configuring topological logic of the photoconductive switch matrix based on an instruction type, and dynamically switching a data transmission path in a hardware instruction period. According to the method, the efficient deployment of the large model in the edge equipment and the low-delay reasoning in the resource-constrained environment are realized.

The invention discloses a protocol result obtaining method and computing device.In the method, for any thread block, all threads in the thread block are operated, elements stored in multiple registers corresponding to the threads are stipulated, protocol results corresponding to the threads are obtained, and according to the protocol results corresponding to the threads, the elements stored in multiple registers corresponding to the threads are stipulated. Updating a protocol result in a shared memory corresponding to the thread block; the element belongs to an input tensor; running a target thread in each thread block, and updating a first protocol result in the global memory according to a protocol result in the shared memory corresponding to each thread block; running a target thread in the target thread block, and determining a first protocol result in the global memory as a protocol result corresponding to the input tensor; the target thread block belongs to a plurality of thread blocks. Through the register-shared memory-global memory protocol mode, the problem of low acquisition efficiency of the protocol result in related technologies is solved.

The invention discloses a core allocation method and device for a many-core processor, equipment and a medium, and relates to the field of big data processing, and the method comprises the steps: obtaining target storage resource information of a target kernel function, and determining a target storage resource demand based on the target storage resource information, integrating the target storage resource demands of the target kernel functions to obtain a target total demand; obtaining a target storage resource occupancy ratio corresponding to the target kernel function based on the target storage resource demand and the target total demand, and determining an allocable core number according to the target storage resource occupancy ratio and the total core number of the many-core processor; determining a target distributable core distributed from the many-core processor according to the number of distributable cores, determining a mapping relation between the target kernel function and the target distributable core, storing the mapping relation to a mapping table, and using the mapping table to schedule the target distributable core through a preset thread block scheduler. And scheduling the thread block of the target kernel function to the target distributable core for execution. And efficient distribution and scheduling of the core computing units are realized.

The invention relates to the technical field of high-performance computing, and provides an inter-thread data sharing method, electronic equipment, a storage medium and a program product.The method comprises the steps that a plurality of threads in a thread block are divided into at least one cooperative thread group, and the threads in each cooperative thread group are from at least two different thread bundle groups; when a write operation of a first thread in any cooperative thread group is received, writing target data into a shared register resource associated with any cooperative thread group; and when a read operation of a second thread in any cooperative thread group for the target data is received, executing a synchronous operation, and reading the target data from the shared register resource after the execution is completed. According to the method, the cooperative thread group spanning different thread beam groups is constructed, and the shared register resources are utilized for data exchange, so that efficient data sharing is directly carried out among the threads spanning the thread beam groups through the register, and the method has the advantages of low delay, high bandwidth and capability of remarkably improving parallel computing performance.

The invention provides a load diagnosis and processing method and device, electronic equipment, a medium and a program product, which can be applied to the technical field of cloud computing. The method comprises the following steps: acquiring a performance index sequence of at least one candidate application process, and in response to meeting a high-load triggering condition, determining a target process to be diagnosed and generating an abnormal event identifier; obtaining thread resource occupation information of the target process in response to the abnormal event identifier, determining an abnormal thread based on the thread resource occupation information, and obtaining execution stack information corresponding to the abnormal thread; thread features are extracted based on the thread resource occupation information and the execution stack information, and a root cause classification label is determined based on the thread features; and generating processing suggestion information for the target application process based on the root cause classification label.

This disclosure describes approaches for sandboxing a thread and memory resources within non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: providing a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to establish a sandbox for a particular thread that executes in the non-secure processing environment and is associated with at least one specified memory region; and associating other threads of the non-secure processing environment with the secure processing environment, such that the particular thread is unable to access memory resources of the other threads while the particular thread is sandboxed.

The invention provides a general purpose computing unit and computing equipment. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and a thread local register for each execution unit, including a plurality of thread beam registers allocated for a plurality of thread beams run by the execution unit, the plurality of thread beam registers being non-overlapping, where the thread local register further includes a shared register shared by the plurality of thread beams.

The invention provides an artificial intelligence chip and a collaborative thread bundle calculation method. The cooperative thread bundle calculation method comprises the following steps of: initializing a plurality of thread bundle units by a thread bundle resource allocation unit, so that the plurality of thread bundle units have the same initial vector register base address to form a group of cooperative thread bundles; the thread beam resource allocation unit notifies a thread beam scheduling and instruction transmitting unit to send a plurality of execution instructions to an execution unit; running a plurality of thread bundles of the plurality of thread bundle units by the execution unit according to the plurality of execution instructions; reading different scalar parameters from the respective scalar registers of the plurality of thread bundle units by the plurality of thread bundles; and accessing, by the plurality of thread bundles, the same register space of the vector register according to the same initial vector register base address. According to the artificial intelligence chip and the cooperative thread beam calculation method, the efficient cooperative thread beam calculation function of the cross-thread beam sharing vector register block can be achieved.

The invention provides a general purpose computing unit and an instruction scheduling method for the general purpose computing unit. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and an instruction scheduler for determining a priority of the plurality of operation instructions based on whether the multiplexing flag exists, and scheduling each operation instruction to one of the plurality of execution units based on the priority; wherein each execution unit comprises one or more reuse registers, each reuse register is used for registering an operand of a previous operation instruction and a label, and the label is used for indicating an address and a thread bundle of the operand; and the instruction decoding unit is used for decoding the received operation instruction to determine the reading position of the operand of the operation instruction. The instruction is preferentially scheduled by adding a reuse mark to the whole operation instruction, so that the hit rate of the operand is improved, and excessive instruction bit fields do not need to be occupied.

The invention provides a thread dynamic scheduling and management method based on real-time resource feedback, which belongs to the field of operating system resource scheduling, and comprises the following steps of: acquiring resource utilization rate, load queue length and thread delay data of a CPU (Central Processing Unit), a memory and a hardware accelerator in real time, and combining task type (calculation / I / O (Input / Output) intensive type), priority and deadline characteristics; constructing a dynamic scheduling strategy: firstly, distributing an initial priority and a time slice by adopting an improved multi-level feedback queue algorithm, secondly, optimizing a resource matching degree through a particle swarm algorithm, and dynamically adjusting a thread priority and a migration strategy according to real-time resource fluctuation in task execution; and finally, realizing cross-processor load balancing based on a minimum residual load migration principle and flow table type queue management. According to the method, through multi-dimensional resource feedback closed-loop control, the problems of non-uniform resource utilization, long-range starvation and low cooperation efficiency of heterogeneous equipment in traditional scheduling are solved.

Embodiments of the disclosed technologies include generating a first thread classification prompt based on a first thread portion of an online dialog involving a user of a computing device, sending the first thread classification prompt to a first large language model, receiving a first thread classification generated and output by the first large language model based on the first thread classification prompt, formulating a plan execution prompt based on the first thread classification, sending the plan execution prompt to a second large language model, receiving a second thread portion generated and output by the second large language model based on the plan execution prompt and the online dialog, and generating a label for a third thread portion of the online dialog.

An intelligent task configuration method based on big data SQL code computing power analysis performs computing power evaluation on sql codes to be operated, and the core lies in that a query processing process is decomposed into three key dimensions: an operation type, a data scale and processing complexity. Each dimension is quantized through well-designed parameters, and finally a unified computing power demand calculation formula is integrated. The formula not only considers a single-thread execution scene, but also particularly adds extra overhead brought by parallel processing, so that an evaluation result is closer to an actual operation environment. The SQL code is further stored in a notebook and kept as a file, the hash value of the file is calculated to serve as an identification code, a plan of an sql code running task is configured according to the authority level and the real-time computing power condition of a user, and computing power resource allocation is intelligently optimized.

This application discloses a method and computing device for obtaining reduction results. In this method, for any given thread block, each thread within the thread block is run, and the elements stored in multiple registers corresponding to each thread are reduced to obtain the reduction result corresponding to that thread. Based on the reduction result corresponding to each thread, the reduction result in the shared memory corresponding to the thread block is updated; the elements belong to the input tensor. The target thread in each thread block is run, and based on the reduction result in the shared memory corresponding to each thread block, the first reduction result in the global memory is updated. The target thread in the target thread block is run, and the first reduction result in the global memory is determined as the reduction result corresponding to the input tensor; the target thread block belongs to multiple thread blocks. Through the above register-shared memory-global memory reduction method, the problem of low efficiency in obtaining reduction results in related technologies is solved.

Embodiments of the disclosed techniques include generating a first thread classification cue based on a first thread portion of an online conversation involving a user of a computing device; sending the first thread classification prompt word to a first large language model; receiving a first thread classification generated and output by the first large language model based on the first thread classification prompt word; formulating a plan execution cue word based on the first thread classification; sending the plan execution cue word to a second large language model; receiving a second thread part generated and output by the second large language model based on the plan execution cue word and the online dialogue; and generating a tag for a third thread portion of the online conversation.

A computer-implemented method comprising: obtaining real-time text data relating to a matter, the text data comprising a plurality of portions of information; performing a categorisation process, wherein the categorisation process is configured to run a plurality of threads in parallel, wherein each thread of the plurality of threads acts on one portion of information at a time, wherein each thread performs the following steps: (i) obtaining a sentiment score based on the portion of information using a Sentiment Analysis machine learning, ML, model; (ii) assigning a category to the matter based on the sentiment score using a classification ML model trained on historical data; and (iii) updating a live category based on the category assigned to the matter; and finally, outputting the live category to a user in real-time.

Apparatuses, systems, and techniques to use user-editable configuration inforamation to use one or more computing resources to perform one or more threads. In at least one embodiment, one or more user-editable configuration files are used to cause one or more computing resources to be allocated to perform one or more software threads.

Systems, apparatuses, and methods are disclosed for arbitrating threads in a computing system. The computing system includes a processor having a plurality of cores that are each capable of concurrently processing instructions of a plurality of threads. When a thread throttling unit receives an indication that a shared cache has a resource contention, the throttling unit sets a cache miss threshold for the cache. If the number of cache misses exceeds the threshold, the throttling unit notifies a particular upstream computing unit to throttle the processing of instructions of the thread. After a time period elapses, if the cache continues to exceed the threshold, the throttling unit notifies the upstream computing unit to more restrictively throttle the thread by performing one or more of decreasing a selection rate and increasing the time period. Otherwise, the unit notifies the upstream computing unit to less restrictively throttle the thread.

The application discloses a data screening, large language model output acceleration method, device, medium and product. The data screening method comprises the following steps: selecting a thread bundle and determining a local comparison value of the thread bundle; triggering each thread bundle to execute an operation of comparing the numerical value between each current probability value and the baseline value of itself, and updating the key value of itself using each current probability value greater than the baseline value of itself; comparing the screening threshold of a target screening algorithm with the key value of each thread bundle; if the screening threshold and the key value of each thread bundle do not match, updating the target set and the current probability value set according to the identified first thread bundle and second thread bundle; and if the screening threshold and the key value of the third thread bundle match, updating the target set according to the third thread bundle as a screening result. The technical scheme of the embodiment of the application effectively reduces the calculation complexity of the data screening algorithm in a soft and hard cooperative manner, and maximally utilizes the parallel computing hardware in the artificial intelligence acceleration computing chip.

The invention discloses a federated learning acceleration method and system based on pipeline in-batch real-time data sampling and training. According to the method, in-batch data sampling is provided on the algorithm level aiming at the problems that computing resources of edge equipment are limited and importance is outdated and gradient deviation is caused by existing static sampling: the importance of samples in a fixed mini-batch is evaluated in real time by utilizing a latest model in each round of iteration, and a dynamic micro-batch is constructed; and through a gradient correction coefficient based on a sampling probability reciprocal, distribution deviation is eliminated, and unbiased training is realized. On the system level, an assembly line parallel mechanism based on a CPU-GPU heterogeneous architecture is designed, overlapping execution of sampling and training is achieved through a double-thread-double-flow concurrent model, data competition is solved through an annular buffer area and an event synchronization mechanism, and overhead is reduced in cooperation with mixing precision reasoning. According to the method, the hardware utilization rate can be remarkably improved, the model convergence precision is improved while the training time is greatly shortened, and the method is suitable for various edge computing scenes.

This disclosure describes an implementation of a computing system that utilizes accelerator hardware configured to perform parallel computation of matching pairs of a join operation of a database program. This computation is performed at least in part by, for each thread that determines a matching pair, computing an offset in an output tuple by adding a global rank of a respective block, an intra block rank of a respective warp, and an intra warp rank of a respective thread. This computation is further performed by storing index values for a primary key and a foreign key in a matching pair at the computed offset location in an output tuple, and outputting the output tuple.

The present disclosure provides methods, apparatus, computing devices, computer storage media, and computer program products for rendering elements in an interface. A method includes determining a plurality of elements in an interface to be rendered, processing, by a first thread of a plurality of threads, a first rendering stage for a first element of the plurality of elements, and in response to the first rendering stage for the first element being processed to completion, processing, by a second thread of the plurality of threads, a second rendering stage for the first element and processing, by the first thread, a first rendering stage for a second element.

This disclosure provides a method, computing device, computer-readable storage medium, and computer program product for performing convolution operations in a vector processing unit. The method includes: loading a first matrix of the convolution operation into a thread-local register; loading a second matrix of the convolution operation into a thread-beam scalar register of the vector processing unit via the thread-local register; multiplying two elements of a submatrix of the first matrix read from the thread-local register and two corresponding elements of the second matrix read from the thread-beam scalar register using a multiply-add instruction to obtain a result of the multiply-add instruction; and adding the result of the multiply-add instruction to the product of a third element of the submatrix read from the thread-local register and a third corresponding element of the second matrix read from the thread-beam scalar register to obtain an element of the result matrix of the convolution operation.