63 results about "Thread (computing)" patented technology

A parallel thread processor executes thread groups belonging to multiple cooperative thread arrays (CTAs). At each cycle of the parallel thread processor, an instruction scheduler selects a thread group to be issued for execution during a subsequent cycle. The instruction scheduler selects a thread group to issue for execution by (i) identifying a pool of available thread groups, (ii) identifying a CTA that has the greatest seniority value, and (iii) selecting the thread group that has the greatest credit value from within the CTA with the greatest seniority value.

The invention discloses a frequent subgraph excavating method based on graphic processor parallel computing. The method includes marking out a plurality of thread blocks through a graphic processing unit (GPU), evenly distributing frequent sides to different threads to conduct parallel processing, obtaining different extension subgraphs through right most, returning the graph excavating data set obtained by each thread to each thread block, finally utilizing the GPU to conduct data communication with a memory and returning a result to a central processing unit (CPU) to process the result. The graph excavating method is feasible and effective, graph excavating performance is optimized under intensive large data environment, graph excavating efficiency is improved, data information is provided for scientific research analysis, market research and the like fast and reliably, and a parallel excavating method on a compute unified device architecture (CUDA) is achieved.

A computer implemented method for automatically for determining errors in concurrent program using lock localization graphs for capturing few relevant lock/unlock statements and function calls required for reasoning about interference at a thread location at hand, responsive to first and second threads of a concurrent program, constructing generalized lock causality graphs and computing cycle signatures, and determining errors in the concurrent program responsive to computing an interference graph and data flow analysis.

A method is presented for processing one or more instructions to be executed on multiple threads in a Single-Instruction-Multiple-Data (SIMD) computing system. The method includes the steps of analyzing the instructions to collect divergent threads among a plurality of thread groups of the multiple threads; obtaining a redirection array for thread-operand association adjustment among the divergent threads according to the analysis, where the redirection array is used for exchanging a first operand associated with a first divergent thread in a first thread group with a second operand associated with a second divergent thread in a second thread group; and generating compiled code corresponding to the instructions according to the redirection array.

The embodiment of the invention discloses a critical resource access method and device, computer equipment and a readable storage medium, which are beneficial to reducing the operation quantity of a thread competition lock, saving computing resources and improving the performance of an ARM architecture processor. The critical resource access method comprises the steps of: selecting a first threadfrom a first thread and a second thread to compete for a target lock, and a first task to be executed by the first thread and a second task to be executed by the second thread correspond to the targetlock; and competing for the target lock based on the first thread to enable the first thread to execute the first task and replace the second thread to execute the second task.

A central processing unit (CPU) according to embodiments of the inventive concept may include an upper core allocated with a main thread and a plurality of lower cores, each of the plurality of the lower cores being allocated with at least one worker thread. The worker thread may perform simulation operations on operation units of a graphic processing unit (GPU) to generate simulation data, and the main thread may generate synchronization data based on the generated simulation data.

The invention provides a request processing method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of data processing. The method comprisesthe steps of obtaining n requests, wherein each request corresponds to a cothread on the thread, and n is an integer greater than 0 and is less than or equal to a preset threshold; determining one dominant coroutine in the n coroutines according to a preset competition rule, and taking the other n-1 coroutines as following coroutines; merging the n requests through the dominant coroutine to obtainmerged request data; and submitting the merge request data to the computing device. According to the embodiment of the invention, when the request processing method is used for processing a pluralityof requests input by a user, the coroutines are introduced to serve as the execution units, the obtained n requests correspond to the coroutines respectively, the dominant coroutines are determined according to the preset competition rule to merge the n requests, server resource consumption caused by cross-thread competition is reduced, and therefore the computing performance of the server can bebrought into full play.

The invention discloses a compiler implementation method supporting heterogeneous computing core architecture. The compiler implementation method comprises the steps of converting a high-level language program into an intermediate representation code; converting the intermediate representation code into a machine code instruction; according to the types of the machine code instructions, mapping the machine code instructions of different types to corresponding computing cores in the heterogeneous computing core architecture to be executed, wherein the machine code instructions comprise a universal instruction, a cluster instruction and a thread instruction, and for the cluster instruction, a corresponding self-defined built-in function is adopted for conversion; and for general instructionsand thread instructions, adopting an existing built-in function or instruction of an open source compiler for conversion. According to the compiler implementation method, multiple types of high-levellanguage programs can be automatically processed, and the high-level language programs are sequentially converted into the intermediate representation codes and the machine code instructions which can be finally executed, and the machine code instructions are distributed to different computing cores to be executed according to the attribute types of the machine code instructions, and data transmission through a system bus is avoided, and the instruction execution performance is improved.

The embodiment of the invention discloses a concurrent calculation method and device for tasks, equipment and a storage medium, and the method comprises the steps: obtaining an independent atomic taskset among all atomic tasks, and enabling each atomic task in the atomic task set to be a corresponding preset step in a to-be-processed task; putting the atomic tasks in the atomic task set into a thread calling queue according to a specific sequence; calling threads in a processor to execute the atomic tasks in the thread calling queue in a one-to-one correspondence manner; monitoring an execution state of each atomic task; and under the condition that the execution state of each atomic task is a completed state, determining that concurrent processing of the to-be-processed tasks is completed.

The invention discloses a thread migration method and device, a storage medium and electronic equipment. The method comprises the following steps: detecting whether a first type of thread exists in aninitial processor core or not, wherein the first type of thread is a thread for executing related tasks in a user interaction event; when the first kind of threads exist in the initial processor core, using the first kind of threads in the initial processor core as first target threads; determining a first target processor core of which the computing power is higher than that of the initial processor core from the plurality of processor cores; and migrating the first target thread to the first target processor core. According to the method, when it is detected that the first kind of threads are located in the processor core with low computing power, the first kind of threads are migrated into the processor core with high computing power, so that the first kind of threads executing the user interaction event related tasks are processed more efficiently, and therefore the jamming phenomenon in a user interaction scene is reduced.

An instruction scheduling method, an instruction scheduling device, a processor and a storage medium, the instruction scheduling method comprising: selecting a first instruction fetch request for a first instruction address initiated by a first thread bundle, and performing instruction fetch operation for the first instruction address; receiving first instruction data which is returned from the first instruction address and corresponds to the first instruction fetching request; and in response to a second fetch request initiated by a second thread bundle for fetch of the first instruction address, broadcasting and sending the first instruction data to the write address of the instruction data access area of the first thread bundle and the write address of the instruction data access area of the second thread bundle in the first clock period. According to the instruction scheduling method, the access of the computing unit to the instruction cache or other cache systems such as the multi-level cache due to the instruction fetching operation can be reduced, and the access bandwidth of the instruction cache or other cache systems such as the multi-level cache can be reduced; and therefore, the access bandwidth of the cache system such as the data cache of the data required for executing the instruction or other multi-level caches can be reduced.

A method, computer program product, and computing system for executing a first sub-thread of an operating system thread on a central processing unit (CPU) of the computing device. The CPU may be released for a defined period of time. One of an application and a second sub-thread of the operating system thread may be executed based upon, at least in part, an execution priority of the operating system thread and an execution priority of the application.

The invention discloses a dynamic resource scheduling method based on an analysis technology and data flow information on heterogeneous many-cores, and relates to the field of heterogeneous many-core systems. The method comprises the following steps: analyzing a program, and determining the execution times of a parallelizable loop body; determining a data flow diagram of the loop body; setting a threshold value, and calculating the number of required GPUs; dividing the GPU task size according to dependence; distributing the tasks to different GPUs for operation according to the data streams of the tasks; and checking whether the platform is load-balanced. The invention mainly aims at providing a resource scheduling method based on information during program analysis and program data flow information aiming at the current situation that programmers need to set the number of GPUs and manually divide tasks on a heterogeneous platform. The execution times and the data dependence of the loop statements obtained through analysis are utilized, a threshold value is set to determine the number of the set GPUs, the thread granularity with data dependent task division is increased, tasks are distributed to each GPU for running by utilizing data flow information at the same time, and a work-stepping algorithm is actively detected and combined to solve the problem of platform load balancing, therefore, the dynamic resource scheduling method capable of automatically setting the number of GPUs, improving the utilization rate of GPU computing resources, actively detecting and realizing load balancing is realized.

The invention provides a method of operating a lock in a computing system with a plurality of processing units in a plurality of runtime environments. The method includes: determining whether an owner thread is suspendable or not when the lock is owned by the owner thread and a requester thread tries to obtain the lock; making the requester thread to be in a spinning state if the owner thread is not suspendable no matter whether the requester thread is suspendable or not; determining whether the the requester thread is suspendable or not if the owner thread is suspendable unless the requester thread gives up obtaining the lock; arranging the requester thread to try again to obtain the lock if the requester thread is not suspendable, and adding the requester thread to a waiting queue as an added suspension thread if the requester thread is suspendable; allowing to restore suspended threads stored in the waiting queue soon afterwards to obtain the lock. The method is applicable to the computing system with a multi-core processor.

The invention discloses a quantum computing distributed queue management method and system, belongs to the technical field of quantum computing, distributed clusters and queue management, and is used for solving the technical problems of single-thread running tasks of a single simulator, heavy tasks and low execution efficiency. The method comprises the steps of querying a newly-added task in a quantum experiment task table based on a preset time interval, and obtaining the submission time of the newly-added task; according to the submission time of the newly-added task, storing the newly-added task in a task queue; determining whether task execution nodes in the quantum computing simulator cluster are idle or not; if any task execution node is in an idle state, extracting a first newly-added task from the task queue through the task execution node to obtain a corresponding to-be-processed task; transmitting the to-be-processed task to a quantum computing simulator corresponding to the task execution node for execution to obtain an execution result of the to-be-processed task; and storing the execution result to a corresponding position in the quantum experiment task table.