110 results about "ARM architecture" patented technology

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

The invention discloses a heterogeneous resource energy-saving optimization scheduling method and system based on computing power perception, and relates to the technical field of modern computing infrastructure, the system comprises a computing power-energy consumption evaluation module, the computing power-energy consumption evaluation module is used for carrying out computing power and energy consumption evaluation on heterogeneous resources, generating and dynamically updating a computing power-energy consumption mapping table, the heterogeneous resources comprise ARM architecture resources, X86 architecture resources and GPU resources. According to the method, the computing power-energy consumption mapping table is generated and updated in real time, so that the scheduling decision is always based on the latest energy efficiency state of the resources, the accuracy of the basic data is ensured, intelligent task classification and dynamic constraint construction are combined, the system can flexibly balance the task performance and the energy consumption target, and particularly, the strategy can be adaptively adjusted for a high-emergency task; the timeliness of key services is guaranteed, the differentiated scheduling strategy serves as an efficient pre-screening mechanism, task requirements and resource architecture characteristics are accurately matched, and the pertinence and efficiency of resource allocation are remarkably improved.

The invention discloses an instruction conversion context switching optimization method based on stack frame hierarchical compression, which comprises the following steps of: loading and executing an executable file in a dynamic instruction conversion mode, and establishing a storage instruction set and a recovery instruction set containing a context switching complete process for context switching related instructions; constructing a register group according to the association degree of registers in the storage instruction set so as to realize the combined storage of register data by adopting a continuous memory space in the ARM architecture, and carrying out hierarchical compression on push data according to a function call hierarchical structure, recovery of the register data and the stack pressing data is achieved in the recovery instruction set according to the mapping relation table and the incidence relation table recorded in the storage process, the flexibility of processing a complex nested structure and a data type is improved, and correct execution of a program is ensured.

The invention discloses a bar code label designing and printing method and system based on an ARM framework and a storage medium. The method comprises the steps that a label template adding instruction is received, a user is prompted to set basic attributes of a label template, the basic attributes are stored, a label design page is initialized, and at least one label control object is preset in the page; in response to a selection instruction of a user for the label control object, adding the selected label control object into the label template, adjusting the attribute of the label control object according to user operation, and generating a label design effect preview; receiving a saving instruction, and prompting a user to confirm the saved information; receiving a storage confirmation instruction, analyzing the label template and converting the label template into a template definition file; compressing the template definition file to generate a label template compressed package; receiving a label printing instruction, decompressing and analyzing the template compressed package, and obtaining a label printing language; generating a printing instruction set according to the label printing language; and printing scheduling is carried out based on a preset scheduling mode, and the printing instruction set is output to a printer.

The invention relates to a self-adaptive optical matrix calculation acceleration method based on an ARM framework, and belongs to the field of self-adaptive optical wavefront correction technology and embedded parallel calculation. The method comprises the following steps: analyzing a mathematical mapping relationship between a microlens array and wavefront phase distribution in a Hartmann sensor image, and constructing a wavefront matrix operation model based on an ARM multi-core architecture; designing a Hartmann image data rearrangement strategy, dividing a single-frame Hartmann image into multiple task calculation units, and realizing parallelization processing of wavefront slope calculation; a wavefront matrix operation kernel is optimized according to ARM NEON instruction set characteristics, and vectorization calculation of multi-channel wavefront reconstruction is realized by adopting an SIMD parallelization technology; and computing resource allocation is coordinated through a dynamic thread scheduling algorithm, and the task allocation proportion among multiple cores is adjusted according to the real-time load condition. According to the method, the wavefront calculation efficiency is remarkably improved, so that the overall bandwidth of the adaptive optical system is greatly improved.

The invention aims to solve the technical problems of insufficient redundant architecture design, low fault diagnosis and switching efficiency and low system integration in the prior art, and provides a front wheel steering engine redundancy control system and method for an unmanned aerial vehicle. A double-ARM architecture cooperative control strategy is adopted, redundant fault-tolerant control of a mechanical coupling single-shaft driving system is achieved, two ARM chips independently drive two motors respectively, the motors are meshed through precision gears to form a mechanical coupling output structure used for driving a corresponding gear set, the gear set is in transmission connection with a gear mechanism, and the gear mechanism is in transmission connection with the gear mechanism. The steering wheel is matched with a nose landing gear of the unmanned aerial vehicle to realize steering; and each ARM chip is provided with a CAN port and an RS485 communication serial port and establishes a parallel data receiving mechanism.

The invention discloses a universal configurable airborne controller digital prototype model, which is characterized in that a virtual target machine simulation module realizes behavior-level simulation of an ARM architecture microcontroller through a Qemu technology, and constructs a virtual target machine for operating controller software; the control panel simulation module constructs a common resource library of a controller panel by using a QT tool, and selects a composition form of the control panel required by a project to form a simulation control panel; the bus data simulation module simulates external bus data excitation based on ICD; through co-simulation software, binding of the simulation control panel and the virtual target machine is realized, an external excitation signal is generated for the virtual target machine, and data transmission from simulation bus data to the virtual target machine and data transmission from target machine simulation to a control panel model are realized. According to the invention, building block type rapid construction of controller products in different projects in a digital prototype model is realized, and development, debugging and testing of software separated from a hardware environment are realized.

The invention relates to a timed startup and shutdown method based on an ARM architecture core processor and an industrial personal computer. The method comprises the following steps: acquiring current time from an RTC clock IC in real time; and controlling the industrial personal computer to be turned on or turned off according to the current time, the preset turn-on time and the preset turn-off time. At least the timed startup and shutdown function of the industrial personal computer based on the ARM architecture platform can be realized, and the energy-saving capability and wide applicability of the ARM architecture platform are improved.

A rail train environment sensing system based on ARM platform AI application deployment comprises a data acquisition module, an AI application module, a multi-modal algorithm module and an application display module, the data acquisition module acquires to-be-detected image data and preprocesses the to-be-detected image data through an ARM platform, the preprocessed image is transmitted to an edge computing server, the AI application module is called to recognize a target image, and the application display module displays the target image. The application display module sends a processing result of the multi-modal algorithm module to a display terminal platform; the edge computing platform based on the ARM architecture can support real-time reasoning of a lightweight deep learning model by means of the characteristics of low power consumption and high parallel processing, provides a reliable carrier for on-orbit processing of multi-modal sensing data, and meets the strict requirements of a train operation control system for safety standards.

The invention discloses an ARM architecture-based airborne general control board card, which comprises an ARM processor, a reset circuit, a discrete magnitude circuit, an SWD interface for programming software by the ARM processor, and an external connector for being electrically connected with external equipment, one pin end of the ARM processor is interactively connected with a communication circuit with an isolation function, and the other pin end of the ARM processor is interactively connected with a communication circuit with an isolation function. The input end of the ARM processor is connected with a power supply circuit and a reset circuit, the ARM processor is provided with a configurable interface, and the configurable interface of the ARM processor is connected with an analog quantity circuit; according to the invention, discrete magnitude input and output, analog quantity acquisition, RS422 communication and fault storage functions are integrated, signal output or signal input and acquisition functions can be realized, on-line loading, abnormal operation monitoring and power failure reset and restart of SWD interface programming software are realized, and the universal control requirements of adaptive power supply, power distribution and motor type aviation airborne equipment are met.

This invention discloses a real-time attitude estimation system for non-cooperative industrial targets based on strong tracking filtering, relating to the fields of industrial machine vision and automation control technology. This system decouples the complete six-degree-of-freedom attitude estimation problem into a linear translational sub-state space and a nonlinear rotational sub-state space. This decomposes the nonlinear calculations that would normally be performed in six dimensions into a three-dimensional linear problem and a three-dimensional nonlinear problem. The translational sub-state only performs a simplified Kalman gain iteration with closed-form solutions, and matrix operations are simplified to low-order linear recursion. Although the rotational sub-state uses strong tracking filtering, it only needs to perform nonlinear updates in the reduced low-dimensional space. The Jacobian matrix sparsification pre-computation and incremental update unit pre-stores the constant part of the observation equation's derivative calculation offline and only incrementally updates the sparsely changing part online. This allows the system to be fully deployed on ARM architecture edge devices and stably meet millisecond-level processing requirements.

The invention relates to the technical field of digital circuit processing, and discloses a data processing device under an ARM architecture. According to the method, a plurality of data processing threads are determined according to the number of registers and the number of external systems needing to be collected currently, and a corresponding sub-operation task is distributed to each data processing thread; performing operation processing on the sub-operation task according to a preset thread operation algorithm to obtain a sub-processing result corresponding to the data processing thread; and determining a final target processing result corresponding to the to-be-processed data element. Therefore, the to-be-processed data elements can be processed in parallel through a plurality of data processing threads under the ARM architecture, so that the ARM architecture can improve the processing efficiency and simplify the processing process while realizing the same capability of performing parallel operation on data as a DSP (Digital Signal Processor).

The invention provides an ARM architecture-oriented symmetric cipher encryption and decryption method and system, and relates to the technical field of encryption and decryption, the symmetric cipher adopts a block cipher, the block cipher adopts a round function to perform confusion and diffusion on data blocks in each round of encryption and decryption, and in a linear layer component for realizing diffusion, the data blocks are subjected to encryption and decryption in a byte copying and filling manner. The method comprises the following steps of: filling 8-bit or 16-bit original variables to be calculated to bits required by an ARM (Advanced RISC Machines) architecture, carrying out combined operation of cyclic shift, XOR and bit permutation on the filled variables, and carrying out low-bit extraction on an operation result according to the original bits of the variables to obtain an operation result of the original variables; according to the method, the linear layer efficiency of the small-size symmetric cryptography can be remarkably improved, a new thought and method are provided for lightweight symmetric cryptography algorithm design, and the method is of great significance to cryptography algorithm performance improvement in the Internet of Things and intelligent terminals.

The invention discloses a binary code instruction analysis method and device for an ARM architecture, and the method comprises the steps: carrying out the classification of instruction functions and purposes of instructions in given binary codes according to extracted setting information; according to the effect of the operand in the instruction, processing the operand through a preset standardization strategy; classifying and standardizing registers used by instructions in the binary codes; performing pointer expression standardization on pointer operation of the instruction in the binary code; creating a vocabulary which comprises a set of instructions and operands, and obtaining a standardized representation of the binary code; performing instruction serialization according to the appearance sequence of the instructions in the binary code, and converting the serialized instructions into a vector form; a serialized instruction in a vector form is input into a converter-based bidirectional encoder (BERT) for pre-training, and an expert model for converting a universal binary code representation into a specified task is obtained. The method solves the limitation of a traditional method in generalization ability and efficiency.

The invention discloses a PCH-free USB overcurrent protection system and an ARM hardware structure, the system comprises a mainboard module, the mainboard module comprises a central processor, a first CPLD, a first load switch, a first USB interface and a PCIe-to-USB unit; the central processing unit configures the working mode of the first CPLD; the first CPLD configures an over-current threshold and a first enable signal for controlling the first load switch according to the working mode, and triggers an interrupt signal to the central processing unit or turns off the power supply; the first load switch controls whether the power supply is connected to the first USB interface or not according to the first enable signal; the PCIe-to-USB unit is connected between the central processing unit and the first USB interface, converts a USB signal of the first USB interface into a PCIe signal and transmits the PCIe signal to the central processing unit under the PCIe drive of the central processing unit; or the PCIe signal of the central processing unit is converted into the USB signal to be output to the first USB interface. According to the invention, when no PCH exists in the ARM architecture, the over-current detection of the USB can be realized.

The application discloses a kind of block storage performance automation test method, system, storage medium based on FIO, it is related to cloud computing and storage performance test technical field, it is applied to the cloud platform environment including management node and multiple test nodes.By running environment deployment script on management node, automatically complete test node IP management, SSH password-free configuration, firewall processing and according to X86 / ARM architecture adaptive deployment FIO;Run test execution script, precheck is carried out to test disk and time synchronization, start FIO service on multiple nodes according to preset task queue, in turn complete the stress test of covering 4K / 32K / 128K / 1M block size and random, order, 7:3 mixed read-write scene;Run result arrangement script, automatically parse FIO log, extract and uniformly output the IOPS, bandwidth and latency index of each scene.The method reduces manual operation while improving the consistency and result reliability of block storage performance test.

The invention discloses a phosphorite grade sorting method and equipment based on an FPGA (Field Programmable Gate Array) and an ARM (Advanced RISC Machines) architecture, and relates to the technical field of phosphorite sorting. The method comprises the steps that a regression model is constructed, ore phosphorus grade data of a known grade is collected through a handheld X-ray fluorescence analyzer to serve as sample data, and model training is achieved; the method comprises the following steps: acquiring hyperspectral data and spectrums of ores on a transmission line in real time through a hyperspectral camera, dividing the hyperspectral data and spectrums into a plurality of narrow bands, and converting a signal of each narrow band into band reflectivity data; according to the method, hyperspectral data are converted into pseudo-color data, a plurality of wave band reflectivity data are established into multi-channel image data, grade regression is performed on each pixel point through a regression model, so that the ore surface phosphorus distribution condition is calculated, and grade sorting is realized. According to the method, the hyperspectral data of the ore is collected in real time through the hyperspectral camera, grade calculation and sorting are carried out through the constructed regression model, and the problems that existing phosphorite grade sorting is low in double speed and low in accuracy are solved.

The embodiment of the invention discloses an embedded application software upgrading method and device based on an ARM framework, and belongs to the field of embedded technologies. Comprising the steps that a configuration file containing to-be-upgraded application software in the mobile storage device is obtained, the to-be-upgraded application software comprises application software in an embedded system based on the ARM architecture, and the configuration file comprises an encrypted software upgrading file and a step file for updating the to-be-upgraded application software; identifying a configuration file in the mobile storage device based on the software naming information of the to-be-upgraded application software and the file naming information of the configuration file in the mobile storage device; when the software naming information of the to-be-upgraded application software is consistent with the file naming information of the configuration file, the corresponding software upgrading file is executed according to the step file in the configuration file so as to upgrade the to-be-upgraded application software, and the application software upgrading efficiency can be improved.

The present invention discloses a prefetch instruction conversion optimization method based on memory access mode virtualization. When an executable file is executed in a dynamic instruction conversion mode, the address memory access mode of the prefetch instruction of the x86 architecture is obtained, and the operand and offset calculation method of the prefetch instruction are analyzed. According to the address memory access mode, the operand and the offset calculation method, an instruction or instruction sequence of the ARM architecture capable of completing the memory address calculation and prefetching functions is constructed. The prefetch instruction of the x86 architecture is replaced with a corresponding ARM instruction or instruction sequence to complete the dynamic conversion of the instruction, thereby realizing the conversion of the prefetch instruction of the complex address mode under the x86 architecture and improving the reliability of the execution of the executable file in the dynamic instruction conversion mode.

The invention relates to the technical field of cross-platform software transplantation, in particular to a migration adaptation method for regional numerical weather forecast software. According to the method, through the software adaptation step, the problem of compatibility of an instruction set and a system environment when existing regional numerical weather forecast software migrates from an X86 architecture to an ARM architecture is solved, and native operation of the regional numerical weather forecast software on a domestic platform is achieved; through a containerization packaging step, software and a complete dependency environment thereof are packaged into a standard mirror image, so that one-time construction and deployment at any place are realized, and the problem of deployment complexity in different operating system environments is thoroughly solved; through the verification step, containerized software is operated, strict cross-platform comparison testing is carried out, prediction precision is quantitatively evaluated, service functions are ensured to be complete, results are reliable, and key technical support is provided for autonomous controllable and safe sustainable development of a meteorological core service system.

The invention discloses a rail transit intelligent control bottom layer method and system based on an ARM architecture, and relates to the technical field of rail transit, and the key points of the technical scheme comprise the following steps: obtaining equipment operation parameters of a rail transit subway gate and ARM architecture control node information, constructing a gate intelligent control bottom layer framework according to the equipment operation parameters and the ARM architecture control node information; the gate intelligent control bottom layer framework comprises a parameter reference area, an internet of things interaction area and a control execution area; wherein the parameter reference area comprises gate machine standard operation parameters and parameter weight coefficients; the Internet of Things interaction area comprises an equipment interaction characteristic factor and a data transmission diagnosis factor; the method comprises the following steps: acquiring real-time sensing data of a subway turnstile through an ARM architecture intelligent traffic Internet of Things service, and obtaining a real-time operation factor of the turnstile according to the real-time sensing data; the method has the effect of realizing accurate and intelligent regulation and control of the gate.

The present invention discloses an embedded people counting method and system based on a dual-model architecture, wherein the embedded people counting method based on the dual-model architecture comprises the following steps: S1, construction of a first model and a second model, S2, person detection using the first model, and S3, person counting using the second model; the present invention implements low-power, low-cost embedded system edge computing by designing a lightweight model and deploying it in an ARM architecture MCU. The system completes data processing and calculation locally, avoiding data uploading to a cloud server, thereby effectively improving data security; in addition, the present invention adopts a dual-model construction, so that the system uses the first model for person detection in an unmanned state, realizes rapid reasoning, significantly reduces the ineffective consumption of computing resources, and further reduces overall power consumption.

The invention discloses a self-adaptive bridge section pneumatic shape adjusting device and a control method thereof, and belongs to the technical field of large-span bridge pneumatic control. The device comprises a wind regime monitoring module, a wind regime control module, a deformable pneumatic adjustment module and a power module, and dynamic self-adaptive adjustment of the pneumatic profile is achieved through cooperative work. The wind regime monitoring module collects wind field and bridge vibration data by using a three-dimensional ultrasonic anemometer and an accelerometer; the control module integrates FFT, TDNN algorithms and a pneumatic optimization agent model based on an ARM architecture, extracts characteristic parameters, identifies a vibration state and outputs an optimal control instruction; the deformable pneumatic adjusting module optimizes the streaming form through a guide plate (angle adjustment from-30 degrees to + 30 degrees) and a stabilizing plate (0-0.20 D lifting adjustment); the power supply module adopts solar energy and storage battery hybrid power supply to guarantee reliability. According to the control method, closed-loop control is achieved through data collection, processing analysis, adjustment execution and feedback iteration, wind-induced vibration is effectively restrained, and the wind-resistant safety and economical efficiency of the bridge are improved.

This utility model relates to the field of computer equipment technology, and in particular to an integrated multi-USB remote access server chassis based on ARM architecture. It includes a casing and a heat dissipation assembly installed inside the casing. The casing includes a PCB board, power supply, USB port group, indicator light board, gigabit Ethernet port, and power socket. The heat dissipation assembly includes small heat dissipation vents on the back of the outer wall of the casing and large heat dissipation vents on both sides of the outer wall. Small cooling fans are bolted to the inside of the small heat dissipation vents, and water-cooling components are installed inside the large heat dissipation vents. This utility model, through the dual heat dissipation design of "small heat dissipation vents + small cooling fans" and "large heat dissipation vents + water-cooling components," forms a three-dimensional and efficient heat dissipation system, ensuring that the overall temperature of the chassis remains within a reasonable range, significantly improving the stability of server operation, and extending the service life of the equipment.

The invention relates to the technical field of computers, and discloses a clock synchronization method, system and device and a medium. The clock synchronization method is applied to a virtualization system based on an ARM architecture, the virtualization system comprises a host machine and a virtual machine, and the method comprises the following steps: deploying a clock synchronization drive in the virtual machine; deploying an HVC interface in a host machine; and acquiring current time data from the host machine based on the clock synchronization drive and the HVC interface, and synchronizing the current time data to a system clock of the virtual machine. Through the scheme of the invention, the problems of delay and error caused by network transmission and software processing are solved, and the precision and efficiency of clock synchronization of the virtual machine in a virtualization environment can be improved.

The present invention discloses an optimization method for instruction conversion context switching based on stack frame hierarchical compression. An executable file is loaded and executed in a dynamic instruction conversion manner. For instructions related to context switching, a set of save instructions and a set of restore instructions that include the complete process of context switching are established. In the set of save instructions, register groups are constructed according to the correlation degree of registers to achieve the combined storage of register data in continuous memory space in the ARM architecture. The stack data is hierarchically compressed according to the function call hierarchy. In the set of restore instructions, the restoration of register data and stack data is realized according to the mapping relation table and association relation table recorded during the save process, improving the flexibility in processing complex nested structures and data types and ensuring the correct execution of the program.

The invention discloses an intelligent integrated disaster recovery method and system, and the method comprises the steps: accessing a device of an X86 architecture and a device of an ARM architecture, and calling a control interface corresponding to each device in a preset heterogeneous device driver library; accessing a computing resource Computeri, a storage resource Storagei and a network resource Networki of each piece of equipment i through the control interface, and constructing a heterogeneous resource pool (ResourcePool); the method comprises the following steps: virtualizing each resource in a resource pool into a standardized resource unit based on a software defined storage and software defined network technology; extracting attribute parameters for each resource unit j to form a resource identification tuple Rj corresponding to the resource unit j, and constructing a uniform resource abstract view table VRDL = [R1, R2, R3,..., Rj,...]; service data synchronization is carried out based on the constructed resources, the service load is monitored for each resource unit j, and the resource load index Wt at the time t is calculated; and when the Wt exceeds a preset threshold value Threshold, triggering a disaster recovery prompt and executing a disaster recovery switching operation by using the VRDL.

The invention discloses a self-adaptive self-checking method, device and equipment for a single-core MCU based on an ARM architecture and a medium, and the method comprises the steps: executing power-on self-checking in a starting stage of the MCU, and carrying out the initialization detection of a core component of the MCU; in the MCU operation stage, working condition data of the MCU are obtained in real time, and the working condition data comprise load information representing the working state of the MCU and environment information representing external environment conditions; dynamically adjusting a detection strategy of on-line self-inspection according to the working condition data, wherein the detection strategy comprises a trigger period of on-line self-inspection, a detection component range and a detection priority of each component; and executing the online self-inspection according to the adjusted detection strategy. Compared with the prior art, by sensing the working condition information of the MCU in real time and dynamically adjusting the self-checking strategy, full-life-cycle intelligent self-checking with high reliability and high operation efficiency is achieved.

The embodiment of the application discloses a heterogeneous chip starting method, a heterogeneous chip, a system on chip and computer equipment, and belongs to the chip field. The heterogeneous chip comprises a first processor core and a second processor core, the first processor core is a RISC-V architecture processor core, and the second processor core is an ARM architecture processor core. The method comprises the following steps: running a first starting firmware stored in a first starting address through the first processor core; and running a second starting firmware stored in a second starting address through the second processor core. The first starting firmware and the second starting firmware are different firmwares obtained by cross-compiling the same starting firmware, the first starting firmware supports the RISC-V architecture, and the second starting firmware supports the ARM architecture. The application saves the workload, effectively reduces the development cost, transplantation difficulty and maintenance cost of the starting firmware, and also reduces the research and development cycle and difficulty of the heterogeneous chip.