518 results about "Static random-access memory" patented technology

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

The invention belongs to the field of hardware neural network design, and particularly discloses a CMOS-based attractor recurrent neural network system and an implementation method thereof.A neuron calculation module receives an external input high-level signal and generates an initial synaptic high-level signal; integration and activation calculation are carried out based on the current output by the synaptic calculation module, and whether a synaptic high-level signal is generated or not is determined according to an activation state; the synaptic storage module writes the non-zero weight into a synaptic weight SRAM (Static Random Access Memory) array; the synaptic calculation module performs product operation on the synaptic high-level signal and the synaptic weight in the synaptic weight SRAM array, and outputs current; when the STDP updating module is in a neuron training mode, the STDP updating module updates the synaptic weight SRAM array according to the synaptic high-level signal; and the group state module outputs a neuron sequence number corresponding to the maximum activation frequency. A cyclic connection structure of the attractor neural network is formed, and the real-time cognitive behavior requirement of the brain is met.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The invention discloses a collaborative authentication method of a safety U disk, which comprises the following steps of: when the safety U disk is inserted into a host for the first time, executing a set read-write sequence on a flash memory storage array of the safety U disk, and acquiring a PUF (Physical Unclonable Function) site of the safety U disk; reading a power-on initial state image of an SRAM (Static Random Access Memory) of an internal controller of the safe USB flash disk when the safe USB flash disk is powered on, and carrying out Hash abstract processing to generate a controller fingerprint abstract of the safe USB flash disk; when the security USB flash disk is authenticated, the host randomly generates a random number, maps the random number into a PUF bit address index and generates a PUF response of the security USB flash disk; combining the controller fingerprint abstract and the PUF response of the secure USB flash disk to obtain a session key; and realizing cooperative authentication of the secure USB flash disk according to the session key. The invention also discloses a system for realizing the collaborative authentication method of the safety USB flash disk. According to the invention, cooperative authentication of the safe USB flash disk is realized, and the reliability is higher and the safety is better.

The invention belongs to the field of computer system structures and artificial intelligence accelerators, and discloses a software and hardware collaborative heterogeneous storage computing accelerator oriented to full-chip DLRM reasoning. A control domain composed of a static random access memory and an embedded dynamic random access memory, an on-chip storage domain, an in-memory computing domain and an on-chip computing domain are integrated in the same chip, an embedded table is compressed by introducing a hierarchical clustering quantization frame, and a dynamic storage management strategy of access frequency perception is combined. The embedded access path is shortened, and the bandwidth requirement is reduced. According to the method, the reasoning process of the whole set of DLRM can be independently completed, and the memory access overhead in a traditional terminal SoC is remarkably reduced by reducing cross-domain data migration between the calculation unit and the storage unit, so that the model reasoning performance and energy efficiency are improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention relates to the technical field of electric digital data processing, and discloses a solid state disk controller circuit and a solid state disk. The controller circuit comprises a physical unclonable function unit based on an SRAM (Static Random Access Memory), which is used for dynamically generating a stable hardware trust root key during power-on; the secure boot and firmware decryption engine is used for deriving a firmware decryption authentication key and a data key packaging key by using the key, and carrying out decryption and integrity verification on the encrypted firmware; the runtime firmware execution monitoring unit is used for detecting illegal jump in real time and triggering safe shutdown through a hardware-level control flow diagram; and the dynamic data encryption key management unit recovers the plaintext data key and sends the plaintext data key to the encryption engine only during operation, and power failure disappears. By means of the scheme, end-to-end security protection of firmware and data is achieved, and the risks of static key leakage and firmware tampering are eradicated.

The invention provides a memory allocation method and device, electronic equipment, a storage medium and a chip. The method comprises the following steps: extracting tensor data of each tensor in a kernel program; constructing a control flow diagram according to the kernel program; allocating first address information in a static random access memory for each piece of tensor data; determining an active path of each tensor according to the control flow graph, the active path comprising a first node involving the tensor; an interferogram of the tensors is constructed according to the active path, each second node in the interferogram represents a different tensor, and edges between the second nodes represent an interference relation between the tensors; the first address information of each piece of tensor data is adjusted according to the interferogram, the second address information of each piece of tensor data is obtained, and in different steps of the kernel program, if no interference relation exists between the two tensors, the storage areas of the two pieces of tensor data are reused. According to the invention, the memory reuse rate can be improved.

A semiconductor device according to the present disclosure includes a first transistor and a second transistor sharing a first source / drain feature, a third transistor and a fourth transistor sharing a second source / drain feature, a first source / drain contact disposed over the first source / drain feature, a second source / drain contact disposed over the second source / drain feature, a first backside via disposed below the first source / drain feature, and a second backside via disposed below the second source / drain feature. A gate structure of the first transistor is coupled to the second source / drain contact and a gate structure of the fourth transistor is coupled to the first source / drain contact.

A semiconductor device includes a first source / drain feature on a front side of a substrate. The device includes a first backside metal line under the first source / drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source / drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source / drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

The invention discloses a laser projection control method and a distributed control device. The laser projection control method comprises the following steps: step 1, designing a first control board card for galvanometer control; the first control board card comprises a first main control chip for realizing real-time calculation, a static random access memory for external memory expansion, a differential driving chip for transmitting a galvanometer control signal and a chip for realizing an independent communication system; 2, designing a second control board card for laser control, focal length control and temperature monitoring; and the second control board card comprises a second main control chip for realizing real-time calculation, a motor driving chip for driving a motor to move the lens to control the focal length, a laser control circuit amplifier chip and a thermistor. According to the invention, the effect of cooperative control of the laser and the galvanometer is realized.

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and / or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass- gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.

A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled models—from another, but same, sequence that was previously invoked—are not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses an anti-radiation SPH-14T SRAM (Static Random Access Memory) circuit and an anti-radiation SPH-14T SRAM chip combining polarity reinforcement and source isolation technologies, which are designed by adopting a polarity reinforcement principle that transistors of the same type have a single flip characteristic under spatial heavy ion bombardment, and the stability of redundant nodes S0 and S1 is ensured by utilizing the design method. And therefore, the anti-overturning capability of nodes in the circuit is enhanced. Secondly, the stability of a node Q and a node QB is improved through multiplexing of a pull-up PMOS tube and the source isolation technology, meanwhile, the circuit uses four transmission transistors for reading and writing, in the data writing process, a bit line writes data into an internal node QQB and an internal node S0S1 at the same time through transmission transistors N7, N8, N9 and N10, so that the data is more easily written into a storage node, and the stability of the storage node is improved. Therefore, the design greatly improves the data writing speed and noise margin (SNM) of the unit, and a simulation result shows that compared with the existing five SRAM units, the SPH-14T unit disclosed by the invention has more prominent advantages in the writing speed aspect and the noise margin aspect compared with other five SRAMs.

The invention discloses an SRAM (Static Random Access Memory) verification method, system and equipment, relates to the technical field of integrated circuits, and is used for solving the problems of low code reuse rate, long verification period and difficulty in defect positioning in the existing SRAM verification method. The method comprises the following steps: setting a unified virtual shell program module for a to-be-verified SRAM memory module, and packaging key attribute information of the to-be-verified SRAM memory module through macro definition parameters; distributing a serial number for the SRAM type of each SRAM memory module to be verified, and establishing a mapping relation between the serial number and the interface module; calling a corresponding excitation signal from an excitation signal library according to the serial number, and determining a corresponding target interface module through a mapping relation; and connecting a virtual shell program module of the SRAM module to be verified through the target interface module, sending an excitation signal, and triggering function verification. According to the technical scheme provided by the invention, high efficiency, compatibility and expansibility of verification can be realized, and the accuracy of a verification result is improved.

Apparatus and method for a low-power quantum controller. For example, one embodiment of an apparatus comprises: a low-power quantum control chip to process a first portion of quantum program code associated with a quantum computing application, the low-power quantum control chip configurable within a dilution refrigeration unit, the low-power quantum control chip comprising: an interface to couple the quantum control chip to a computer which is to execute a second portion of the quantum program code associated with the quantum computing application; a Static Random Access Memory (SRAM) to store the first portion of quantum program code; a compute unit to execute the first portion of quantum program code during execution of the quantum computing application and responsively generate control signals; routing hardware logic to route the control signals; a plurality of digital signal processor (DSP) units coupled to the routing hardware logic, at least one DSP of the plurality of DSPs to receive one or more of the control signals and responsively generate analog qubit control signals to control qubits of a quantum processor.

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.