998 results about "Static random-access memory" patented technology

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention discloses a number-theory transformation structure of concurrency constant geometry, which uses two polynomial storage blocks to store polynomials, namely a left storage block MembL and a right storage block MembR, each of the left storage block MembL and the right storage block MembR consists of four 1024 * 24 single-port SRAMs (Static Random Access Memory), and n is an integer multiple greater than or equal to 16; and parallel computing of the two butterfly arithmetic units is realized through the four multiplexers, and position transformation of input and output data of the BFU is controlled. To be compatible with multiple algorithms, there is a need for an additional number-theoretical transform constant memory to store a pre-computed twiddle factor to provide a required twiddle factor access bandwidth. According to the method, data independence between polynomial storage blocks is utilized, a modular arithmetic unit of a two-concurrence BFU is designed, and the polynomial multiplication performance is improved by more than one time under the condition that the area increase is limited.

A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention relates to a multi-bit data in-memory computing array structure, an SRAM (Static Random Access Memory) and electronic equipment, and the multi-bit data in-memory computing array structure is used for determining a multiply-accumulate result of five-bit input and five-bit weight, and comprises a plurality of columns of multi-bit data in-memory computing arrays, the core of the multi-bit data in-memory calculation array is characterized in that a calculation result is represented through the pulse width adjustment amount of a reference signal, and the pulse width adjustment amount can be accumulated, so that when the multiplication and accumulation calculation of five-bit input and five-bit weight needs to be realized, the calculation result is more accurate; the multi-column multi-bit data in-storage calculation array is combined in a row form, and the reference signal output by each voltage-controlled time delay circuit in the previous column is the reference signal received by the corresponding voltage-controlled time delay circuit in the next column, so that the reference signal output by each voltage-controlled time delay circuit in the next column is converted into the reference signal received by the corresponding voltage-controlled time delay circuit in the next column. The problem that an existing nonvolatile in-memory calculation circuit generally only supports single-bit input and weight multiply-accumulate in-memory calculation and only can provide limited system-level reasoning precision is solved.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The invention discloses a lightweight identity authentication and key exchange scheme based on an SRAM (Static Random Access Memory) PUF (Physical Unclonable Function) in an Internet of Vehicles environment. The lightweight identity authentication and key exchange scheme comprises the following steps: (1) a one-time registration stage: a vehicle unit (OBU) transmits static random access memory (SRAM) information and identity (ID) information serving as fingerprints to a roadside unit (RSU) under a safe condition; and (2) an identity authentication stage: the OBU and the RSU verify each other through dynamic identity authentication. And the OBU sends a challenge value, the RSU generates a response value by using the stored SRAM fingerprint, and the OBU verifies the identity of the RSU by confirming the correctness of the response value. Then, the RSU generates a new challenge value, the OBU generates and sends a response value through the SRAM PUF, the RSU verifies and confirms the OBU identity, and therefore bidirectional authentication is completed; and (3) key generation: after identity authentication is completed, the OBU and the RSU generate a secure session key through Hash operation. The secret key is used for subsequent encryption communication, and the integrity and confidentiality of data in the transmission process are ensured. The new key generated by each communication session further enhances the security of the system.

The invention discloses a large model chip decoding stage reasoning optimization method under a long context, and the method comprises the following steps: 1, carrying out the dynamic slicing of KV cache data and model parameters in a decoding stage, and enabling the KV cache data and model parameters to be called by a static random access memory (SRAM); step 2, a QKV module, a self-attention module, an attention project module and an FFN module are loaded and calculated in sequence in parallel, and the QKV module, the self-attention module, the attention project module and the FFN module are loaded and calculated in sequence; carrying out residual error connection processing after the loading calculation of the attention project and the FFN module, and carrying out the residual error connection processing after the loading calculation of the attention project and the FFN module; and step 3, completing the whole reasoning calculation. The invention further discloses a reasoning optimization system for implementing the reasoning optimization method and corresponding application, and the reasoning optimization system and the corresponding application have wide application scenarios.

The embodiment of the invention discloses a static random access memory in-memory computing system and method, and the system comprises a feature memory which is used for storing an input signal of a neural network model; the SRAM storage array is used for storing each weight of the neural network model and performing logical operation on an input signal and each weight to obtain a plurality of logical operation results, each weight is divided into a plurality of binary blocks after CSD coding, complementary mode blocks are reserved after processing of eliminating all-zero mode blocks, and each binary block is divided into a plurality of binary blocks; after information is extracted from each complementary mode block, an index, a symbol and a value are obtained, and each weight is stored in a complementary mode block mode; the metadata storage is used for storing indexes and symbols; the adder tree is used for performing decoding and additive operation on the plurality of logical operation results according to the indexes and the symbols; the shift accumulation unit is used for performing shift accumulation on the addition result; and the post-processing unit is used for post-processing the shift accumulation result to obtain an output signal of the neural network model.

The invention provides an on-chip and off-chip collaborative triple modular redundancy in-memory computing system, a chip and a satellite. The on-chip and off-chip collaborative triple modular redundancy in-memory computing system comprises an on-chip unit and an off-chip unit, the on-chip unit comprises an SRAM (Static Random Access Memory), a Hamming code decoding circuit and an in-memory calculation core; the Hamming code decoding circuit is used for checking and correcting 1-bit errors of weights and characteristic values in the SRAM and the in-memory calculation core; the off-chip unit comprises a FLASH and a triple modular redundancy voter; the FLASH stores original weights and characteristic values, multi-bit error checking is carried out through the Hamming code decoding circuit, correct data are read from the Flash through the triple modular redundancy voter, and the correct data are transmitted to the SRAM. Through the innovative multi-stage error correction design and the triple modular redundancy technology, the accuracy of neural network calculation and the reliability of the system can still be ensured in the face of multi-bit errors, the robustness of the in-memory calculation system is remarkably improved, and the calculation requirements of high energy efficiency, low power consumption and high reliability are met.

The invention provides a complete hardware K-SAT solver based on a dual-path macro array, the macro array comprises M * N processing units, the processing unit in the ith row corresponds to the ith clause of a Boolean formula, the processing unit in the ith row and the jth column is used for storing the jth variable in the ith clause, each processing unit comprises a static random access memory (SRAM) unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit and a K-SAT unit, the representation module is used for representing appearance forms of variables in clauses; the forward in-memory calculation unit is connected with one end of the SRAM unit and is used for deriving a clause state based on the variable assignment and the variable appearance form represented by the SRAM unit; and the backward index unit is connected with the other end of the SRAM unit and is used for reading all unassigned characters in the activation clause set so as to support updating of variable assignment. According to the method, a bidirectional derivation function from assignment to clause state and from clause state to assignment is realized, and a high-performance and low-energy-consumption hardware solution is provided for integrity analysis of a complex SAT problem.

The invention discloses a heterogeneous Chiplet hybrid precision Transformer acceleration system based on an MRAM-SRAM (Magnetic Random Access Memory-Static Random Access Memory), which adopts a Chiplet block integration technology, gives full play to the modularization advantages of high yield and low cost of the Chiplet block integration technology, and internally integrates two types of heterogeneous calculation cores of MRAM calculation Chiplet and SRAM-NPU calculation Chiplet and two types of scheduling management Chiplet and data interaction Chiplet control units. In a Transform calculation process, an MRAM (Magnetic Random Access Memory) calculates a Chiplet to carry out approximate token relationship prediction in a self-attention mechanism, an SRAM-NPU (Synchronous Random Access Memory-Network Processing Unit) calculates the Chiplet to realize accurate attention calculation by utilizing a high-speed read-write characteristic of an SRAM (Static Random Access Memory) and a flexible calculation capability of the NPU, meanwhile, a scheduling management Chiplet coordinates calculation task allocation, and a data interaction Chiplet ensures efficient data flow; according to the acceleration system, optimal combination of different process node devices is realized through a Chiplet heterogeneous integration technology, and three dimensions of calculation efficiency, energy consumption and precision are balanced by combining the high-density low-power-consumption storage and calculation integrated advantage of an MRAM and high-precision calculation of an SRAM-NPU.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

The invention relates to a firmware updating method, system and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring a dynamic code and to-be-burnt data; the dynamic code is updated when the system-on-chip is changed; downloading the dynamic code to an SRAM (Static Random Access Memory) of a system-on-chip based on a debugging interface board; the debugging interface board is used for connecting a debugging interface of the system-on-chip to an upper computer and performing data conversion according to a debugging protocol of the debugging interface; based on the debugging interface board, sending a burning instruction to the system-on-chip and downloading the to-be-burnt data to an SRAM (Static Random Access Memory) of the system-on-chip; the dynamic code is used for writing the to-be-burnt data into a FLASH of the system-on-chip in response to the burning instruction. By adopting the method, the firmware updating efficiency and flexibility of the system-on-chip can be improved.

The invention provides a static random access memory mismatch test structure and a test method, the static random access memory mismatch test structure comprises a plurality of rows of ring oscillators with different stages, a decoder and a multiplexer, and the stages of each row of ring oscillators are sequentially increased. The ring oscillator in each row comprises a plurality of first phase inverters connected in series and a plurality of second phase inverters connected in series, the input ends of the plurality of first phase inverters are connected in series with the output ends of the plurality of second phase inverters, each first phase inverter is composed of a first PMOS tube and a first NMOS tube in the storage unit, and each second phase inverter is composed of a second PMOS tube and a second NMOS tube in the storage unit. The first phase inverter is composed of a first PMOS transistor and a first NMOS transistor in the memory cell, the second phase inverter is composed of a second PMOS transistor and a second NMOS transistor in the memory cell, so that the layout area of the static random access memory mismatch test structure is smaller than that of an existing mismatch device test structure, and the area occupied by the static random access memory mismatch test structure is saved.

The invention belongs to the field of hardware neural network design, and particularly discloses a CMOS-based attractor recurrent neural network system and an implementation method thereof.A neuron calculation module receives an external input high-level signal and generates an initial synaptic high-level signal; integration and activation calculation are carried out based on the current output by the synaptic calculation module, and whether a synaptic high-level signal is generated or not is determined according to an activation state; the synaptic storage module writes the non-zero weight into a synaptic weight SRAM (Static Random Access Memory) array; the synaptic calculation module performs product operation on the synaptic high-level signal and the synaptic weight in the synaptic weight SRAM array, and outputs current; when the STDP updating module is in a neuron training mode, the STDP updating module updates the synaptic weight SRAM array according to the synaptic high-level signal; and the group state module outputs a neuron sequence number corresponding to the maximum activation frequency. A cyclic connection structure of the attractor neural network is formed, and the real-time cognitive behavior requirement of the brain is met.

The invention relates to the technical field of integrated circuit chips, and discloses a hardware accelerator for realizing attention weighted summation, which comprises a control module, a dynamic random access memory, a ping-pong static random access memory, a data buffer, an input first-in first-out queue module, an output first-in first-out queue module, a processing unit array, an exp module, an adder tree module and a log2 module, according to the hardware accelerator, by designing a special circuit structure, efficient parallel computing can be achieved, memory access delay is reduced, and therefore the computing speed of attention weighted summation is increased.

The invention discloses an SRAM (Static Random Access Memory)-based ACIM (Access Control Information Module) architecture circuit capable of realizing inter-core interconnection, which consists of a plurality of computing core circuits which are communicated with one another, and each computing core circuit comprises a DPW-CIM macro circuit based on a dual-port parallel weight read (DPW) strategy and a near-memory extensible communication module (NM-eCM) circuit. The DPW-CIM macro circuit performs read and write operations on weights in the storage unit in an SRAM (Static Random Access Memory) mode; and carrying out multi-bit multiplication and addition operation through a dual-port parallel weight reading strategy in the CIM mode. And the NM-eCM circuit realizes an interconnection network between the DPW-CIM macro circuits through a mode of communication between a'priority 'judgment mechanism and an adjacent broadcast. The architecture circuit aims at improving the working efficiency, the data throughput and the general expansibility of the ACIM architecture for accelerating neural network calculation, and is suitable for reasoning acceleration tasks of neural network models of different scales.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

The invention discloses a floating-point number index maximum value searching circuit and an in-memory computing chip. The searching circuit comprises an SRAM (Static Random Access Memory) unit matrix which comprises a plurality of rows and columns of SRAM units, wherein each unit comprises NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N5 and PMOS (P-channel Metal Oxide Semiconductor) tubes P1 and P2; n1, N2, P1 and P2 are in reverse cross coupling to form a pair of storage nodes Q and QB; the grid electrode of the N5 is connected with a node QB; the grid electrode of the N3 in the ith row is connected with a word line WLLlt; igt; the grid electrode of the N4 is connected with a word line WLRlt; igt; ; the drain electrode of each column of N5 is connected in series with the source electrode of the next column of N5, and the source electrode of the first column of N5 is connected with a signal SELlt; igt; the N5 drain electrode of the last column is connected with a signal PRE; in the jth column, N3 is a corresponding node Q and a bit line BLlt; jgt; the transmission tube N4 is a corresponding node QB and a bit line BLBlt; jgt; and a transmission tube. According to the invention, the number of searching cycles is saved, the calculation time is shortened, the subsequent calculation amount is reduced, the efficiency is improved, the power consumption is reduced, and the defects of relatively high power consumption, complex hardware implementation, relatively long calculation delay and the like of an existing circuit are overcome.

The invention discloses a reading static noise margin measurement method of a static random access memory, computing equipment and a storage medium. The method comprises the following steps: acquiring test data of a static random access memory, and extracting test voltage of each chip; carrying out format conversion on the test voltage; and performing curve fitting interpolation on the test voltage after format conversion to obtain a first fitting curve and a second fitting curve, obtaining a fitting curve intersection point for the first fitting curve and the second fitting curve, then calculating the maximum square side length on the curves on the left side and the right side of the intersection point, and further judging the reading static noise margin of the static random access memory. According to the method, the RSNML value and the RSNMR value can be more accurately determined by utilizing curve fitting interpolation and interpolation operation, the dependence on experiences of engineers is reduced, and the estimation error is reduced. According to the method, the automation, the accuracy, the efficiency and the reliability are remarkably improved, and a novel efficient tool is provided for the field of SRAM design and test.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

The embodiment of the invention provides a calculation method and device for elliptic curve encryption scalar multiplication, electronic equipment and a computer readable storage medium, and relates to the technical field of information encryption. The method comprises the following steps: determining a base point G and each group of sub-scalar quantity k on an elliptic curve, wherein each group of sub-scalar quantity k is obtained by coding a scalar quantity K based on a window method; reading a first result Rd corresponding to the actual value of the sub-scalar k from an SRAM (Static Random Access Memory) for each group of sub-scalar; determining a Q point on the elliptic curve according to the first result Rd corresponding to each group of sub-scalar k; wherein the first result Rd corresponding to the actual value of the sub-scalar k is obtained from the preset SRAM, and the method further comprises the following steps of: aiming at each possible value of each group of sub-scalar k, performing scalar multiplication on the base point G and the possible value through a point addition and point doubling operator realized by hardware to obtain the first result Rd corresponding to the possible value, and writing the first result Rd into the SRAM. According to the embodiment of the invention, the scalar multiplication operation efficiency is improved.

A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The invention provides a 10T SRAM (Static Random Access Memory) storage unit applied to a multi-bit storage and calculation integrated multiplication circuit, which comprises a first phase inverter, a second phase inverter, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a first PMOS (P-channel Metal Oxide Semiconductor) tube, the output end of the first phase inverter and the input end of the second phase inverter are connected with the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is controlled by a word line, and the source electrode of the first NMOS tube is connected with the first write-in end; the grid electrode of the second NMOS tube is controlled by the word line, and the source electrode of the second NMOS tube is connected with the second write-in end; the grid electrode of the third NMOS tube is connected with the first storage node, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the third NMOS tube is grounded; the drain electrode of the fourth NMOS tube is connected with the first reading end, and the grid electrode of the fourth NMOS tube is connected with a first control signal. According to the invention, the in-memory calculation of the multi-bit multiplication circuit is realized.

The invention provides a multi-mode aerospace static random access memory irradiation fault diagnosis method and platform, and relates to the technical field of anti-radiation integrated circuit design, and the method comprises the following steps: collecting the voltage, current, electromagnetic wave and temperature data of a to-be-tested device through an analog end circuit module; carrying out data preprocessing based on a digital signal recovery fixed-point decimal algorithm and wavelet transform filtering; the method comprises the following steps: establishing a fault diagnosis system, establishing a reverse neural network and a Pytorch end feedforward neural network, training and testing the neural network through a fault data set, adaptively adjusting the learning rate of each parameter in combination with an Adam algorithm, extracting weight and bias parameters of the trained neural network, transmitting the weight and bias parameters to an FPGA end feedforward neural network, and detecting the diagnosis precision. According to actually measured irradiation fault data, a static random access memory is used as a chip to be detected, and current and voltage parameters in two irradiation fault states of a single event effect and a total dose effect are collected and detected.