337 results about "Static random-access memory" patented technology

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The invention belongs to the field of computer system structures and artificial intelligence accelerators, and discloses a software and hardware collaborative heterogeneous storage computing accelerator oriented to full-chip DLRM reasoning. A control domain composed of a static random access memory and an embedded dynamic random access memory, an on-chip storage domain, an in-memory computing domain and an on-chip computing domain are integrated in the same chip, an embedded table is compressed by introducing a hierarchical clustering quantization frame, and a dynamic storage management strategy of access frequency perception is combined. The embedded access path is shortened, and the bandwidth requirement is reduced. According to the method, the reasoning process of the whole set of DLRM can be independently completed, and the memory access overhead in a traditional terminal SoC is remarkably reduced by reducing cross-domain data migration between the calculation unit and the storage unit, so that the model reasoning performance and energy efficiency are improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention relates to the technical field of electric digital data processing, and discloses a solid state disk controller circuit and a solid state disk. The controller circuit comprises a physical unclonable function unit based on an SRAM (Static Random Access Memory), which is used for dynamically generating a stable hardware trust root key during power-on; the secure boot and firmware decryption engine is used for deriving a firmware decryption authentication key and a data key packaging key by using the key, and carrying out decryption and integrity verification on the encrypted firmware; the runtime firmware execution monitoring unit is used for detecting illegal jump in real time and triggering safe shutdown through a hardware-level control flow diagram; and the dynamic data encryption key management unit recovers the plaintext data key and sends the plaintext data key to the encryption engine only during operation, and power failure disappears. By means of the scheme, end-to-end security protection of firmware and data is achieved, and the risks of static key leakage and firmware tampering are eradicated.

The invention provides a memory allocation method and device, electronic equipment, a storage medium and a chip. The method comprises the following steps: extracting tensor data of each tensor in a kernel program; constructing a control flow diagram according to the kernel program; allocating first address information in a static random access memory for each piece of tensor data; determining an active path of each tensor according to the control flow graph, the active path comprising a first node involving the tensor; an interferogram of the tensors is constructed according to the active path, each second node in the interferogram represents a different tensor, and edges between the second nodes represent an interference relation between the tensors; the first address information of each piece of tensor data is adjusted according to the interferogram, the second address information of each piece of tensor data is obtained, and in different steps of the kernel program, if no interference relation exists between the two tensors, the storage areas of the two pieces of tensor data are reused. According to the invention, the memory reuse rate can be improved.

A semiconductor device includes a first source / drain feature on a front side of a substrate. The device includes a first backside metal line under the first source / drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source / drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source / drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

The invention discloses a laser projection control method and a distributed control device. The laser projection control method comprises the following steps: step 1, designing a first control board card for galvanometer control; the first control board card comprises a first main control chip for realizing real-time calculation, a static random access memory for external memory expansion, a differential driving chip for transmitting a galvanometer control signal and a chip for realizing an independent communication system; 2, designing a second control board card for laser control, focal length control and temperature monitoring; and the second control board card comprises a second main control chip for realizing real-time calculation, a motor driving chip for driving a motor to move the lens to control the focal length, a laser control circuit amplifier chip and a thermistor. According to the invention, the effect of cooperative control of the laser and the galvanometer is realized.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.

A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled models—from another, but same, sequence that was previously invoked—are not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses an SRAM (Static Random Access Memory) verification method, system and equipment, relates to the technical field of integrated circuits, and is used for solving the problems of low code reuse rate, long verification period and difficulty in defect positioning in the existing SRAM verification method. The method comprises the following steps: setting a unified virtual shell program module for a to-be-verified SRAM memory module, and packaging key attribute information of the to-be-verified SRAM memory module through macro definition parameters; distributing a serial number for the SRAM type of each SRAM memory module to be verified, and establishing a mapping relation between the serial number and the interface module; calling a corresponding excitation signal from an excitation signal library according to the serial number, and determining a corresponding target interface module through a mapping relation; and connecting a virtual shell program module of the SRAM module to be verified through the target interface module, sending an excitation signal, and triggering function verification. According to the technical scheme provided by the invention, high efficiency, compatibility and expansibility of verification can be realized, and the accuracy of a verification result is improved.

Apparatus and method for a low-power quantum controller. For example, one embodiment of an apparatus comprises: a low-power quantum control chip to process a first portion of quantum program code associated with a quantum computing application, the low-power quantum control chip configurable within a dilution refrigeration unit, the low-power quantum control chip comprising: an interface to couple the quantum control chip to a computer which is to execute a second portion of the quantum program code associated with the quantum computing application; a Static Random Access Memory (SRAM) to store the first portion of quantum program code; a compute unit to execute the first portion of quantum program code during execution of the quantum computing application and responsively generate control signals; routing hardware logic to route the control signals; a plurality of digital signal processor (DSP) units coupled to the routing hardware logic, at least one DSP of the plurality of DSPs to receive one or more of the control signals and responsively generate analog qubit control signals to control qubits of a quantum processor.

Described herein are memory devices that include a cooling structure for cooling one or more memory arrays. The memory arrays may be static random access memory (SRAM) arrays formed in multiple layers as a stacked memory device. The cooling structure may cool one or more layers of an SRAM device. For example, a cooling structure may be formed around the SRAM device and coupled to a cooling device. Alternatively, a cooling layer may be included in a memory device and coupled to one or more thermal interface layers in thermal contact with a memory layer by cold vias. The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.

The invention discloses a configurable rapid SRAM (Static Random Access Memory) automatic optimization type selection method which comprises the following steps: traversing all parameter specifications, generating all SRAM instances, extracting frequency, area, power consumption and aspect ratio parameters, and constructing an SRAM data lookup table; obtaining an SRAM parameter requirement input by a user and a configurable equalization algorithm parameter; retrieving the SRAM data lookup table based on an SRAM parameter requirement, and screening to obtain an SRAM alternative list I; based on configurable equalization algorithm parameters, inputting the alternative list I into an equalization algorithm, and calculating to obtain an SRAM alternative list II; and taking the SRAM instance with the highest score as a recommendation scheme based on the SRAM alternative list 2. The method has a configurable function, a user can dynamically modify equalization algorithm parameters, multi-dimensional model selection is achieved, and the balance of the area and the power consumption is achieved.

Systems and methods for multi-source hidden-state fusion on edge devices. A processing system executes a state-space model, accesses a vector database in dynamic random-access memory, and maintains model state in on-chip static random-access memory. The system processes document chunks to form hidden states and computes a key for each chunk. Tuples pairing each key with a hidden state are stored in the database. For a received query, the system computes a query key and retrieves tuples by nearest-neighbor search using the stored keys and the query key. A fusion function computes a fused hidden state across the retrieved hidden states. The fused hidden state is loaded as the initialization state. The model processes the query tokens from that state and generates answer tokens as a function of the fused state and the query tokens.

A non-volatile static random-access memory (NVSRAM) device includes at least one array of NVSRAM cells. Each NVSRAM cell includes an SRAM unit and an MRAM unit. The SRAM unit includes at least six transistors, and the MRAM unit includes at least two-transistors and two magnetic tunnel junction (MTJ) structures. The SRAM units are accessed during normal read / write operations to allows for fast access to the NVSRAM cells with unlimited endurance and without read / write error rate issues. Hidden MRAM write operations in NVSRAM cells that are not accessed for normal read / write operations may be activated manually or automatically to back up the data stored in the corresponding SRAM units. When the NVSRAM device loses power, data stored in the SRAM units are lost, while the data backed-up in corresponding MRAM units are retained. When power is restored, an automatic data restore write cycle is started, during which the SRAM units recover their data from their corresponding MRAM units.

The invention belongs to the technical field of integrated circuits, and particularly relates to a self-loading storage unit based on a nonvolatile storage unit and a storage array. The self-loading storage unit comprises an SRAM (Static Random Access Memory) unit structure and a nonvolatile storage structure; the self-loading storage array comprises N rows and N columns of self-loading storage units and N peripheral circuits, the self-loading storage units in the same row share the same word line WL, share the same balance signal line EQ, share the same reset signal line RS, share the same first switching signal STRS and share the same second switching signal STRSN; the self-loading storage units in the same column share the same source line SL, share the same first bit line BL and share the same second bit line BLB; according to the self-loading storage array, the data configured in the configuration storage array circuit cannot be lost after the FPGA is powered down, and the data does not need to be read from an external configuration memory for operation during power-on.

The embodiment of the invention discloses a memory device and a method for forming a semiconductor device. The memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on a first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, in which the first level is disposed vertically with respect to the second level. The first to seventh transistors are operable to form a static random access memory (SRAM) cell.

The utility model provides an SRAM (Static Random Access Memory) unit, an SRAM circuit and a memory, comprising ten MOS (Metal Oxide Semiconductor) tubes, namely M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10; m1, M3, M5, M6, M7, M8 and M10 are NMOS (N-channel Metal Oxide Semiconductor), and M2, M4 and M9 are PMOS (P-channel Metal Oxide Semiconductor). The SRAM cell may be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOS (Metal Oxide Semiconductor) tubes on the basis of the existing 6T SRAM. When the 10T SRAM reads and writes data, the 10T SRAM is similar to an 8T SRAM, and the read-write speed of the 10T SRAM is slightly slower than that of the 8T SRAM, but is higher than that of a 6T SRAM. After the 10T SRAM is combined, the 10T SRAM can be directly used for copying the data, an ALU is not needed when the data is copied, and the speed of copying the data is obviously improved.

A photonic random access memory employs series connected photosensors to define switching nodes driving optical modulators, the series connection operating to reduce the effect of photosensor dark current.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

The application provides a static random access memory structure and a preparation method thereof. The static random access memory structure comprises a substrate, an isolation structure, at least two static random access memory cells sharing a word line, and a plurality of active regions defined by the isolation structure on the substrate. Each static random access memory cell comprises at least two inverter groups and at least two transfer transistor groups. Each inverter group comprises two inverters cross-coupled, each inverter being formed by a pull-up transistor and a pull-down transistor stacked in the same active region along the vertical direction of the substrate. The plurality of active regions comprises at least two common regions shared by different static random access memory cells. Each transfer transistor group is formed by two transfer transistors stacked in the same common region along the vertical direction of the substrate, and the two transfer transistors in the same common region belong to different static random access memory cells. Thus, the coupled two static random access memory cells save 50% of the area.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

The invention relates to the field of chip design, in particular to an automatic SRAM (Static Random Access Memory) configuration method and system based on dynamic adjustment and interpolation calculation. The method comprises the following steps: firstly, confirming a configuration requirement and generating a matching item, searching a record completely matched with the matching item in a reference table, if the record is found, reading a minimum period corresponding to the record, judging whether the minimum period meets the requirement, if so, passing the configuration and generating an SRAM, otherwise, based on historical data points in the reference table, determining that the configuration is successful. Calculating the minimum period corresponding to the configuration requirement by using linear interpolation, judging whether the minimum period meets the requirement or not, generating the SRAM if the minimum period meets the requirement, otherwise, splitting the width or depth according to the priority, calculating the minimum period corresponding to the split width or depth, stopping splitting until the minimum period meets the requirement, and generating the SRAM according to the current width and depth. According to the invention, efficient and accurate SRAM configuration can be realized, and especially, the optimal configuration can be automatically selected in the face of technical node change.