683 results about "Static random-access memory" patented technology

The invention relates to the technical field of SRAM (Static Random Access Memory) memory anti-radiation testing, and discloses an SRAM memory anti-radiation testing method and system based on running state injection, and the method comprises the following steps: system initialization, mapping preparation and time sequence baseline establishment; carrying out model quantitative compiling, sensitivity analysis and physical bit candidate generation; generating a running state injection plan and loading a test case; performing operation state execution, disturbance injection and synchronous monitoring acquisition; multi-source triggering, weight read-back and fault decoupling judgment are carried out; and performing quantitative evaluation on anti-radiation performance, constructing a degradation curve and outputting a report. The system corresponds to the method. According to the invention, a hardware-in-the-loop operation state injection and online evaluation technology is constructed, and the technical problems of guidance and position limited disturbance / equivalent irradiation injection based on weight bit level sensitivity and logic-physical mapping are solved.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The invention discloses a large model chip decoding stage reasoning optimization method under a long context, and the method comprises the following steps: 1, carrying out the dynamic slicing of KV cache data and model parameters in a decoding stage, and enabling the KV cache data and model parameters to be called by a static random access memory (SRAM); step 2, a QKV module, a self-attention module, an attention project module and an FFN module are loaded and calculated in sequence in parallel, and the QKV module, the self-attention module, the attention project module and the FFN module are loaded and calculated in sequence; carrying out residual error connection processing after the loading calculation of the attention project and the FFN module, and carrying out the residual error connection processing after the loading calculation of the attention project and the FFN module; and step 3, completing the whole reasoning calculation. The invention further discloses a reasoning optimization system for implementing the reasoning optimization method and corresponding application, and the reasoning optimization system and the corresponding application have wide application scenarios.

The invention provides an on-chip and off-chip collaborative triple modular redundancy in-memory computing system, a chip and a satellite. The on-chip and off-chip collaborative triple modular redundancy in-memory computing system comprises an on-chip unit and an off-chip unit, the on-chip unit comprises an SRAM (Static Random Access Memory), a Hamming code decoding circuit and an in-memory calculation core; the Hamming code decoding circuit is used for checking and correcting 1-bit errors of weights and characteristic values in the SRAM and the in-memory calculation core; the off-chip unit comprises a FLASH and a triple modular redundancy voter; the FLASH stores original weights and characteristic values, multi-bit error checking is carried out through the Hamming code decoding circuit, correct data are read from the Flash through the triple modular redundancy voter, and the correct data are transmitted to the SRAM. Through the innovative multi-stage error correction design and the triple modular redundancy technology, the accuracy of neural network calculation and the reliability of the system can still be ensured in the face of multi-bit errors, the robustness of the in-memory calculation system is remarkably improved, and the calculation requirements of high energy efficiency, low power consumption and high reliability are met.

The invention provides a complete hardware K-SAT solver based on a dual-path macro array, the macro array comprises M * N processing units, the processing unit in the ith row corresponds to the ith clause of a Boolean formula, the processing unit in the ith row and the jth column is used for storing the jth variable in the ith clause, each processing unit comprises a static random access memory (SRAM) unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit, a K-SAT unit and a K-SAT unit, the representation module is used for representing appearance forms of variables in clauses; the forward in-memory calculation unit is connected with one end of the SRAM unit and is used for deriving a clause state based on the variable assignment and the variable appearance form represented by the SRAM unit; and the backward index unit is connected with the other end of the SRAM unit and is used for reading all unassigned characters in the activation clause set so as to support updating of variable assignment. According to the method, a bidirectional derivation function from assignment to clause state and from clause state to assignment is realized, and a high-performance and low-energy-consumption hardware solution is provided for integrity analysis of a complex SAT problem.

The invention discloses a heterogeneous Chiplet hybrid precision Transformer acceleration system based on an MRAM-SRAM (Magnetic Random Access Memory-Static Random Access Memory), which adopts a Chiplet block integration technology, gives full play to the modularization advantages of high yield and low cost of the Chiplet block integration technology, and internally integrates two types of heterogeneous calculation cores of MRAM calculation Chiplet and SRAM-NPU calculation Chiplet and two types of scheduling management Chiplet and data interaction Chiplet control units. In a Transform calculation process, an MRAM (Magnetic Random Access Memory) calculates a Chiplet to carry out approximate token relationship prediction in a self-attention mechanism, an SRAM-NPU (Synchronous Random Access Memory-Network Processing Unit) calculates the Chiplet to realize accurate attention calculation by utilizing a high-speed read-write characteristic of an SRAM (Static Random Access Memory) and a flexible calculation capability of the NPU, meanwhile, a scheduling management Chiplet coordinates calculation task allocation, and a data interaction Chiplet ensures efficient data flow; according to the acceleration system, optimal combination of different process node devices is realized through a Chiplet heterogeneous integration technology, and three dimensions of calculation efficiency, energy consumption and precision are balanced by combining the high-density low-power-consumption storage and calculation integrated advantage of an MRAM and high-precision calculation of an SRAM-NPU.

The invention provides a power consumption feature extraction method and system for a static random access memory standard cell library, electronic equipment and a storage medium, and the method comprises the steps: S1, reading a standard cell model file, a standard cell netlist and a standard cell time sequence path of a static random access memory, and constructing and generating an excitation waveform description file; s2, establishing a simulation file of the static random access memory standard unit, simulating the static random access memory standard unit, and respectively obtaining electrical characteristic data of an input pin and an output pin of the static random access memory standard unit; s3, analyzing the electrical characteristic data of the static random access memory standard unit, and obtaining a short-circuit power consumption time sequence path and a switching power consumption time sequence path existing in the static random access memory standard unit; and S4, respectively calculating power consumption values of each switching power consumption time sequence path and each short-circuit power consumption time sequence path. According to the method, the power consumption characteristics of the SRAM standard cell are extracted in the design stage of the standard cell library, and the precision and efficiency of power consumption analysis can be improved.

The invention belongs to the field of hardware neural network design, and particularly discloses a CMOS-based attractor recurrent neural network system and an implementation method thereof.A neuron calculation module receives an external input high-level signal and generates an initial synaptic high-level signal; integration and activation calculation are carried out based on the current output by the synaptic calculation module, and whether a synaptic high-level signal is generated or not is determined according to an activation state; the synaptic storage module writes the non-zero weight into a synaptic weight SRAM (Static Random Access Memory) array; the synaptic calculation module performs product operation on the synaptic high-level signal and the synaptic weight in the synaptic weight SRAM array, and outputs current; when the STDP updating module is in a neuron training mode, the STDP updating module updates the synaptic weight SRAM array according to the synaptic high-level signal; and the group state module outputs a neuron sequence number corresponding to the maximum activation frequency. A cyclic connection structure of the attractor neural network is formed, and the real-time cognitive behavior requirement of the brain is met.

Methods, systems, and devices for low latency logical (L3A) unit for a memory system are described. For example, a logical unit, such as an L3Alogical unit or L3A logical unit number (LUN), may include a storage area for storing information for system swap operations, including, for example, a logical-block-address (LBA) range for one or more single-level-cells (SLCs). The logical unit may include a logical-to-physical (L2P) mapping table stored in a local memory of a memory system controller, such as in static random access memory (SRAM). In some examples, a reserved storage area may be overprovisioned, and the logical unit may be associated with a higher priority and a larger granularity than one or more other logical units. Further, one or more read-only (RO) descriptors stored to one or more registers, one or more provisioning parameters, or both, may be defined for the logical unit.

Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

The invention discloses a floating-point number index maximum value searching circuit and an in-memory computing chip. The searching circuit comprises an SRAM (Static Random Access Memory) unit matrix which comprises a plurality of rows and columns of SRAM units, wherein each unit comprises NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N5 and PMOS (P-channel Metal Oxide Semiconductor) tubes P1 and P2; n1, N2, P1 and P2 are in reverse cross coupling to form a pair of storage nodes Q and QB; the grid electrode of the N5 is connected with a node QB; the grid electrode of the N3 in the ith row is connected with a word line WLLlt; igt; the grid electrode of the N4 is connected with a word line WLRlt; igt; ; the drain electrode of each column of N5 is connected in series with the source electrode of the next column of N5, and the source electrode of the first column of N5 is connected with a signal SELlt; igt; the N5 drain electrode of the last column is connected with a signal PRE; in the jth column, N3 is a corresponding node Q and a bit line BLlt; jgt; the transmission tube N4 is a corresponding node QB and a bit line BLBlt; jgt; and a transmission tube. According to the invention, the number of searching cycles is saved, the calculation time is shortened, the subsequent calculation amount is reduced, the efficiency is improved, the power consumption is reduced, and the defects of relatively high power consumption, complex hardware implementation, relatively long calculation delay and the like of an existing circuit are overcome.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

The invention discloses an SRAM (Static Random Access Memory) memory cell, a static random access memory and a preparation method thereof, and belongs to the field of semiconductors. Channel directions of two transmission gate transistors are set as a first direction, channel directions of two pull-up transistors are set as a second direction, and channel directions of two pull-down transistors are set as a third direction; the third direction and the first direction are crystal orientations of the same family, and the two pull-up transistors are arranged in a sinking manner; active regions of the pull-up transistor and other transistors are staggered so as to improve the heat dissipation capability; in order to manufacture the structure, a corresponding preparation method is designed, in the preparation process, the grid electrode of the pull-up transistor is stepped, so that the grid electrode of the pull-up transistor can be connected with the active region of the transmission grid transistor through a metal silicification technology, the contact resistance is greatly reduced, and the performance of the device is improved. Therefore, the performance of the whole device is improved, and the read-write speed is higher than that of the prior art under the same condition.

The embodiment of the invention provides a photoelectric Transform accelerator cooperation method and device, and aims to efficiently process Transform model calculation. Firstly, according to the size M of an optical chip static random access memory on an optical computing chip and feature dimensions d of a query matrix Q, a key matrix K and a value matrix V, Q is divided into Tr sub-blocks, and K and V are respectively divided into Tc sub-blocks. Then, the universal computing chip and the optical computing chip are in interactive communication, the jth sub-block of K and V is transmitted to the optical computing chip firstly, and then the ith sub-block of Q is transmitted circularly for the sub-block. The optical computing chip computes a local attention score matrix Sij and then transmits the matrix back, the general computing chip carries out nonlinear processing on the matrix to obtain a local attention weight matrix Pij, the maximum value mij of each row of the Sij and the sum lij of each row of the Pij are computed, and m, l and O are updated until all sub-blocks K and V are processed. According to the method, through photoelectric collaboration and block calculation, resource utilization is optimized, and calculation efficiency is improved.

The invention discloses a collaborative authentication method of a safety U disk, which comprises the following steps of: when the safety U disk is inserted into a host for the first time, executing a set read-write sequence on a flash memory storage array of the safety U disk, and acquiring a PUF (Physical Unclonable Function) site of the safety U disk; reading a power-on initial state image of an SRAM (Static Random Access Memory) of an internal controller of the safe USB flash disk when the safe USB flash disk is powered on, and carrying out Hash abstract processing to generate a controller fingerprint abstract of the safe USB flash disk; when the security USB flash disk is authenticated, the host randomly generates a random number, maps the random number into a PUF bit address index and generates a PUF response of the security USB flash disk; combining the controller fingerprint abstract and the PUF response of the secure USB flash disk to obtain a session key; and realizing cooperative authentication of the secure USB flash disk according to the session key. The invention also discloses a system for realizing the collaborative authentication method of the safety USB flash disk. According to the invention, cooperative authentication of the safe USB flash disk is realized, and the reliability is higher and the safety is better.

The invention belongs to the field of computer system structures and artificial intelligence accelerators, and discloses a software and hardware collaborative heterogeneous storage computing accelerator oriented to full-chip DLRM reasoning. A control domain composed of a static random access memory and an embedded dynamic random access memory, an on-chip storage domain, an in-memory computing domain and an on-chip computing domain are integrated in the same chip, an embedded table is compressed by introducing a hierarchical clustering quantization frame, and a dynamic storage management strategy of access frequency perception is combined. The embedded access path is shortened, and the bandwidth requirement is reduced. According to the method, the reasoning process of the whole set of DLRM can be independently completed, and the memory access overhead in a traditional terminal SoC is remarkably reduced by reducing cross-domain data migration between the calculation unit and the storage unit, so that the model reasoning performance and energy efficiency are improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention relates to the technical field of electric digital data processing, and discloses a solid state disk controller circuit and a solid state disk. The controller circuit comprises a physical unclonable function unit based on an SRAM (Static Random Access Memory), which is used for dynamically generating a stable hardware trust root key during power-on; the secure boot and firmware decryption engine is used for deriving a firmware decryption authentication key and a data key packaging key by using the key, and carrying out decryption and integrity verification on the encrypted firmware; the runtime firmware execution monitoring unit is used for detecting illegal jump in real time and triggering safe shutdown through a hardware-level control flow diagram; and the dynamic data encryption key management unit recovers the plaintext data key and sends the plaintext data key to the encryption engine only during operation, and power failure disappears. By means of the scheme, end-to-end security protection of firmware and data is achieved, and the risks of static key leakage and firmware tampering are eradicated.

The invention provides a memory allocation method and device, electronic equipment, a storage medium and a chip. The method comprises the following steps: extracting tensor data of each tensor in a kernel program; constructing a control flow diagram according to the kernel program; allocating first address information in a static random access memory for each piece of tensor data; determining an active path of each tensor according to the control flow graph, the active path comprising a first node involving the tensor; an interferogram of the tensors is constructed according to the active path, each second node in the interferogram represents a different tensor, and edges between the second nodes represent an interference relation between the tensors; the first address information of each piece of tensor data is adjusted according to the interferogram, the second address information of each piece of tensor data is obtained, and in different steps of the kernel program, if no interference relation exists between the two tensors, the storage areas of the two pieces of tensor data are reused. According to the invention, the memory reuse rate can be improved.

A semiconductor device according to the present disclosure includes a first transistor and a second transistor sharing a first source / drain feature, a third transistor and a fourth transistor sharing a second source / drain feature, a first source / drain contact disposed over the first source / drain feature, a second source / drain contact disposed over the second source / drain feature, a first backside via disposed below the first source / drain feature, and a second backside via disposed below the second source / drain feature. A gate structure of the first transistor is coupled to the second source / drain contact and a gate structure of the fourth transistor is coupled to the first source / drain contact.

A semiconductor device includes a first source / drain feature on a front side of a substrate. The device includes a first backside metal line under the first source / drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source / drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source / drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

The invention provides a data processing method and device, computing equipment and a storage medium. The method comprises the following steps: acquiring a power-on initial value of a target storage unit of a target SRAM (Static Random Access Memory) of first equipment, wherein the target storage unit is a readable and non-writable storage unit in the SRAM; acquiring a device fingerprint of the first device; obtaining a power-on tendency value of the target storage unit based on the equipment fingerprint; and authenticating the first equipment according to the power-on initial value and the power-on tendency value. Therefore, the SRAM can be authenticated under the condition that the SRAM is not required to be powered off, so that the service operation in the SRAM is prevented from being influenced after the SRAM is powered off.

The invention discloses a laser projection control method and a distributed control device. The laser projection control method comprises the following steps: step 1, designing a first control board card for galvanometer control; the first control board card comprises a first main control chip for realizing real-time calculation, a static random access memory for external memory expansion, a differential driving chip for transmitting a galvanometer control signal and a chip for realizing an independent communication system; 2, designing a second control board card for laser control, focal length control and temperature monitoring; and the second control board card comprises a second main control chip for realizing real-time calculation, a motor driving chip for driving a motor to move the lens to control the focal length, a laser control circuit amplifier chip and a thermistor. According to the invention, the effect of cooperative control of the laser and the galvanometer is realized.

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and / or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

A semiconductor memory cell includes six vertical transport field effect transistors (VTFETs) on a wafer. The six VTFETs are in the first layer. The six VTFETs are in a first row.

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass- gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.