1245 results about "Tunnel junction" patented technology

A magnetoresistive random access memory (MRAM) includes a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. A bottom electrode is centrally disposed to be located within a periphery of the MTJ. The bottom electrode has sloped sidewalls that slope inwardly to connect to the MTJ.

A method comprises forming a shadow evaporation mask on a substrate, and utilizing the shadow evaporation mask to perform a double angle evaporation process to form a plurality of tunnel junction devices in each of the different regions of the substrate. The shadow evaporation mask comprises a plurality of patterned openings in different regions of the substrate, wherein each of the patterned openings comprises a same size and shaped opening. The tunnel junction devices each comprise a first metal layer and a second metal layer having an overlapping area, wherein the overlapping areas of the tunnel junction devices are invariant over the different regions of the substrate.

The invention provides a three-junction quantum well solar cell epitaxial structure and a manufacturing method thereof, the three-junction quantum well solar cell epitaxial structure comprises a substrate serving as a first sub-cell, a first tunnel junction, a second sub-cell, a second tunnel junction and a third sub-cell which are sequentially stacked from bottom to top, and the three sub-cells are connected through the tunnel junctions; wherein the first sub-cell is a Ge cell, the second sub-cell is an InGaAs cell, the third sub-cell is a GaInP / AlGaInP quantum well cell, the third sub-cell comprises a (Al < x > 1 < Ga < 1-x > 1 < y > 1 < In < 1-y > 1 < P) back field layer, a quantum well base region, a (Al < x > 4 < Ga < 1-x > 4 < y > 4 < In < 1-y > 4 < P) emitter region and an Al < x > 5 < In < 1-y > 5 window layer which are sequentially stacked from bottom to top, the quantum well base region is composed of a Ga < x > 2 < In < 1-x > 2 layer and a (Al < x > 3 < Ga < 1-x > 3 < y > 3 < In < 1 x is larger than or equal to 0.5 and smaller than or equal to 0.8, y is larger than or equal to 0.5 and smaller than or equal to 0.8, y is equal to 0.5, the GaInP / AlGaInP quantum well structure is used for replacing a traditional AlGaInP material to serve as a top cell material, the open-circuit voltage of the solar cell is increased, and meanwhile the defect that the short-circuit current of the AlGaInP / GaAs / Ge solar cell is insufficient is overcome.

The invention provides a synthetic antiferromagnetic memory cell driven by spin orbit moment without magnetic field assistance, and belongs to the technical field of magnetic memory, the synthetic antiferromagnetic memory cell comprises a magnetic tunnel junction of a multilayer film structure, the magnetic tunnel junction comprises a heavy metal layer and a synthetic antiferromagnetic free layer located on the heavy metal layer; the tunneling insulating layer is located on the synthetic antiferromagnetic free layer, the reference layer is located on the tunneling insulating layer, and the metal electrode layer is located on the reference layer; wherein the synthetic antiferromagnetic free layer comprises an inclined vertical magnetic layer, a non-magnetic metal layer and a coupling magnetic layer which are stacked in sequence, and the inclined vertical magnetic layer and the coupling magnetic layer are subjected to antiferromagnetic coupling through the middle non-magnetic metal layer; the inclined perpendicular magnetic layer has inclined perpendicular anisotropy. According to the invention, deterministic magnetization flipping driven by spin orbit moment and resistance state control of the magnetic tunnel junction memory cell without the assistance of an external magnetic field are realized.

A spin-orbit-torque (SOT) memory cell includes a first electrode embedded in dielectric material layers overlying a substrate; a magnetic-tunnel-junction-containing (MTJ-containing) pillar structure contacting a top surface of the first electrode and including a pinned layer and a free layer that overlies the pinned layer; a spin current metal line including a center portion that contacts the MTJ-containing pillar structure; and a selector element electrically connected to a first end of the spin current metal line.

The invention relates to a method for improving epitaxial growth quality of a tunnel junction cascade semiconductor laser. The invention innovatively provides a strain superlattice gradient repair technology. By designing a low-temperature low-speed nucleation-high-temperature high-speed epitaxy composite growth mode, a periodic superlattice buffer layer is introduced to a tunnel junction interface. Wherein lattice strain relaxation is achieved at the rate of 0.5-2 / s in the low-temperature stage, defect coverage is completed at the rate of 4-8 / s in the high-temperature stage, and dislocation line bending is terminated on a superlattice interface through thermodynamic regulation and control. Compared with the traditional process, the scheme can obviously improve the crystal quality, and does not increase the specific contact resistance of the tunnel junction interface.

The invention provides a physical unclonable function magnetic device and an application method thereof, the magnetic device comprises a plurality of magnetic storage units arranged in an array and a control circuit, and each magnetic storage unit comprises a spin orbit moment layer and at least one magnetic tunnel junction arranged on the spin orbit moment layer; and the control circuit is used for applying a composite reconstruction signal with oscillation change to the magnetic memory units, and forming a superposed physical field with oscillation change at the magnetic memory units so as to enable the resistance state of the magnetic tunnel junction to generate oscillation change to realize PUF reconstruction of the plurality of magnetic memory units arranged in an array. In order to solve the problems of limited CRP generated by the PUF circuit and low resource utilization rate, the physical field with oscillation change is formed through the composite reconstruction signal, so that the PUF of the magnetic tunnel junction of the SOT-MRAM generates random oscillation change, the PUF of the magnetic device can be reconstructed, the reconstructed magnetic device can generate new CRP, and the resource utilization rate is improved.

The invention relates to the technical field of laser preparation, and provides a photonic crystal surface emitting laser and a preparation method thereof. The preparation method comprises the following steps: sequentially growing an n-type doped layer, a p-type independent limiting layer and a p + / n + tunnel junction on a GaAs substrate; preparing a patterned mask structure on the p + / n + tunnel junction; the patterned mask structure comprises a plurality of preset patterns; etching the p + / n + tunnel junction according to a preset pattern to obtain a plurality of photonic crystals; sequentially growing an n-type coating layer, an undoped active layer and a p-type coating layer on the photonic crystal; growing a p-type electrode on the p-type coating layer; and growing an n-type electrode on the GaAs substrate. According to the preparation method, the SHB problem can be effectively solved, the multiple photonic crystals can be arranged in different modes to form a pattern capable of achieving the needed light emitting mode, light emitting in all directions can be achieved, the requirements for different light emitting characteristics of the photonic crystal surface emitting laser are met, and the use performance of the laser is guaranteed.

The invention provides an electric field regulation and control two-dimensional magnetic tunnel junction and a preparation method and application thereof, and belongs to the technical field of spinning electronic devices. The two-dimensional magnetic tunnel junction comprises a bottom electrode, a two-dimensional ferromagnetic material layer I, a two-dimensional ferroelectric material layer, a two-dimensional ferromagnetic material layer II and a protective layer which are stacked in sequence, the two-dimensional ferroelectric material layer adopts CuInP2S6, and migration of Cu ions is regulated and controlled through external voltage. The device can be applied to a high-density magnetic random access memory (MRAM), a high-sensitivity magnetic sensor and a low-power-consumption spin logic device, and has an industrialization prospect.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

The invention relates to a semiconductor structure, a preparation method thereof and a magnetic tunnel junction sensor. The semiconductor structure comprises a substrate, and a buffer layer, a solid magnetic layer, a tunnel barrier layer, a free layer and a protective layer which are located on the substrate. The solid magnetic layer comprises an antiferromagnetic pinning layer and a reference layer which are stacked, the antiferromagnetic pinning layer is located on the top surface of the buffer layer, and the magnetization direction of the reference layer is pinned by the antiferromagnetic pinning layer; the tunnel barrier layer is located on the top surface of the reference layer; the free layer is located on the top surface of the tunnel barrier layer, the thickness of the free layer in the direction perpendicular to the substrate continuously and smoothly changes in the preset direction, the thickness value distribution of the free layer conforms to a preset gradient function, and a preset included angle is formed between the preset direction and the pinned magnetization direction of the reference layer; the protective layer is on the top surface of the free layer. Multi-range or continuous wide-range detection can be realized in a single-chip semiconductor device, and high sensitivity is realized.

The invention discloses a 23T4M anti-radiation TCAM storage unit circuit which comprises a pre-charging module, an RH reading circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction storage module, a discharging module and an output module. In the RH reading circuit module, the grid electrode of a transistor N7 is connected with the drain electrode of a transistor N8, the grid electrode of the transistor N8 is connected with the drain electrode of the transistor N7, a cross coupling structure is formed, a node S0 and a node S1 are controlled by a node Q and a node QB, meanwhile, the node S0 and the node S1 control the charging and discharging paths of the node Q and the node QB respectively, and after any node is overturned by high-energy particles, the charging and discharging paths of the node Q and the node QB are controlled by the node S0 and the node S1. All the nodes are maintained or charged to recover to the original logic level. According to the method, data upset at a single sensitive node can be completely resisted, and meanwhile, the search error rate of the TCAM is improved.

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

The invention provides a magnetic random access memory and a preparation method thereof. The magnetic random access memory is applied to a comparison circuit, and comprises a magnetic tunnel junction comprising a free layer, a barrier layer and a reference layer which are stacked in sequence; the spin-orbit torque layer is located on the side, away from the reference layer, of the free layer, the conductive material layer is located on the side, away from the spin-orbit torque layer, of the magnetic tunnel junction, and a conductive material of the conductive material layer has the following characteristics that spontaneous magnetization capacity is achieved, and the resistance temperature coefficient is smaller than 0; the conductive material layer comprises a first part and a second part which are arranged at an interval, the first part is in contact with the reference layer, a first input end of the comparison circuit is electrically connected with the first part, and a second input end of the comparison circuit is electrically connected with the second part. According to the invention, the technical problems that the reading window of the magnetic tunnel junction becomes small and even the reading is wrong and the magnetic random access memory needs to apply an auxiliary magnetic field along the current direction to realize the deterministic overturning of the magnetic moment are at least solved.

The invention relates to the technical field of semiconductors, and discloses a semiconductor storage structure and an array, and the semiconductor storage structure at least comprises a plurality of semiconductor storage units, a top electrode, and gating devices corresponding to the semiconductor storage units. Each semiconductor storage unit at least comprises a spin orbit moment layer and a magnetic tunnel junction arranged above the spin orbit moment layer; the top electrode is located above the plurality of magnetic tunnel junctions, the plurality of magnetic tunnel junctions share the same top electrode, and a corresponding interconnection through hole is formed between the top electrode and each semiconductor storage unit; each gating device is arranged in the corresponding interconnection through hole, and the two ends of each gating device are electrically connected with the corresponding magnetic tunnel junction and the top electrode respectively. The number of transistors and wires can be reduced, the layout area occupied by the transistors and the wires is saved, and therefore the storage density is improved.

The invention provides an ion beam etching system with an etching rate in-situ monitoring function and an etching method, the ion beam etching system is provided with an objective table which can deflect by 90 degrees and an electrical test detection element which can move close to or far away from the objective table, and by the etching method, an ion source is not closed, a sample is not taken out, and the etching rate can be accurately measured. The etching depth can be accurately monitored by measuring the surface resistance of the sample in situ, the etching rate can be reduced in time, and the method is more suitable for the tape-out process. According to the ion beam etching system and the etching method, sputter spectrum monitoring is replaced by sample surface resistance detection, so that the test sensitivity is higher, the system cost is lower, the etching precision in magnetic tunnel junction preparation is greatly improved, the sample is prevented from being excessively etched, the thickness of a sample layer can be kept consistent, the resistance distribution is uniform, and the quality of the magnetic tunnel junction is improved. And the high success rate preparation of the SOT-MRAM memory with large capacity and small size is realized.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

The invention provides a high-power and high-efficiency single-mode semiconductor light-emitting structure and a preparation method thereof, the high-power and high-efficiency single-mode semiconductor light-emitting structure comprises a first Bragg reflector and a second Bragg reflector which are arranged along a first direction, and the reflectivity of the first Bragg reflector is greater than that of the second Bragg reflector; the multiple active layers are located between the first Bragg reflector and the second Bragg reflector and arranged in the first direction; the current limiting layer comprises a light emitting region and an oxidation region surrounding the light emitting region; the tunnel junctions are positioned between the adjacent active layers; the modulation layer is located on the side, away from the active layer, of the second Bragg reflector, the modulation layer comprises a first microstructure region and a second microstructure region surrounding the first microstructure region, the first microstructure region has a projection on a first part of the light emitting region in the first direction, and the second microstructure region has a projection on a second part of the light emitting region in the second direction; the second microstructure region has a projection on a second part of the light emitting region along the first direction, and the second part surrounds the first part.

The invention discloses an AlGaInP red light LED chip structure with a polarization-induced tunnel junction and a preparation method thereof. The chip structure sequentially comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type etching barrier layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, a non-doped InGaP / quantum well structure, a p-type spacer layer, a p-type AlGaInP polarization-induced doping layer, an insertion layer and an n-type ohmic contact layer from bottom to top. Wherein the p-type AlGaInP polarization induction doping layer introduces a piezoelectric polarization electric field through an Al component gradual change design, high-density two-dimensional hole gas is formed through induction, and the high-Al component insertion layer and the n-type ohmic contact layer form a tunnel junction; according to the invention, the problems of low p-type doping efficiency and high resistivity of the AlGaInP material with high Al component are fundamentally solved, the epitaxial structure and the chip process are simplified, the series resistance of the chip is reduced, the luminous efficiency is improved, the yield is improved, and the method has remarkable technical and commercial values.

The present invention relates to the field of photovoltaic technology, and discloses a TBC battery structure with a self-formed gap region and a PVD method for preparing the same, comprising a silicon substrate, wherein the back surface of the silicon substrate is provided with a p+ region and an n+ region, wherein the height positions of the p+ region and the n+ region on the back surface of the silicon substrate are staggered to form a step, and a gap region is formed at the step sidewall connecting the p+ region and the n+ region, wherein the gap region is used to electrically isolate the p+ region and the n+ region; the p+ region comprises a first tunneling oxide layer, a p‑poly layer, a second tunneling oxide layer and an n‑poly layer sequentially deposited on the silicon substrate; and the n+ region comprises a second tunneling oxide layer and an n‑poly layer sequentially deposited on the silicon substrate. The present invention utilizes p‑poly to superimpose n‑poly to form a tunneling junction, which can directly avoid using a second laser to remove the n‑poly on the p‑poly, avoids damage to the surface crystalline silicon layer by the laser, and simultaneously reduces a laser grooving process, thereby greatly reducing the production cost.

A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.

A semiconductor device and methods forming the device is disclosed. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top elec

A magnetoresistive memory cell includes a magnetic polarizer layer having a hard magnetization along a hard magnetization direction, a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and including a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer. The memory cell also includes a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and including a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer.

A semiconductor device includes a substrate, magnetic tunnel junction (MTJ) structures, and a write structure. The MTJ structures are disposed above the substrate. The write structure is disposed on and connected with the MTJ structures. The write structure includes spin-orbit torque (SOT) patterns and an electrically conductive layer. The SOT patterns are separated from one another, and each of the SOT patterns is disposed on and connected with one of the MTJ structures. The conductive layer covers the SOT patterns. The electrically conductive layer is partly disposed above the SOT patterns in a vertical direction and partly disposed between the SOT patterns in a first horizontal direction.

The invention is suitable for the technical field of semiconductors, and provides a blue-green double-peak LED epitaxial growth method, which comprises the following steps: processing a substrate, growing a low-temperature GaN buffer layer, growing a non-doped GaN layer, growing a Si-doped N-type GaN layer, growing a multi-quantum well layer, growing an AlGaN electron barrier layer, growing a Mg-doped P-type GaN layer, and cooling. Wherein the growth of the multi-quantum well layer sequentially comprises the steps of growing a first MQWs, growing a tunnel junction layer, growing a second MQWs and growing an AlGaN / GaN superlattice layer, the tunnel junction layer is introduced into the multi-quantum well layer to enhance tunneling of holes, meanwhile, the AlGaN / GaN superlattice layer is introduced, gradual change of an Al component in AlGaN is controlled by controlling the introduction time of TMAl, the problem of light emitting peak broadening is solved, and the light emitting efficiency is improved. The quantum well is ensured to emit blue light and green light at the same time, the color saturation of the light is improved, and the color temperature is reduced.

The invention relates to high temperature superconducting qubits with disorder induced tunnel barriers. A superconducting qubit circuit and a method of forming a superconducting qubit are disclosed herein. A superconducting qubit circuit includes a superconducting qubit, where the superconducting qubit includes a tunnel junction in a superconducting material having a critical temperature above 1.2 K. The tunnel junction is formed from a disorder-induced tunnel barrier, where the disorder results from spatial crystal defects in the superconducting material.

A magnetic tunnel junction element and a memory device including the same are provided. The magnetic tunnel junction element includes: a pinned layer and a free layer facing each other; a buffer layer on the pinning layer; an auxiliary layer on the buffer layer; a polarization enhancement layer between the auxiliary layer and the free layer; and a tunnel barrier layer between the polarization enhancement layer and the free layer, in which the buffer layer is amorphous and includes CoFeBX, and X is W, Mo, Re, or Ta, and the auxiliary layer includes W, Mo, or Ta.

An embodiment of the present application provides a storage device, a preparation method, a reading and writing method, a storage chip, and an electronic device, which relate to the field of storage technology and are used to solve the problem that the number of storage states in a spin-orbit torque-magnetic random access memory increases while the storage state change range remains unchanged. The storage device includes: a first magnetic tunnel junction, a spin-orbit coupling layer, and a second magnetic tunnel junction that are sequentially stacked. The first magnetic tunnel junction includes a first free layer, and the second magnetic tunnel junction includes a second free layer. The first free layer and the second free layer are disposed on two opposite surfaces of the spin-orbit coupling layer.

The application relates to a TMR magnetic sensor, comprising: a plurality of inclined structures, each inclined structure being arranged along a first axis and comprising a first inclined surface and a second inclined surface symmetrically arranged along the first axis; the first magnetic induction pairs are used for inducing a third-axis magnetic field, each first magnetic induction pair comprises a first magnetic resistance element and a second magnetic resistance element, and the first magnetic resistance elements and the second magnetic resistance elements are formed by combining the same number of magnetic tunnel junctions in the same mode; the magnetic tunnel junctions of the first magnetic resistance element and the second magnetic resistance element are respectively arranged on a first inclined surface and a second inclined surface which are of an inclined structure and have the same axis; the magnetic tunnel junctions of the first magnetoresistive element and the second magnetoresistive element have initial magnetization directions along a first axis and have the same positive and negative, the magnetic tunnel junctions of the first magnetoresistive element and the second magnetoresistive element have pinning directions along the inclined planes, the components of the pinning directions on the second axis are opposite in positive and negative, and the components of the pinning directions on the third axis are the same in positive and negative. The cross-axis interference can be reduced, and the detection anti-interference capability is improved.

A neuromorphic computing array includes horizontal lines and vertical lines that intersect the horizontal lines at cell locations. Magnetic tunnel junction cells are located at the cell locations. Each cell is electrically connected to a corresponding one of the horizontal lines and to a corresponding one of the vertical lines. Each cell includes a substrate, a seed layer overlying the substrate, and a nitride layer, overlying the seed layer, and optionally having a thickness greater than 5 Angstroms. Each cell further includes a templating layer, outward of the nitride layer, including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms. Each cell still further includes a magnetic layer overlying the templating layer, a tunnel barrier outward of the magnetic layer; and a magnetic layer outward of the tunnel barrier. The magnetic layer includes a Heusler compound and exhibits perpendicular magnetic anisotropy (PMA).