1675 results about "Tunnel junction" patented technology

The present invention comprises Magnetic Tunnel Junctions and Bit-Patterned Media with a warped geometry with the purpose of attaining large thermal stability factors and dramatically increasing the scalability of the magnetic bits while still allowing the reduction of switching current density and switching magnetic field, and also increasing switching speed. The warped shape allows providing thermal stability to the bits through dynamic exchange energy barrier and also by providing additional net magnetic anisotropy through shape-induced reduction of the demagnetization field. The dynamic exchange energy barrier in turn allows engineering the damping torque and the free-layer's magnetic parameters to a much larger extent than the current planar technology. It also allows much faster magnetic-field-induced switching of patterned bits than it is possible with current hard disk drive technology, through the use of precession torque instead of conventional damping torque.

A magnetoresistive random access memory (MRAM) includes a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. A bottom electrode is centrally disposed to be located within a periphery of the MTJ. The bottom electrode has sloped sidewalls that slope inwardly to connect to the MTJ.

A method comprises forming a shadow evaporation mask on a substrate, and utilizing the shadow evaporation mask to perform a double angle evaporation process to form a plurality of tunnel junction devices in each of the different regions of the substrate. The shadow evaporation mask comprises a plurality of patterned openings in different regions of the substrate, wherein each of the patterned openings comprises a same size and shaped opening. The tunnel junction devices each comprise a first metal layer and a second metal layer having an overlapping area, wherein the overlapping areas of the tunnel junction devices are invariant over the different regions of the substrate.

The invention provides a three-junction quantum well solar cell epitaxial structure and a manufacturing method thereof, the three-junction quantum well solar cell epitaxial structure comprises a substrate serving as a first sub-cell, a first tunnel junction, a second sub-cell, a second tunnel junction and a third sub-cell which are sequentially stacked from bottom to top, and the three sub-cells are connected through the tunnel junctions; wherein the first sub-cell is a Ge cell, the second sub-cell is an InGaAs cell, the third sub-cell is a GaInP / AlGaInP quantum well cell, the third sub-cell comprises a (Al < x > 1 < Ga < 1-x > 1 < y > 1 < In < 1-y > 1 < P) back field layer, a quantum well base region, a (Al < x > 4 < Ga < 1-x > 4 < y > 4 < In < 1-y > 4 < P) emitter region and an Al < x > 5 < In < 1-y > 5 window layer which are sequentially stacked from bottom to top, the quantum well base region is composed of a Ga < x > 2 < In < 1-x > 2 layer and a (Al < x > 3 < Ga < 1-x > 3 < y > 3 < In < 1 x is larger than or equal to 0.5 and smaller than or equal to 0.8, y is larger than or equal to 0.5 and smaller than or equal to 0.8, y is equal to 0.5, the GaInP / AlGaInP quantum well structure is used for replacing a traditional AlGaInP material to serve as a top cell material, the open-circuit voltage of the solar cell is increased, and meanwhile the defect that the short-circuit current of the AlGaInP / GaAs / Ge solar cell is insufficient is overcome.

The invention provides a perovskite-crystalline silicon laminated cell, which comprises a heterogeneous crystalline silicon cell, a tunnel junction, a conductive layer, a first carrier transport layer, a perovskite light absorption layer, a second carrier transport layer and a transparent electrode layer which are sequentially laminated, wherein the first carrier transport layer comprises a dendritic structure facing and extending into the perovskite light absorption layer, and the length of the dendritic structure is smaller than the thickness of the perovskite light absorption layer. According to the perovskite-crystalline silicon laminated cell provided by the invention, through the arrangement of the dendritic structure with a relatively good capillary effect in the first carrier transport layer, a high-quality perovskite absorption layer can be formed, so that the energy conversion efficiency of the perovskite-crystalline silicon laminated solar cell is greatly improved.

The invention provides a synthetic antiferromagnetic memory cell driven by spin orbit moment without magnetic field assistance, and belongs to the technical field of magnetic memory, the synthetic antiferromagnetic memory cell comprises a magnetic tunnel junction of a multilayer film structure, the magnetic tunnel junction comprises a heavy metal layer and a synthetic antiferromagnetic free layer located on the heavy metal layer; the tunneling insulating layer is located on the synthetic antiferromagnetic free layer, the reference layer is located on the tunneling insulating layer, and the metal electrode layer is located on the reference layer; wherein the synthetic antiferromagnetic free layer comprises an inclined vertical magnetic layer, a non-magnetic metal layer and a coupling magnetic layer which are stacked in sequence, and the inclined vertical magnetic layer and the coupling magnetic layer are subjected to antiferromagnetic coupling through the middle non-magnetic metal layer; the inclined perpendicular magnetic layer has inclined perpendicular anisotropy. According to the invention, deterministic magnetization flipping driven by spin orbit moment and resistance state control of the magnetic tunnel junction memory cell without the assistance of an external magnetic field are realized.

A spin-orbit-torque (SOT) memory cell includes a first electrode embedded in dielectric material layers overlying a substrate; a magnetic-tunnel-junction-containing (MTJ-containing) pillar structure contacting a top surface of the first electrode and including a pinned layer and a free layer that overlies the pinned layer; a spin current metal line including a center portion that contacts the MTJ-containing pillar structure; and a selector element electrically connected to a first end of the spin current metal line.

The invention provides a magnetic memory and a preparation method thereof. The magnetic memory comprises a plurality of memory units, at least part of the memory units are arranged along a first direction, and each memory unit comprises a magnetic tunnel junction; at least part of the magnetic shielding structure is located between the adjacent storage units in the first direction, and the magnetic shielding structure and the adjacent storage units are arranged at intervals; wherein the magnetic shielding structures and the adjacent storage units are arranged at intervals. Due to the fact that the magnetic shielding structure is arranged between every two adjacent storage units, the storage area can be saved through the design, meanwhile, the magnetic shielding structures can prevent the storage units from making contact with the magnetic shielding structures to cause short circuit, and the storage units have the anti-magnetic characteristic of an opposite internal magnetic field. Therefore, the magnetic memory has the diamagnetic properties of a vertical magnetic field and an in-plane magnetic field, the diamagnetic capability of the magnetic memory is improved, and the reliability of the magnetic memory in a magnetic field environment is further improved.

A magnetic gradiometer can be used in systems or methods for nondestructive testing, even when the material being tested is weakly magnetic. The magnetic gradiometer can include a printed circuit board (PCB) comprising a first end and a second end separated by a base length; an excitation coil encircling at least a portion of the PCB and configured to deliver an alternating current (AC) to generate an excitation magnetic field; and a differential sensor. The differential sensor can include a reference magnetic tunneling junction in magnetic vortex state (vortex MTJ) sensor array at the first end to generate a voltage based on the excitation magnetic field; and a signal vortex MTJ sensor array at the second end to generate another voltage based on the excitation magnetic field due to a composition of the measurement target. The second end of the PCB can be oriented towards the measurement target.

The invention relates to a method for improving epitaxial growth quality of a tunnel junction cascade semiconductor laser. The invention innovatively provides a strain superlattice gradient repair technology. By designing a low-temperature low-speed nucleation-high-temperature high-speed epitaxy composite growth mode, a periodic superlattice buffer layer is introduced to a tunnel junction interface. Wherein lattice strain relaxation is achieved at the rate of 0.5-2 / s in the low-temperature stage, defect coverage is completed at the rate of 4-8 / s in the high-temperature stage, and dislocation line bending is terminated on a superlattice interface through thermodynamic regulation and control. Compared with the traditional process, the scheme can obviously improve the crystal quality, and does not increase the specific contact resistance of the tunnel junction interface.

The invention provides a multi-junction surface-emitting laser and a light-emitting module. A first reflecting layer, an active region and a second reflecting layer are sequentially stacked on a substrate, the active region is composed of at least two PN junctions or P-I-N junctions, and the PN junctions or the P-I-N junctions are connected through tunnel junctions; wherein the material of the substrate is gallium arsenide or indium phosphide, the crystal face of the substrate is {n11} crystal face family, n is 0 or an integer greater than 1, and anisotropic gain can be obtained in the VCSEL by using the non-(001)-oriented substrate and the quantum well, so that polarization in a quantum well plane (active region) is controlled to obtain higher gain, a grating structure does not need to be additionally arranged, the preparation process is simplified, and the preparation cost is reduced.

This disclosure presents a 3D magnetic memory device comprising a stack with alternatingly arranged dielectric and silicon-based layers, and a magnetic material channel formed through the stack. The channel has a first diameter where it extends through a silicon-based layer, and a second diameter where it extends through a dielectric layer. Pinning sites defined by the layers are formed in the channel, each pinning site being configured to store one magnetic bit. A first metallic layer is arranged on a first end of the channel and the stack. A magnetic tunnel junction (MTJ) and a first electrode are arranged on the first metallic layer in a distance to another. Either the first metallic layer is configured as a spin-orbit-torque (SOT) track, or a second metallic layer is configured as a SOT track, wherein a second end of the channel and the stack are arranged on the second metallic layer.

The invention provides a physical unclonable function magnetic device and an application method thereof, the magnetic device comprises a plurality of magnetic storage units arranged in an array and a control circuit, and each magnetic storage unit comprises a spin orbit moment layer and at least one magnetic tunnel junction arranged on the spin orbit moment layer; and the control circuit is used for applying a composite reconstruction signal with oscillation change to the magnetic memory units, and forming a superposed physical field with oscillation change at the magnetic memory units so as to enable the resistance state of the magnetic tunnel junction to generate oscillation change to realize PUF reconstruction of the plurality of magnetic memory units arranged in an array. In order to solve the problems of limited CRP generated by the PUF circuit and low resource utilization rate, the physical field with oscillation change is formed through the composite reconstruction signal, so that the PUF of the magnetic tunnel junction of the SOT-MRAM generates random oscillation change, the PUF of the magnetic device can be reconstructed, the reconstructed magnetic device can generate new CRP, and the resource utilization rate is improved.

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

The invention relates to the technical field of laser preparation, and provides a photonic crystal surface emitting laser and a preparation method thereof. The preparation method comprises the following steps: sequentially growing an n-type doped layer, a p-type independent limiting layer and a p + / n + tunnel junction on a GaAs substrate; preparing a patterned mask structure on the p + / n + tunnel junction; the patterned mask structure comprises a plurality of preset patterns; etching the p + / n + tunnel junction according to a preset pattern to obtain a plurality of photonic crystals; sequentially growing an n-type coating layer, an undoped active layer and a p-type coating layer on the photonic crystal; growing a p-type electrode on the p-type coating layer; and growing an n-type electrode on the GaAs substrate. According to the preparation method, the SHB problem can be effectively solved, the multiple photonic crystals can be arranged in different modes to form a pattern capable of achieving the needed light emitting mode, light emitting in all directions can be achieved, the requirements for different light emitting characteristics of the photonic crystal surface emitting laser are met, and the use performance of the laser is guaranteed.

The invention provides a true random number generator based on a magnetic tunnel junction device and a random number generation method. The true random number generator provided by the invention comprises a control circuit, a magnetic tunnel junction device and a random number generator, the control circuit is used for providing a plurality of continuous voltage pulse signals for the magnetic tunnel junction device, so that the resistance of the magnetic tunnel junction device oscillates; the plurality of continuous voltage pulse signals correspond to different flip probabilities of the magnetic tunnel junction device, and after the plurality of continuous voltage pulse signals cooperatively act on the magnetic tunnel junction device, the magnetic tunnel junction device accumulates the flip probabilities based on in-memory calculation, so that the final flip probability after accumulation tends to be a half-and-half probability; and the random number generator is used for generating a random number according to the resistance state of the magnetic tunnel junction device after the plurality of continuous voltage pulse signals are applied. According to the true random number generator based on the magnetic tunnel junction device and the random number generation method provided by the invention, random numbers with high randomness and uniform distribution can be generated.

The invention provides an electric field regulation and control two-dimensional magnetic tunnel junction and a preparation method and application thereof, and belongs to the technical field of spinning electronic devices. The two-dimensional magnetic tunnel junction comprises a bottom electrode, a two-dimensional ferromagnetic material layer I, a two-dimensional ferroelectric material layer, a two-dimensional ferromagnetic material layer II and a protective layer which are stacked in sequence, the two-dimensional ferroelectric material layer adopts CuInP2S6, and migration of Cu ions is regulated and controlled through external voltage. The device can be applied to a high-density magnetic random access memory (MRAM), a high-sensitivity magnetic sensor and a low-power-consumption spin logic device, and has an industrialization prospect.

A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.

The invention relates to the technical field of semiconductor lasers, and discloses a semiconductor laser and a preparation method thereof, the semiconductor laser comprises a substrate layer and an epitaxial structure, the epitaxial structure comprises a plurality of light emitting structures, a tunnel junction and an ohmic contact layer; the light-emitting structure comprises a lower limiting layer, an active region and an upper limiting layer which are arranged from bottom to top, and further comprises a first oxide layer; the multiple light-emitting structures are arranged in a stacked mode, every two adjacent light-emitting structures are connected through a tunnel junction, the light-emitting structure on the lowest layer is arranged on the surface of one side of the substrate layer, and the ohmic contact layer is arranged on the surface of the side, away from the substrate layer, of the epitaxial structure on the uppermost layer; a ridge-shaped waveguide structure or a columnar hole array structure is formed in the epitaxial structure in the direction perpendicular to the epitaxial growth direction and the light emitting direction, and the side wall, close to the ridge-shaped waveguide structure or the columnar hole, of the first oxide layer is an insulating layer. According to the invention, power doubling is realized under the same electric injection, Joule heat is reduced, and power density is reduced.

The invention relates to a semiconductor structure, a preparation method thereof and a magnetic tunnel junction sensor. The semiconductor structure comprises a substrate, and a buffer layer, a solid magnetic layer, a tunnel barrier layer, a free layer and a protective layer which are located on the substrate. The solid magnetic layer comprises an antiferromagnetic pinning layer and a reference layer which are stacked, the antiferromagnetic pinning layer is located on the top surface of the buffer layer, and the magnetization direction of the reference layer is pinned by the antiferromagnetic pinning layer; the tunnel barrier layer is located on the top surface of the reference layer; the free layer is located on the top surface of the tunnel barrier layer, the thickness of the free layer in the direction perpendicular to the substrate continuously and smoothly changes in the preset direction, the thickness value distribution of the free layer conforms to a preset gradient function, and a preset included angle is formed between the preset direction and the pinned magnetization direction of the reference layer; the protective layer is on the top surface of the free layer. Multi-range or continuous wide-range detection can be realized in a single-chip semiconductor device, and high sensitivity is realized.

The invention discloses a 23T4M anti-radiation TCAM storage unit circuit which comprises a pre-charging module, an RH reading circuit module, a programmable logic module, a reconfigurable magnetic tunnel junction storage module, a discharging module and an output module. In the RH reading circuit module, the grid electrode of a transistor N7 is connected with the drain electrode of a transistor N8, the grid electrode of the transistor N8 is connected with the drain electrode of the transistor N7, a cross coupling structure is formed, a node S0 and a node S1 are controlled by a node Q and a node QB, meanwhile, the node S0 and the node S1 control the charging and discharging paths of the node Q and the node QB respectively, and after any node is overturned by high-energy particles, the charging and discharging paths of the node Q and the node QB are controlled by the node S0 and the node S1. All the nodes are maintained or charged to recover to the original logic level. According to the method, data upset at a single sensitive node can be completely resisted, and meanwhile, the search error rate of the TCAM is improved.

The invention discloses a spin orbit moment magnetic tunnel junction, a majority gate spin logic device and cascade of the majority gate spin logic device, and the magnetic tunnel junction comprises an electrode layer, an artificial antiferromagnetic reference layer, an insulating tunneling layer, a magnetization free layer and an abnormal spin orbit moment layer which are sequentially stacked from top to bottom, the artificial antiferromagnetic reference layer comprises a first ferromagnetic layer, a non-magnetic spacer layer and a second ferromagnetic layer which are sequentially stacked from top to bottom, and the first ferromagnetic layer has vertical magnetization with a fixed direction; the electrode layer in contact with the first ferromagnetic layer has in-plane polarization to adjust the magnetization direction of the second ferromagnetic layer, and the magnetic free layer has vertical magnetization with variable direction; and the abnormal spin-orbit moment layer in contact with the magnetic free layer has an in-plane magnetization direction to generate an abnormal spin Hall effect, so that the magnetization of the magnetic free layer is overturned, the resistance state of the spin-orbit moment magnetic tunnel junction is changed, and a logic function is realized.

A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.

The invention provides a magnetic random access memory and a preparation method thereof. The magnetic random access memory is applied to a comparison circuit, and comprises a magnetic tunnel junction comprising a free layer, a barrier layer and a reference layer which are stacked in sequence; the spin-orbit torque layer is located on the side, away from the reference layer, of the free layer, the conductive material layer is located on the side, away from the spin-orbit torque layer, of the magnetic tunnel junction, and a conductive material of the conductive material layer has the following characteristics that spontaneous magnetization capacity is achieved, and the resistance temperature coefficient is smaller than 0; the conductive material layer comprises a first part and a second part which are arranged at an interval, the first part is in contact with the reference layer, a first input end of the comparison circuit is electrically connected with the first part, and a second input end of the comparison circuit is electrically connected with the second part. According to the invention, the technical problems that the reading window of the magnetic tunnel junction becomes small and even the reading is wrong and the magnetic random access memory needs to apply an auxiliary magnetic field along the current direction to realize the deterministic overturning of the magnetic moment are at least solved.

The invention provides an LED epitaxial wafer, an LED chip and a preparation method of the LED epitaxial wafer, and belongs to the technical field of light emitting diodes, the LED epitaxial wafer comprises a substrate and an epitaxial layer, the epitaxial layer comprises an n-type electronic layer, an n-type electronic barrier layer, an active layer, a p-type hole barrier layer, a p-type hole layer and a p-type window layer which are sequentially stacked, the p-type window layer comprises two tunnel junction structures and superlattice units which are clamped between the two tunnel junction structures and are periodically distributed in the stacking direction, each tunnel junction structure comprises a p-type doped InP sub-layer, an undoped InP sub-layer and an n-type doped InP sub-layer which are sequentially stacked, and each superlattice unit comprises an Al < x > P sub-layer and a Ga < 1-x > P sub-layer which are sequentially stacked. The tunnel junction structure and the superlattice structure formed by the superlattice units are introduced into the p-type window layer, so that the injection efficiency of current carriers can be improved, the resistance can be reduced, and the current expansion capability can be improved.

The invention relates to the technical field of semiconductors, and discloses a semiconductor storage structure and an array, and the semiconductor storage structure at least comprises a plurality of semiconductor storage units, a top electrode, and gating devices corresponding to the semiconductor storage units. Each semiconductor storage unit at least comprises a spin orbit moment layer and a magnetic tunnel junction arranged above the spin orbit moment layer; the top electrode is located above the plurality of magnetic tunnel junctions, the plurality of magnetic tunnel junctions share the same top electrode, and a corresponding interconnection through hole is formed between the top electrode and each semiconductor storage unit; each gating device is arranged in the corresponding interconnection through hole, and the two ends of each gating device are electrically connected with the corresponding magnetic tunnel junction and the top electrode respectively. The number of transistors and wires can be reduced, the layout area occupied by the transistors and the wires is saved, and therefore the storage density is improved.

A magnetic tunnel junction device includes a pillar structure including, from bottom to top, a bottom electrode and a magnetic tunnel junction structure, a top electrode overlying the magnetic tunnel junction structure, and a dielectric metal oxide layer extending from a sidewall of the pillar structure to a sidewall of the top electrode. The magnetic tunnel junction structure contains a reference magnetization layer including a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer including a second ferromagnetic material. The top electrode includes a metallic material containing a nonmagnetic metal element. The dielectric metal oxide layer may be formed by performing an oxidation process that oxidizes a residual metal film after a focused ion beam etch process, and eliminates conductive paths from surfaces of the pillar structure.

The invention provides an ion beam etching system with an etching rate in-situ monitoring function and an etching method, the ion beam etching system is provided with an objective table which can deflect by 90 degrees and an electrical test detection element which can move close to or far away from the objective table, and by the etching method, an ion source is not closed, a sample is not taken out, and the etching rate can be accurately measured. The etching depth can be accurately monitored by measuring the surface resistance of the sample in situ, the etching rate can be reduced in time, and the method is more suitable for the tape-out process. According to the ion beam etching system and the etching method, sputter spectrum monitoring is replaced by sample surface resistance detection, so that the test sensitivity is higher, the system cost is lower, the etching precision in magnetic tunnel junction preparation is greatly improved, the sample is prevented from being excessively etched, the thickness of a sample layer can be kept consistent, the resistance distribution is uniform, and the quality of the magnetic tunnel junction is improved. And the high success rate preparation of the SOT-MRAM memory with large capacity and small size is realized.

To improve the characteristics of an optical semiconductor element.SOLUTION: An optical semiconductor element according to the present invention includes a first active layer having an emission and reception wavelength of a first wavelength, a tunnel junction layer on the first active layer, and a second active layer on the tunnel junction layer having an emission and reception wavelength of a second wavelength, and the first and second active layers include Sb, and the tunnel junction layer has a p-type InAs layer and an n-type InAs layer.SELECTED DRAWING: Figure 1

A magnetic tunnel junction pillar is positioned above a bottom electrode composed of a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region. A sidewall spacer is positioned along sidewalls of the magnetic tunnel junction pillar, and the metal region is in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.