525 results about "Tunnel junction" patented technology

The invention relates to a semiconductor structure, a preparation method thereof and a magnetic tunnel junction sensor. The semiconductor structure comprises a substrate, and a buffer layer, a solid magnetic layer, a tunnel barrier layer, a free layer and a protective layer which are located on the substrate. The solid magnetic layer comprises an antiferromagnetic pinning layer and a reference layer which are stacked, the antiferromagnetic pinning layer is located on the top surface of the buffer layer, and the magnetization direction of the reference layer is pinned by the antiferromagnetic pinning layer; the tunnel barrier layer is located on the top surface of the reference layer; the free layer is located on the top surface of the tunnel barrier layer, the thickness of the free layer in the direction perpendicular to the substrate continuously and smoothly changes in the preset direction, the thickness value distribution of the free layer conforms to a preset gradient function, and a preset included angle is formed between the preset direction and the pinned magnetization direction of the reference layer; the protective layer is on the top surface of the free layer. Multi-range or continuous wide-range detection can be realized in a single-chip semiconductor device, and high sensitivity is realized.

The invention provides a magnetic random access memory and a preparation method thereof. The magnetic random access memory is applied to a comparison circuit, and comprises a magnetic tunnel junction comprising a free layer, a barrier layer and a reference layer which are stacked in sequence; the spin-orbit torque layer is located on the side, away from the reference layer, of the free layer, the conductive material layer is located on the side, away from the spin-orbit torque layer, of the magnetic tunnel junction, and a conductive material of the conductive material layer has the following characteristics that spontaneous magnetization capacity is achieved, and the resistance temperature coefficient is smaller than 0; the conductive material layer comprises a first part and a second part which are arranged at an interval, the first part is in contact with the reference layer, a first input end of the comparison circuit is electrically connected with the first part, and a second input end of the comparison circuit is electrically connected with the second part. According to the invention, the technical problems that the reading window of the magnetic tunnel junction becomes small and even the reading is wrong and the magnetic random access memory needs to apply an auxiliary magnetic field along the current direction to realize the deterministic overturning of the magnetic moment are at least solved.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

A magnetoresistive memory cell includes a magnetic polarizer layer having a hard magnetization along a hard magnetization direction, a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and including a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer. The memory cell also includes a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and including a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer.

The invention relates to an anti-radiation five-junction solar cell and a preparation method thereof, and belongs to the technical field of semiconductor devices. The radiation-proof five-junction solar cell comprises a substrate, and a first buffer layer, a first component order change buffer layer, a fourth sub-cell, a second component order change buffer layer, a fourth tunnel junction, a fifth sub-cell and an electrode contact layer which are sequentially stacked on a first surface of the substrate, a second buffer layer, a third tunnel junction, a third sub-cell, a second tunnel junction, a second sub-cell, a first tunnel junction, a first sub-cell and a cap layer are sequentially stacked on the second surface of the substrate; and the base region thicknesses of the second sub-cell, the third sub-cell and the fourth sub-cell are smaller than the respective emitter region thicknesses. The anti-radiation five-junction solar cell comprises a plurality of sub-cells with quantum well structures, so that the anti-radiation performance of the solar cell can be effectively improved, and the last-stage use efficiency of the solar cell is further remarkably improved.

The embodiment of the invention provides a physical unclonable function generator and a true random number generator. The physical unclonable function generator comprises a storage array and a control unit, a storage unit in the storage array comprises a magnetic storage device, and the magnetic storage device comprises a magnetic tunnel junction; the control unit is used for controlling the application of a magnetic field along a target direction to the storage array, and reading the resistance state of the storage unit to generate a physical unclonable function after the application of the magnetic field is stopped; wherein the target direction is perpendicular to or approximately perpendicular to the magnetic moment direction of the free layer in the magnetic tunnel junction in the in-plane direction, and the randomness and uniformity of the physical unclonable function are improved.

The invention provides a vertical cavity surface emitting laser and an epitaxial growth method thereof, and belongs to the technical field of semiconductors. The vertical cavity surface emitting laser comprises a substrate, an N-DBR, an active region growth layer, an oxidation limiting layer, a tunnel junction, a P-DBR and a surface ohmic contact layer which are stacked in sequence. The tunnel junction comprises a p + + layer, a first diffusion barrier layer, an n + + layer and a second diffusion barrier layer which are stacked in sequence. The p + + layer and the n + + layer are obtained through pulse doping growth, and P-DBR growth is carried out after stepped heating is carried out on the tunnel junction. The invention provides a comprehensive process based on pulse doping, an in-situ protection layer and stepped heating control, pulse doping is adopted when the n + + / p + + layer of the tunnel junction grows, the first diffusion barrier layer, the second diffusion barrier layer and the stepped heating process in subsequent growth are combined, and doping diffusion is remarkably inhibited while high conductivity of the tunnel junction is maintained.

The invention provides a multi-junction cascade photonic crystal surface emitting laser and a preparation method thereof. The multi-junction cascade photonic crystal surface emitting laser comprises a substrate; the three-dimensional photonic crystal structure is arranged on the substrate, the three-dimensional photonic crystal structure comprises a longitudinal periodic structure formed by a plurality of laminated structures which are sequentially stacked in the vertical direction of the substrate, each laminated structure comprises an active layer and a photonic crystal layer, and the photonic crystal layer provides optical feedback for the active layer to form optical resonance; a transverse periodic structure is formed in each photonic crystal layer; and the plurality of tunnel junctions are arranged between the two adjacent laminated structures and are used for electrically connecting the two adjacent laminated structures.

A magnetoresistive memory cell includes a magnetic polarizer layer having a hard magnetization along a hard magnetization direction, a first magnetic tunnel junction located on a first side of the magnetic polarizer layer and including a first reference layer having a first side facing the magnetic polarizer layer, a first free layer facing a second side of the first reference layer, and a first tunnel barrier layer located between the first free layer and the first reference layer. The memory cell also includes a second magnetic tunnel junction located on a second side of the magnetic polarizer layer and including a second reference layer having a second side facing the magnetic polarizer layer, a second free layer facing a first side of the second reference layer, and a second tunnel barrier layer located between the second free layer and the second reference layer.

The invention provides a magnetic superconducting memory and a preparation method and a read-write method thereof. According to the magnetic superconducting memory, the superconducting layer maps the magnetization state by using the resistance difference between the superconducting state and the normal state; the ferromagnetic layer serves as a free layer capable of adjusting magnetization, and the magnitude of superconductive critical current of the superconductive layer is influenced through the magnetization direction. The heavy metal layer generates spin orbit torque through a spin Hall effect to drive the ferromagnetic layer to be magnetized and overturned; an infinite switching ratio between a superconducting state and a normal state is realized through a superconducting diode magnetoresistance effect, a high-efficiency and high-reliability nonvolatile storage scheme is realized in combination with a current-driven spin-orbit torque magnetization overturning technology, inherent defects of a traditional TMR are thoroughly overcome, and the signal contrast of a storage unit is remarkably improved; the heterostructure designed by the invention replaces a traditional magnetic tunnel junction, reduces material stacking and process complexity, and adopts a material compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process to promote large-scale integration of the low-temperature memory.

The invention discloses a red-light high-voltage light-emitting chip and a preparation method thereof, and the chip comprises an epitaxial structure which comprises at least two red light-emitting devices which are sequentially stacked in a direction from a first surface to a second surface, and a series tunnel junction which is located between the two adjacent red light-emitting devices, the series tunnel junction is used for connecting two adjacent red light-emitting devices in series; the direction of the first surface pointing to the second surface is parallel to the light emitting direction of the epitaxial structure; a first electrode connected to the red light emitting device closest to the first surface among the red light emitting devices connected in series; and a second electrode connected to the red light emitting device closest to the second surface among the red light emitting devices connected in series. According to the technical scheme provided by the invention, the production cost of the red-light high-voltage light-emitting chip is reduced and the production efficiency is improved while the red-light high-voltage light-emitting chip with high brightness and low driving power consumption is realized.

The invention provides a magnetic storage structure and a preparation method thereof, electronic equipment and a read-write method. The magnetic storage structure comprises a spin-orbit moment coupling layer and a plurality of magnetic storage elements. Wherein each magnetic storage element comprises a magnetic tunnel junction and a one-way conducting piece, the magnetic tunnel junctions in the multiple magnetic storage elements are arranged on the spin orbit moment coupling layer in parallel, and the one-way conducting pieces are connected to the sides, away from the spin orbit moment coupling layer, of the magnetic tunnel junctions. According to the magnetic storage structure, the storage states of a plurality of magnetic tunnel junctions can be operated through one spin-orbit moment coupling layer, so that the array density of the magnetic storage structure is effectively improved. In addition, the magnetic storage structure can also improve the sneak current problem and improve the read-write precision of the device.

The invention provides a magnetoresistive random access memory structure and a preparation method thereof. The method comprises the following steps: providing a substrate; forming a magnetic tunnel junction film layer on the substrate; forming a first dielectric layer on the magnetic tunnel junction film layer; etching the two ends of the first dielectric layer in the first direction so as to enable the two opposite ends of the magnetic tunnel junction film layer in the first direction to extend out of the etched first dielectric layer; forming a metal layer on the magnetic tunnel junction film layer, wherein the metal layer wraps the etched first dielectric layer; and etching the metal layer to form top electrodes on two opposite sides of the first dielectric layer along the first direction. According to the invention, the yield of the MRAM can be improved.

A 3D magnetic memory device includes a stack having dielectric layers and silicon-based layers arranged alternately, and a magnetic material channel formed through the stack. The channel has a first diameter at which it extends through the silicon-based layer and a second diameter at which it extends through the dielectric layer. Pinning sites defined by layers are formed in the channel, each pinning site configured to store one magnetic potential. A first metal layer is disposed on the first end of the channel and the stack. A magnetic tunnel junction (MTJ) and a first electrode are arranged on the first metal layer at a distance from each other. The first metal layer is configured as a spin-orbit torque (SOT) orbit, or the second metal layer is configured as a SOT orbit, where the second end of the channel and the stack are disposed on the second metal layer.

The invention provides a semiconductor structure, which comprises a plurality of magnetic tunnel junction (MTJ) elements. Seen from a top view, the MTJ elements are arranged in an array, at least one second contact structure is located in the array arranged by the MTJ elements, and at least one first mask layer covers a top surface and two sidewalls of each MTJ element, when seen from a cross-sectional view, a sidewall of the first mask layer is aligned with a sidewall of a second metal layer which is disposed below the second contact structure.

A semiconductor device includes a first substrate, a transistor, an interconnection structure, a first bonding pad, a magnetic tunnel junction (MTJ) structure, a conductive line and a second substrate. The transistor is formed on the first substrate. The interconnection structure is formed on the first substrate and electrically connected to the transistor. The first bonding pad is formed on and electrically connected to the interconnection structure. The MTJ structure is disposed on and electrically connected to the first bonding pad, wherein the MTJ structure comprises a free layer, a tunnel barrier layer, a synthetic antiferromagnet layer sequentially stacked up over the first bonding pad. The conductive line is disposed on the MTJ structure. The second substrate is disposed on the conductive line.

A semiconductor laser device includes a first metamaterial element, a semiconductor substrate having a main surface, and a multijunction active region arranged over the main surface of the semiconductor substrate between the first metamaterial element and the semiconductor substrate. The multijunction active region includes a plurality of active regions each comprising a multiple-quantum-well (MQWs), and a plurality of tunnel junction layers providing electrical coupling and located between neighboring active regions along a vertical direction perpendicular to the main surface of the semiconductor substrate.

Embodiments of the present application provide an MRAM device, comprising: a first dielectric layer located above a substrate and having a first opening; a second dielectric layer located above the first dielectric layer and having a second opening; a variable resistance memory cell comprising a first electrode, a second electrode, and a magnetic tunnel junction layer located between the first electrode and the second electrode, the first electrode located in the first opening and having a rectangular cross-section, a top surface of the first electrode in contact with a bottom surface of the magnetic tunnel junction layer, the second electrode and the magnetic tunnel junction layer located in the second opening; the magnetic tunnel junction layer having a U-shaped cross-section and surrounding sidewalls and a bottom surface of the second electrode; a top surface of the second electrode coplanar with a top surface of the second dielectric layer; the second dielectric layer comprising an etch stop layer and an intermediate layer located above the etch stop layer, a peripheral width of the first electrode less than or equal to a peripheral width of the U-shaped cross-section of the magnetic tunnel junction layer. Embodiments of the present application relate to a method of forming an MRAM device.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, the semiconductor device comprises a plurality of storage units which are located on a substrate and distributed in an array at intervals, and each storage unit comprises a transistor and a magnetic tunnel junction which are stacked on the substrate; the transistor comprises a first electrode, a second electrode, a semiconductor layer and a gate electrode, the semiconductor layer is located between the first electrode and the second electrode and extends in the direction perpendicular to the substrate, the gate electrode is insulated from the semiconductor layer, and the semiconductor layer at least partially surrounds the gate electrode; the second electrode is connected with the magnetic tunnel junction. The semiconductor device provided by the embodiment of the invention can have higher storage density, and the adjustable range of the size of the gate electrode is relatively large.

Provided are a reconfigurable neuron device based on ion gate regulation and a method of preparing the same. The device includes: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer and a top electrode layer which are sequentially stacked from bottom to top. A left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions are provided on two opposite edges of a bottom end of the synthetic antiferromagnetic layer, and a magnetic tunnel junction configured to output a spike signal is further provided in a middle portion of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer and the top electrode layer constitute an ion gate, the ionic liquid layer includes a positive ion and a negative ion.

In a method of manufacturing a magnetic memory device, a temporary shift cancel layer including X metal atoms and Y metal atoms as free atoms may be formed. A magnetic tunnel junction layer may be formed on the temporary shift cancel layer. The magnetic tunnel junction layer and the temporary shift cancel layer may be etched to form a magnetic tunnel junction pattern and a temporary shift cancel pattern. The Y metal atoms redeposited between the magnetic tunnel junction pattern and the temporary shift cancel pattern may be oxidized to form metal oxide. The Y metal atoms of the temporary shift cancel pattern may be substituted with Z metal atoms to form a shift cancel pattern. The Y metal atoms may have higher oxidizing than the Z metal atoms. The Z metal atoms may have a higher reduction potential than the Y metal atoms.

A semiconductor device comprising a variable resistance memory layer, wherein the memory layer includes a magnetic tunnel junction structure including a free layer having a changeable magnetization direction, a fixed layer having a fixed magnetization direction, a tunnel barrier layer disposed between the free layer and the fixed layer, and a magnetic oxide layer disposed on a sidewall of the free layer.

A magnetic memory device includes a substrate, a base insulating film on the substrate, a magnetic tunnel junction element including first and second magnetic patterns and a tunnel barrier pattern therebetween on the base insulating film, an upper electrode pattern on an upper face of the magnetic tunnel junction element, a capping structure including a first to third capping films sequentially stacked on a side face of the magnetic tunnel junction element, and a conductive line on both the upper electrode pattern and the capping structure and connected to the upper electrode pattern. An uppermost end of the second capping film is higher than an uppermost end of the first capping film, an uppermost end of the third capping film is lower than the uppermost end of the first capping film, and the second capping film includes a material different from respective materials of the first and third capping films.

The application provides a semiconductor structure preparation method, a semiconductor structure and a memory. The semiconductor structure preparation method comprises the following steps: providing a substrate; sequentially forming a magnetic composite layer and a transfer mask layer on the substrate; performing a plurality of mask etching processes on the transfer mask layer to form a plurality of mask patterns arranged in an array in the transfer mask layer, and the transfer mask layer between at least part of the mask patterns forms a transfer pattern; and etching the magnetic composite layer along the transfer pattern to form a plurality of columnar structures arranged in an array, and the columnar structures form magnetic tunnel junctions. Adjacent columnar structures are isolated by gaps. The application facilitates the preparation of a semiconductor structure with high-density magnetic tunnel junctions, and can effectively adjust the size of the magnetic tunnel junctions and reduce the difficulty of preparing the semiconductor structure.

A spin orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having a (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or a combination thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or a combination thereof, where M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

The invention relates to the technical field of semiconductor lasers, in particular to a high-speed communication vertical-cavity surface-emitting laser and a preparation method thereof.The high-speed communication vertical-cavity surface-emitting laser comprises a substrate, an epitaxial structure is arranged on the substrate and comprises an active area, a transition DBR layer is arranged on the active area, and a tunnel junction is arranged in the center of the transition DBR layer; the tunnel junction comprises a P-type high-concentration C doping layer and an N-type high-concentration Te doping layer, and a top DBR layer is arranged on the transition DBR layer. The tunnel junction is used for replacing an oxide layer of a traditional oxidizing VCSEL and is used for providing current limitation and optical limitation. According to a traditional oxide layer, the oxidation depth is controlled by oxidizing Al0. 98Ga0. 02As to achieve current and optical limitation of the oxidation caliber, Al interface oxidation can be avoided by replacing the traditional oxide layer with a tunnel junction structure, and the problem of further growth of defects can be prevented. An oxide layer is replaced by a tunnel junction limiting structure, higher emission uniformity and higher repeatability manufacturing can be achieved, the size of an oxidation aperture can be accurately defined, and the stability of a mode can be controlled.

Provided is a double-stack type semiconductor light-emitting element having good output characteristics and enabling improvement of reverse voltage characteristics (reduction of leakage current).　A double-stack type semiconductor light-emitting element 100 comprises, in this order: a first n-type semiconductor layer 140; an undoped first active layer 144; a p-type pseudo tunnel junction layer 1471 having a p-type dopant; an n-type pseudo tunnel junction layer 1472 having an n-type dopant and provided in contact with the p-type pseudo tunnel junction layer 1471; an undoped second active layer 149; and a second p-type semiconductor layer 150. The maximum value of the impurity concentration of the n-type dopant included on the n-type pseudo tunnel junction layer 1472 side of the second active layer 149 is 1.0 × 1016 atoms / cm3 or less.

The invention discloses an atomic-scale construction method for manufacturing a semiconductor substrate quantum simulator, which comprises the following steps: firstly, depositing singly distributed metal atoms on a semiconductor substrate at a controllable deposition rate by adopting a vacuum thermal evaporation method, and then depositing metal atoms on the semiconductor substrate at a controllable deposition rate by utilizing a longitudinal control method of a scanning tunneling microscope (STM). The metal atoms adsorbed on the surface of the substrate are carried at a target position by accurately regulating and controlling the dragging speed of the needle tip, the tunnel junction bias voltage and the tunneling current, so that lifting, placing and moving of a single atom are realized. The construction of artificial quantum dots and quantum dot molecules is realized by regulating and controlling the distance between metal atoms. A source electrode, a drain electrode and a grid electrode of quantum dot molecules are controlled in an integrated mode through vacuum evaporation, and the quantum simulator capable of simulating quantum behaviors of a specific molecular structure is formed. According to the invention, the coupling strength of the artificial quantum dot molecules is accurately regulated and controlled through the external grid voltage, and the quantum characteristics of molecule front track filling and electron transport kinematics thereof can be accurately simulated.

The invention relates to the technical field of integrated circuits, and provides a ferroelectric tunnel junction, a memory and a ferroelectric tunnel junction preparation method, the ferroelectric tunnel junction comprises an electrode layer, a ferroelectric layer, a conductive function layer and a semiconductor layer, the ferroelectric layer is located between the electrode layer and the conductive function layer, and the semiconductor layer is located between the electrode layer and the conductive function layer. The semiconductor layer is located on the side, away from the ferroelectric layer, of the conductive functional layer, and the thickness of the conductive functional layer is smaller than or equal to 10 nm. According to the ferroelectric tunnel junction, the conductive function layer is introduced into the ferroelectric tunnel junction with the structure, so that the switching ratio and the stability of the ferroelectric tunnel junction are improved, and the problem of high power consumption caused by relatively high reading voltage is avoided.

The present disclosure provides a magnetoresistive random access memory (MRAM), including a magnetic tunnel junction (MTJ) and a transistor structure. The magnetic tunnel junction includes a magnetic fixed layer, a tunnel barrier layer, a magnetic free layer and at least one magnetic enhancement layer. The tunnel barrier layer is stacked with the magnetic fixed layer. The magnetic free layer is stacked with the tunnel barrier layer. The at least one magnetic enhancement layer is disposed corresponding to at least one of the magnetic free layers or the magnetic fixed layers. The transistor structure is electrically connected to the magnetic tunnel junction.