10 results about "Tunnel current" patented technology

A device for characterization of polymers is described. The device includes a plurality of atomically thin electrodes with their edges exposed along a fluidic channel through which a single stranded polymer molecule is controllably positioned. The polymer includes a series of subunits where each in sequence is identified by an electrical signal between two of the electrodes when in contact with the two electrodes. The position of the polymer strand within the fluidic channel is controlled by voltages applied to the atomically thin electrodes as well as global electrodes located within the fluidic channel. The electrical signal includes tunneling currents along the length of each segment, ionic currents within solutions containing the polymer segments, and, in some embodiments tunneling currents across each polymer segment, and, based upon those measurements, identifying the chemical composition of each segment and therefore the chemical composition of the polymer as a sequence of subunits.

The application discloses a differential gate tunneling current monitoring and resetting circuit applied to a low-power intermittent phase-locked loop, comprising a phase-locked loop (PLL), a second switch, a copy capacitor, a virtual device, a positive threshold comparator, a phase-locked loop state indication module and a crystal oscillator, wherein the phase-locked loop (PLL) comprises a phase-frequency discriminator, a charge pump, a series RC filter, a first switch, a filter capacitor, a voltage-controlled oscillator and a frequency divider, and the application realizes a leakage monitoring and resetting mode which is independent of PLL locking initial value, has strong robustness and low static power consumption, does not need an additional low-frequency clock, reduces power consumption and area, accurately controls frequency drift, adapts to flexible requirements, partially offsets temperature influence, enhances environmental adaptability, simplifies circuit control logic and improves working reliability.

Embodiments of the present disclosure provide a vacuum transistor, an array substrate and an electronic device, and relate to the technical field of vacuum electronics, and are used for improving the control of the gate on the vacuum tunneling current and improving the on-off ratio of the vacuum transistor. The vacuum transistor comprises a substrate, a first electrode, a gate, a second electrode and a via hole. The first electrode, the gate and the second electrode are sequentially stacked on the substrate along a first direction and a direction gradually away from the substrate, and the first direction is the thickness direction of the substrate. The first electrode and the gate, and the gate and the second electrode are both spaced apart along the first direction. The via hole penetrates the second electrode and the film layer between the second electrode and the first electrode along the first direction, and exposes the side surface of the first electrode away from the substrate. The orthogonal projection of the gate on the substrate and the orthogonal projection of the second electrode on the substrate overlap.

The application discloses a kind of based on monitoring incremental data's operation railway tunnel state rapid evaluation method, belong to railway tunnel state evaluation field, including: based on tunnel basic data, the deformation and stress mechanism of tunnel lining structure is analyzed using three-dimensional numerical simulation method, and the logical relationship between lining structure deformation, stress and safety factor is established;Based on periodic inspection and special detection, obtain real-time data under the operation state of tunnel, based on logical relationship, the real-time evaluation result of structure safety under the operation state of tunnel is obtained;Long-term monitoring data of tunnel structure is used to correct real-time evaluation result, and the corrected logical relationship is obtained;The actual data of tunnel current is obtained by rapid detection equipment, and the rapid evaluation of tunnel lining structure safety state is realized by combining the corrected logical relationship.The application effectively solves the problems of low data utilization, inaccurate evaluation and inability to quickly respond to tunnel state changes in traditional methods.

This invention discloses a method, storage medium, and device for constructing a proton irradiation effect prediction model for InP heterojunction bipolar transistors (HBTs). The method includes establishing an equivalent circuit topology and characteristic prediction equations, introducing parasitic diodes and tunneling current sources to characterize the characteristic degradation caused by proton irradiation, and introducing DC and RF model parameter degradation equations to characterize the degradation of device electrical characteristics with flux. This enables the model to accurately predict various electrical characteristics of InP HBTs after proton irradiation. This invention solves the difficulty of accurately characterizing the electrical characteristics of devices after high-flux proton irradiation using the classical Agilent HBT model, providing technical support for predicting on-orbit operating characteristics and lifetime of devices, as well as for radiation-hardened design of space integrated circuits.

This invention discloses a dual-mode self-calibrating MEMS accelerometer and its calibration method, belonging to the field of microelectromechanical system (MEMS) sensor technology. It includes a substrate, a mass block, a differential capacitance detection unit, an electrothermal driving unit, a tunneling current generation unit, and a data processing unit. The differential capacitance detection unit is located on both sides of the mass block along the sensitive axis and is used to detect the differential capacitance caused by the movement of the mass block. The differential capacitance detection unit includes a movable electrode fixed to one side of the mass block and a fixed electrode mounted on the substrate. The electrothermal driving unit is connected to the fixed electrode and is used to drive the fixed electrode to move closer to or away from the movable electrode. The tunneling current generation unit is located opposite each other at both ends of the mass block and is used to calibrate a specified position. When the mass block moves to the specified position, it generates a tunneling current and a capacitance value corresponding to the tunneling current. This invention achieves high-precision online self-calibration under all operating conditions.

The invention belongs to the technical field of semiconductor devices, and discloses a single-ended tunnel junction P-channel gallium nitride transistor and a preparation method thereof.The single-ended tunnel junction P-channel gallium nitride transistor comprises a substrate layer, a buffer layer, a barrier layer, a p cap layer and a p + + cap layer which are sequentially stacked, and the center of the stacked structure is provided with a groove with the bottom located in the p cap layer; the n + + cap layer is located on the p + + cap layer on one side of the groove, and a drain electrode is arranged on the p + + cap layer on the other side of the groove; a source electrode is arranged on the n + + cap layer; a dielectric layer is arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode are in contact with the dielectric layer; and a gate electrode is arranged on the dielectric layer. According to the single-ended tunnel junction P-channel gallium nitride transistor, the single-ended tunnel junction structure is introduced between the p cap layer and the source electrode, so that the on-resistance of a channel is remarkably reduced, the injection efficiency of carriers is improved, the tunneling current is remarkably improved, and monolithic integration with an N-channel device piece can be realized on the same process line.

The invention discloses a differential gate tunneling current monitoring and resetting circuit applied to a low-power-consumption intermittent phase-locked loop, which comprises a phase-locked loop (PLL), a second switch, a copy capacitor, a virtual device, a positive threshold comparator, a phase-locked loop state indication module and a crystal oscillator, the phase-locked loop (PLL) comprises a phase detection discriminator, a charge pump, a series RC filter, a first switch, a filter capacitor, a voltage-controlled oscillator and a frequency divider, an electric leakage monitoring and resetting mode which is irrelevant to a PLL locking initial value, high in robustness and low in static power consumption is achieved, an extra low-frequency clock is not needed, power consumption and area are reduced, frequency drift is accurately controlled, and the reliability of the electric leakage monitoring and resetting circuit is improved. The adaptive flexible requirements are met, the temperature influence is partially counteracted, the environmental adaptability is enhanced, the circuit control logic is simplified, and the working reliability is improved.

We provide semiconductor devices with large memory capacity. [Solution] A semiconductor device having a plurality of insulators, a first conductor 132A and a first semiconductor 151, wherein the first conductor is located on the first upper surface of the first insulator 101A and on the first lower surface of the second insulator 101B. The third insulator 102 is located in a region including the side surface of the first insulator, the second upper surface of the first insulator, the side surface of the first conductor, the second lower surface of the second insulator, and the side surface of the second insulator. On the formation surface of the third insulator, a fourth insulator 111, a fifth insulator 104, and a first semiconductor are stacked in order, and the sixth insulator 109a is located in a region of the formation surface of the fifth insulator that overlaps with the first conductor. The seventh insulator 105 is located in a region including the formation surface of the first semiconductor and the formation surface of the sixth insulator. The fourth insulator has the function of accumulating charge, and by applying a potential to the first conductor, a tunnel current is induced between the first semiconductor and the fourth insulator via the fifth insulator.