21 results about "Tunnel current" patented technology

The invention discloses a method for acquiring passive intermodulation interference caused by oxidation corrosion of a base station antenna, and aims to further supplement and improve the existing research so as to quantitatively evaluate the passive intermodulation interference generated after the oxidation corrosion of the base station antenna. An analysis object is set as the side surface of a microstrip line conductor, firstly, the amplitude coefficient AD2 of voltage of each point in the lower edge area of the side surface of an unoxidized and corroded microstrip line under the action of a single carrier signal is determined, and then after it is determined that the microstrip line is oxidized and corroded, the amplitude coefficient AD2 of voltage of each point is determined. According to the method, the tunneling current density JMIM and the total tunneling current IMIM of the oxidation corrosion areas are obtained according to the average voltage value of the oxidation corrosion areas, and on the basis, the third-order passive intermodulation voltage V3rd-PIM (t) is calculated, so that the passive intermodulation interference generated after oxidation corrosion of the base station antenna is quantitatively evaluated.

The embodiment of the present application provides a stress sensor and a preparation method thereof, and a stress sensing device. When the upper substrate or the lower substrate of the stress sensor is subjected to pressure, the elastic insulating protrusion structure of the tunneling layer is deformed, so that the distance between the low-square-resistance layer and the high-square-resistance layer is shortened, and a tunneling effect occurs, generating a tunneling current, and the magnitude of the tunneling current is proportional to the magnitude of the pressure. The present invention fills a tunneling layer between the high-square-resistance layer and the low-square-resistance layer instead of a traditional gasket structure, thereby greatly reducing the thickness of the stress sensor, reducing the minimum stress trigger threshold, and improving the sensitivity of the sensor, which can realize the extraction of weak signals and effectively extend the life of the sensor.

The invention belongs to the technical field of electrical parameter testing and electrical fault diagnosis, and discloses a fault detection method for a redundant relay voting system, which comprises the following steps: acquiring real-time contact voltage and contact equivalent capacitance between contacts, and analyzing to obtain real-time electric field intensity and effective spacing; according to the real-time electric field intensity and the effective spacing, analyzing to obtain a quantum tunneling probability and a quantum tunneling current; a current mirror circuit is connected in parallel between the contacts, main current is acquired and obtained, and a current signal is obtained by combining quantum tunneling current; counting the current signals in a preset time period and analyzing to obtain a Fano factor; judging a state signal of the pre-built redundant architecture, performing state voting, triggering frequency domain verification according to a state voting result, and obtaining a fault positioning result by combining Fano factor analysis; judging based on a fault decision tree according to the fault positioning result to obtain a fault judgment result; according to the invention, a full-process technical guarantee from current signal acquisition to fault decision is provided for the operation of a redundant equipment system.

The invention provides a multi-time programmable non-volatile storage structure, an array and an operation method, the multi-time programmable non-volatile storage structure is equivalent to a structure in which a control capacitor and a floating gate capacitor are connected in series, when voltage is applied to a source line end SL and a word line end WL, the control capacitor can control the voltage drop on the floating gate capacitor, and the voltage drop on the floating gate capacitor is reduced. And when the voltage drop meets the tunneling condition, F-N tunneling current is generated, and charges can move back and forth between the floating gate and the second doped well through the gate dielectric layer in the floating gate electrode, so that the purposes of erasing and programming the device are achieved. The purposes of multi-time programming and nonvolatile storage can be achieved through one capacitor and one floating gate transistor, the number of tubes is effectively reduced, and therefore the area of a storage unit is greatly reduced; meanwhile, the programming and erasing processes are both based on the tunneling effect, the power consumption of the device is effectively reduced, and the effects of miniaturization, low power consumption and low cost are achieved.

A device for characterization of polymers is described. The device includes a plurality of atomically thin electrodes with their edges exposed along a fluidic channel through which a single stranded polymer molecule is controllably positioned. The polymer includes a series of subunits where each in sequence is identified by an electrical signal between two of the electrodes when in contact with the two electrodes. The position of the polymer strand within the fluidic channel is controlled by voltages applied to the atomically thin electrodes as well as global electrodes located within the fluidic channel. The electrical signal includes tunneling currents along the length of each segment, ionic currents within solutions containing the polymer segments, and, in some embodiments tunneling currents across each polymer segment, and, based upon those measurements, identifying the chemical composition of each segment and therefore the chemical composition of the polymer as a sequence of subunits.

In a first aspect, the invention relates to a MEMS microphone for detecting acoustic signals. The MEMS microphone exhibits a vibratable microphone membrane which is induced into vibrations by sound waves passing through a sound inlet opening. Furthermore, the MEMS microphone exhibits a cantilever comprising a measuring tip. The cantilever is actively induced into vibrations by an actuator such that the measuring tip is guided to the microphone membrane in a contactless vibrating manner. A tunnel current flows between the microphone membrane and the measuring tip, with which the vibration behavior of the microphone membrane, which is dependent on the sound waves, can be detected. An electronic circuit is configured to measure the tunnel current between the microphone membrane and the measuring tip. The MEMS microphone according to the invention makes it possible to detect particularly low sound pressure levels with high resolution.In a further aspect, the invention relates to methods for detecting acoustic signals using the MEMS microphone according to the invention.

The application discloses a differential gate tunneling current monitoring and resetting circuit applied to a low-power intermittent phase-locked loop, comprising a phase-locked loop (PLL), a second switch, a copy capacitor, a virtual device, a positive threshold comparator, a phase-locked loop state indication module and a crystal oscillator, wherein the phase-locked loop (PLL) comprises a phase-frequency discriminator, a charge pump, a series RC filter, a first switch, a filter capacitor, a voltage-controlled oscillator and a frequency divider, and the application realizes a leakage monitoring and resetting mode which is independent of PLL locking initial value, has strong robustness and low static power consumption, does not need an additional low-frequency clock, reduces power consumption and area, accurately controls frequency drift, adapts to flexible requirements, partially offsets temperature influence, enhances environmental adaptability, simplifies circuit control logic and improves working reliability.

Embodiments of the present disclosure provide a vacuum transistor, an array substrate and an electronic device, and relate to the technical field of vacuum electronics, and are used for improving the control of the gate on the vacuum tunneling current and improving the on-off ratio of the vacuum transistor. The vacuum transistor comprises a substrate, a first electrode, a gate, a second electrode and a via hole. The first electrode, the gate and the second electrode are sequentially stacked on the substrate along a first direction and a direction gradually away from the substrate, and the first direction is the thickness direction of the substrate. The first electrode and the gate, and the gate and the second electrode are both spaced apart along the first direction. The via hole penetrates the second electrode and the film layer between the second electrode and the first electrode along the first direction, and exposes the side surface of the first electrode away from the substrate. The orthogonal projection of the gate on the substrate and the orthogonal projection of the second electrode on the substrate overlap.

The invention discloses a vehicle-mounted Ethernet defense method based on quantum decoupling and chaotic dynamic fingerprints, and relates to the field of vehicle-mounted Ethernet security authentication and dynamic defense. According to the method, a tunable laser source is used for driving a graphene metamaterial quantum resonant cavity array to perform high-precision decoupling on a mixed Ethernet signal; bias voltage and temperature compensation are adjusted in real time to guarantee stable separation; then, quantum tunneling current fluctuation and equipment inherent electric noise are introduced into a nonlinear dynamic circuit, spatiotemporal chaotic attractors are generated based on an improved Lorenz equation, and chaotic features are extracted; and then the quantum noise and the chaotic attractor are fused according to Hash to generate a 256-bit dynamic fingerprint, dynamic key negotiation is completed in combination with a Challenge-Response protocol, and cross-layer linkage defense is realized in a physical layer, a data link layer and an application layer through quantum noise fingerprint anomaly detection, MAC address chaotic confusion and SM9 algorithm key rotation.

Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

The application discloses a kind of based on monitoring incremental data's operation railway tunnel state rapid evaluation method, belong to railway tunnel state evaluation field, including: based on tunnel basic data, the deformation and stress mechanism of tunnel lining structure is analyzed using three-dimensional numerical simulation method, and the logical relationship between lining structure deformation, stress and safety factor is established;Based on periodic inspection and special detection, obtain real-time data under the operation state of tunnel, based on logical relationship, the real-time evaluation result of structure safety under the operation state of tunnel is obtained;Long-term monitoring data of tunnel structure is used to correct real-time evaluation result, and the corrected logical relationship is obtained;The actual data of tunnel current is obtained by rapid detection equipment, and the rapid evaluation of tunnel lining structure safety state is realized by combining the corrected logical relationship.The application effectively solves the problems of low data utilization, inaccurate evaluation and inability to quickly respond to tunnel state changes in traditional methods.

This invention discloses a method, storage medium, and device for constructing a proton irradiation effect prediction model for InP heterojunction bipolar transistors (HBTs). The method includes establishing an equivalent circuit topology and characteristic prediction equations, introducing parasitic diodes and tunneling current sources to characterize the characteristic degradation caused by proton irradiation, and introducing DC and RF model parameter degradation equations to characterize the degradation of device electrical characteristics with flux. This enables the model to accurately predict various electrical characteristics of InP HBTs after proton irradiation. This invention solves the difficulty of accurately characterizing the electrical characteristics of devices after high-flux proton irradiation using the classical Agilent HBT model, providing technical support for predicting on-orbit operating characteristics and lifetime of devices, as well as for radiation-hardened design of space integrated circuits.

The present invention discloses a feedback two-terminal fuse memory cell and a preparation method thereof. Based on the traditional two-terminal fuse, the feedback two-terminal fuse memory cell of the present invention adds a vertical metal gate, and the gate is made on the drain side and electrically connected to the drain. After applying a voltage at the drain end, a lateral voltage VDS and a vertical voltage VGS will be generated simultaneously, and the magnitudes of the two voltages are equal. By reasonably designing the thickness of the gate oxide layer, the breakdown from the gate to the channel in the vertical direction can occur first. The breakdown in the vertical direction is achieved through the tunneling current from the gate to the channel. This design can reduce the programming voltage and programming current and achieve mild low power consumption. The present invention uses electron beam lithography and lift-off processes to realize the preparation of the fuse memory cell. The process is simple, can realize the preparation of large-area devices and save process costs.

This invention discloses a dual-mode self-calibrating MEMS accelerometer and its calibration method, belonging to the field of microelectromechanical system (MEMS) sensor technology. It includes a substrate, a mass block, a differential capacitance detection unit, an electrothermal driving unit, a tunneling current generation unit, and a data processing unit. The differential capacitance detection unit is located on both sides of the mass block along the sensitive axis and is used to detect the differential capacitance caused by the movement of the mass block. The differential capacitance detection unit includes a movable electrode fixed to one side of the mass block and a fixed electrode mounted on the substrate. The electrothermal driving unit is connected to the fixed electrode and is used to drive the fixed electrode to move closer to or away from the movable electrode. The tunneling current generation unit is located opposite each other at both ends of the mass block and is used to calibrate a specified position. When the mass block moves to the specified position, it generates a tunneling current and a capacitance value corresponding to the tunneling current. This invention achieves high-precision online self-calibration under all operating conditions.

The invention belongs to the technical field of semiconductor devices, and discloses a single-ended tunnel junction P-channel gallium nitride transistor and a preparation method thereof.The single-ended tunnel junction P-channel gallium nitride transistor comprises a substrate layer, a buffer layer, a barrier layer, a p cap layer and a p + + cap layer which are sequentially stacked, and the center of the stacked structure is provided with a groove with the bottom located in the p cap layer; the n + + cap layer is located on the p + + cap layer on one side of the groove, and a drain electrode is arranged on the p + + cap layer on the other side of the groove; a source electrode is arranged on the n + + cap layer; a dielectric layer is arranged between the source electrode and the drain electrode, and the source electrode and the drain electrode are in contact with the dielectric layer; and a gate electrode is arranged on the dielectric layer. According to the single-ended tunnel junction P-channel gallium nitride transistor, the single-ended tunnel junction structure is introduced between the p cap layer and the source electrode, so that the on-resistance of a channel is remarkably reduced, the injection efficiency of carriers is improved, the tunneling current is remarkably improved, and monolithic integration with an N-channel device piece can be realized on the same process line.

The invention discloses a differential gate tunneling current monitoring and resetting circuit applied to a low-power-consumption intermittent phase-locked loop, which comprises a phase-locked loop (PLL), a second switch, a copy capacitor, a virtual device, a positive threshold comparator, a phase-locked loop state indication module and a crystal oscillator, the phase-locked loop (PLL) comprises a phase detection discriminator, a charge pump, a series RC filter, a first switch, a filter capacitor, a voltage-controlled oscillator and a frequency divider, an electric leakage monitoring and resetting mode which is irrelevant to a PLL locking initial value, high in robustness and low in static power consumption is achieved, an extra low-frequency clock is not needed, power consumption and area are reduced, frequency drift is accurately controlled, and the reliability of the electric leakage monitoring and resetting circuit is improved. The adaptive flexible requirements are met, the temperature influence is partially counteracted, the environmental adaptability is enhanced, the circuit control logic is simplified, and the working reliability is improved.

We provide semiconductor devices with large memory capacity. [Solution] A semiconductor device having a plurality of insulators, a first conductor 132A and a first semiconductor 151, wherein the first conductor is located on the first upper surface of the first insulator 101A and on the first lower surface of the second insulator 101B. The third insulator 102 is located in a region including the side surface of the first insulator, the second upper surface of the first insulator, the side surface of the first conductor, the second lower surface of the second insulator, and the side surface of the second insulator. On the formation surface of the third insulator, a fourth insulator 111, a fifth insulator 104, and a first semiconductor are stacked in order, and the sixth insulator 109a is located in a region of the formation surface of the fifth insulator that overlaps with the first conductor. The seventh insulator 105 is located in a region including the formation surface of the first semiconductor and the formation surface of the sixth insulator. The fourth insulator has the function of accumulating charge, and by applying a potential to the first conductor, a tunnel current is induced between the first semiconductor and the fourth insulator via the fifth insulator.

To solve a problem of a physical limit of thinning of a gate insulation layer when the gate insulation layer is a single layer of a silicon oxide film due to increase in tunnel current, that is, gate leakage current although a minute transistor requires thinning of the gate insulation layer.SOLUTION: In a semiconductor device, gate leakage current of a minute transistor is reduced by using a high-k film having a dielectric constant of 10 and more for a gate insulation layer. By using the high-k film as a first insulation layer having a dielectric constant higher than that of a second insulation layer which contacts an oxide semiconductor layer, the gate insulation layer can be thinned to a further degree than a gate insulation layer in the case of being converted to a silicon oxide film.SELECTED DRAWING: Figure 1

The utility model relates to a current detection system used for a three-phase collectively-wrapped cable. The current detection system comprises a master control module, a signal conditioner, three magnetic tunnel current sensors and a power supply module. The three magnetic tunnel current sensors are arranged on the outer surface of the three-phase collectively-wrapped cable, so that the three magnetic tunnel current sensors and the three cable cores are in one-to-one correspondence, and the current signal of each cable core can be accurately measured based on the tunnel magnetic resistance technology. Therefore, current parameters are provided for cable operation state and harmonic analysis, and guarantee is provided for stable operation of the cable, a power grid and electric equipment. Meanwhile, through the arrangement of the signal conditioner, current signals transmitted by the three magnetic tunnel current sensors can be received, stable current can be provided for the three magnetic tunnel current sensors, and continuous and stable operation of the magnetic tunnel current sensors is guaranteed.

This invention belongs to the field of electrical parameter testing and electrical fault diagnosis technology, and discloses a fault detection method for a redundant relay voting system, including: acquiring real-time contact voltage and equivalent capacitance between contacts, and analyzing to obtain real-time electric field strength and effective spacing; analyzing to obtain quantum tunneling probability and quantum tunneling current based on real-time electric field strength and effective spacing; connecting a current mirror circuit in parallel between contacts to acquire the main current, and combining it with the quantum tunneling current to obtain a current signal; statistically analyzing the current signal within a preset time period to obtain the Fano factor; judging the state signal of the pre-built redundant architecture and performing state voting, triggering frequency domain verification based on the state voting result, and combining it with the Fano factor analysis to obtain the fault location result; and making a judgment based on the fault location result using a fault decision tree to obtain the fault judgment result. This invention provides a full-process technical guarantee for the operation of redundant equipment systems, from current signal acquisition to fault decision-making.