104 results about "Tunnel current" patented technology

It is important to ensure good selectivity of a single magnetic tunnel junction storage cell within a memory array without affecting nearby storage cells. For this purpose, this memory array of storage cells preferably comprises a) an array of electrically conducting bit lines and electrically conducting word lines which form intersections therebetween, b) a storage cell disposed at each of said intersections, each storage cell comprising at least one reversible magnetic region or layer characterized by a magnetization state which can be reversed by applying thereto a selected external magnetic field, said reversible magnetic layer comprising a material whose magnetization state is more easily reversed upon a change in the temperature thereof, and c) a temperature change generator for changing the temperature of said reversible magnetic layer of only a selected one of said array of storage cells at any moment. To select a cell, it is preferable to select a cell by using a brief pulse of tunnelling current between the intersecting bit and word lines at that cell in order to provide sufficient Joule heating to facilitate a change in the magnetization state of its reversible magnetic layer, which preferably comprises a ferrimagnetic material.

A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier structure covering the channel region. A second tunneling barrier is disposed above the floating gate. A dielectric charge trapping structure disposed above the second tunneling barrier and a blocking dielectric structure is disposed above the charge trapping structure. A top conductive layer disposed above the top dielectric structure acts as a gate. The second tunneling barrier is a more efficient conductor of tunneling current, under bias conditions applied for programming and erasing the memory cell, than the first tunneling barrier structure.

The invention discloses a back contact silicon solar battery, which comprises an N type monocrystalline silicon piece subjected to surface texturing, wherein a first N type heavy doping layer is arranged at the front side of the N type monocrystalline silicon piece, a silicon dioxide (SiO2) passivation layer and a reflection reduction film layer are sequentially arranged at the outer side of the first N type heavy doping layer, a second N type heavy doping layer and a P type heavy doping layer are arranged at the back side of the N type monocrystalline silicon piece in a mutual separating way, second SiO2 passivation layers are arranged at the outer side of the second N type heavy doping layer and the P type heavy doping layer, a heavy doping AZO film layer and silver slurry are sequentially arranged outside the second SiO2 passivation layer arranged at the second N type heavy doping layer part, and a heavy doping CuAlO2 film layer and silver aluminum slurry are sequentially arranged outside the second SiO2 passivation layer arranged at the P type heavy doping layer part. The invention also discloses a manufacture process of the back contact silicon solar battery. The back contact silicon solar battery and the manufacture method solve the problems that in the prior art, the conversion rate of the solar battery is low, and the back contact battery generally adopts laser punching, so the manufacture cost is high. Through the technical improvement, heavy doping is realized on the contact surface, the heavy-doping low-resistance transparent conductive oxide (TCO) materials are attached to the contact surface so as to form tunnel current, and in addition, a low-temperature slurry sintering method is adopted, the manufacture cost is reduced on the premise that the battery efficiency is ensured.

To provide a NOR-type nonvolatile semiconductor memory that can inject electric charge into a charge accumulation layer through the use of an FN tunnel current without compromising an increase in the packing density of memory cells. The above problem is solved by a nonvolatile semiconductor memory in which nonvolatile semiconductor memory cells are arranged in a matrix, each nonvolatile semiconductor memory cell having an island semiconductor layer in which a drain diffusion layer formed in the upper part of the island semiconductor layer, a source diffusion layer formed in the lower part of the island semiconductor layer, a charge accumulation layer formed on a channel region of the side wall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge accumulation layer are formed. Further, bit lines connected to the drain diffusion layer are laid out in a column direction, control gate lines are laid out in a row direction, and source lines connected to the source diffusion layer are laid out in the column direction.

Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

A displacement detection portion is provided in a lever portion of a cantilever or between the lever portion and a main body portion. The displacement detection portion is provided by laminating two conductor electrodes to sandwich an insulating portion. A thickness of the insulating portion (electrode interval) is set to a value capable of detecting a variation in tunnel current due to a change in electrode interval which corresponds to a displacement of the lever portion while a predetermined voltage is applied. When the lever portion is slightly displaced, the interval between the conductor electrodes changes. Therefore, the displacement may be detected as the variation in tunnel current at high resolution with sensitivity of an exponential multiple of the change in interval.

The invention provides a DNA sequencing device and a manufacturing method. The device mainly comprises a silicon dioxide thin film arranged on a double-side polished monocrystalline silicon piece. A silicon nitride thin film grows on the top of the silicon dioxide thin film. A bottom layer contact electrode is prepared on the silicon nitride thin film and covered with a bottom layer graphene micro-strip. The bottom layer graphene micro-strip is covered with a hexagonal boron nitride micro-strip. The hexagonal boron nitride micro-strip is covered with a top layer graphene micro-strip. A graphene-hexagonal boron nitride-graphene heterostructure is formed by the bottom layer graphene micro-strip, the hexagonal boron nitride micro-strip and the top layer graphene micro-strip. Graphene-hexagonal boron nitride-graphene nano-pores are etched. According to the device, the problem that a conventional solid-state nano-pore channel is too long, so that the sequencing resolution ratio does not reach single base is solved, and the problem that a tunneling electrode is difficult to manufacture in a tunneling current DNA sequencing method is solved. The advantages lay a foundation for achieving single base resolution ratio and direct nano-pore sequencing.

The invention provides a tunneling transistor with hetero-material grid dielectrics and a forming method of the tunneling transistor. The tunneling transistor comprises a substrate, a channel region, a source region, a drain region and a grid stack, wherein the channel region is formed in the substrate; the source region and the drain region are formed in the substrate and respectively at both sides of the channel region; the source region belongs to first type of heavy doping; the drain region belongs to second type of heavy doping; the grid stack is formed on the substrate; the grid stack comprises a grid dielectric layer and a grid electrode, wherein the grid dielectric layer is located on the channel region, and the grid electrode is located on the grid dielectric layer; the grid dielectric layer comprises a first section of grid dielectric near the source region and a second section of grid dielectric near the drain region; and the first section of grid dielectric and the second section of grid dielectric are different in material. Through introducing local stress into the channel region by the first section of grid dielectric near the source region, the tunneling effective mass is changed, and the tunneling current is increased, and through introducing the local stress into the channel region by the second section of grid dielectric near the drain region, the electronic mobility is increased.

The invention relates to a preparation method of an electron emission source nano seam array of a surface conduction electron emitter display (SED). A layer of a laser photoexpansion polymer material is introduced between a transparent base material and an electron emission thin film material with a stress concentration opening, so that a sandwich structure of the transparent base material, the laser photoexpansion polymer material and the electron emission material is formed; laser irradiates the laser photoexpansion polymer material in a seam of a lead electrode on one side, which does not has an electron emission source pattern structure, of the transparent base material, so that the volume of the laser photoexpansion polymer material is expanded and a pulling stress is generated inside the electron emission thin film material on the surface of the laser photoexpansion polymer material; and when the pulling stress reaches a breakage limit of the thin film material, the electron emission thin film material is broken to form a nano crack structure. In the method, by introducing the laser photoexpansion polymer material, the problem of a stress source required by breakage of the electron emission thin film can be solved and the position of a crack can be controlled precisely; meanwhile, array mirror scanning is realized by an in-situ tunnel current control method, and the uniformity of electron emission characteristics of array nano seams can be guaranteed.

The invention discloses a manufacturing method for an atomic power sensor, a sensor, and an atomic power sensor measuring apparatus and a method thereof. The manufacturing method comprises: a lower cantilever of a tuning fork is fixed at a ceramic substrate by an insulation paste, wherein the ceramic pedestal is provided with a tunnel current extraction electrode and a charge extraction electrode and tuning fork electrodes are respectively arranged at the tail end of the upper cantilever and the tail end of the lower cantilever of the tuning fork; a rectangular insulated layer is coated at a position, approaching a free end, of the upper cantilever of the tuning fork; one end portion of a tungsten filament and one end portion of a spun gold are pasted at the rectangular insulated layer, wherein the tungsten filament and the spun gold are respectively perpendicular to the upper cantilever of the tuning fork and the spun gold is in an approximate U shape; the other end of the spun gold is connected with the tunnel current extraction electrode; the tuning fork electrode of the tail end of the upper cantilever of the tuning fork is connected with the charge extraction electrode by a lead; and the free end of the tungsten filament is etched into a shape of a needle tip. According to the invention, a small-amplitude atomic power sensor with precisely controllable parameters can be manufactured rapidly; the proportion of a short-range force in a measuring signal is improved; and the resolution ratio of the sensor is enhanced.

The invention discloses a tunnel type MEMS (Micro-electromechanical Systems) gyroscope and belongs to the technical field of micro-electromechanical systems. The tunnel type MEMS gyroscope provided by the invention comprises a thin plate with a normal hexadecagon shape; the thin plate is used as a sensitive mass block to be bonded on a glass substrate; each edge of the normal hexadecagon shape corresponds to one electrode; the sixteen electrodes are divided into four sets and are respectively used as driving electrodes, adjusting electrodes, feedback electrodes and wedged conical tip electrodes for generating tunneling current; the conical tip electrodes are arranged on a movable comb. The invention provides a brand-new structure and adopts the symmetrical polygonal mass block; the feedback electrodes and the adjusting electrodes are good for realizing the match of a driving modal frequency and a detection modal frequency, and the high sensitivity is realized; meanwhile, the movable comb is used for controlling the distance between the conical tip electrodes and the mass block; the two transverse conical tip electrodes are used for detecting the difference tunnel current so as to be good for reducing the drifting and further improve the detection sensitivity.

Devices, systems and methods for sequencing protein samples are provided. In some examples, currents generated when a monomer passes through between electrodes of a nanogap electrode pair are measured for each of several different distances, so that monomers are identified when compared to a reference physical quantity of a known monomer, which may be obtained from a current measured with a similar inter-electrode distance(s) at which each of plural kinds of monomers are identifiable and ordered with predetermined accuracy and based on a detected physical quantity obtained from a tunneling current, which may be further normalized by the use of one or more reference substances.

Operation procedures of a compound processing device of micro-nano electric spark machine and tunneling current scanning are: a computer 23 controls a power switch 8 to choose the micro-nano electric spark machine power supply 1 and processes of nano to hypo-nano for a workpiece 13 is performed, and then a switcher of power supply 8 chooses processing power supply 2 for the tunneling current scanning to make process of nano to hypo-nano performed for the workpiece 13. The whole processing is observed by a microscope system 9 and timely displayed on a screen of the computer 23 by CCD imaging system 10. During processing, position control data of the workpiece 13 is transferred to a coarse adjustment station of workpiece15 and a precise adjustment station of workpiece 14 by a motion servo of workpiece control of the computer 13 and a position feedback system 24. And position control for a probe 12 in the processing is performed by the computer 23 via D/A connector 6, a control circuit of piezoelectric ceramics 6, a fine adjustment controller for electrode position 7 and a fine adjustment mechanism of tri-electrode 11.

This disclosure proposed one kind of one-time programming and repeatably random read integrated circuit memory. The storage device of this memory programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.

The invention discloses a micronano metal fiber surface topography measuring device, a use method thereof and a movement distance measuring method of a drive in the device. A substrate is arranged on a base through a rail. A chute is arranged in the middle of the base. A template is placed in the chute. A visual window is arranged at the center of the base. One end of a cross beam is connected with the base. One end of a side beam is connected with a support leg, and the drive is arranged on the other end. One end of an electrode is arranged on the side beam. The other end points to the surface of the template through the visual window. The distance from one end, which points to the template, of the electrode to the surface of the template is 0.01 to 100nm. According to the invention, a produced tunnel current effect is used to scan the surface of a measured object, and the three-dimensional shape of the surface of the measured object is acquired through difference in current magnitude.

In the present invention, for each of a plurality of pulses of tunneling current arising when a polynucleotide passes between an electrode pair, the greatest current value and the pulse continuation time are measured, and on the basis of the greatest current value and pulse continuation time, the base sequence of the polynucleotide is determined.

The invention discloses a semiconductor device, and relates to the field of semiconductor optoelectronic devices. The semiconductor device disclosed by the invention comprises a first conductive typesemiconductor layer; an insertion layer arranged on the first conductive type semiconductor layer, wherein the insertion layer is silicon-tellurium co-doped indium gallium arsenic; a second conductivity type semiconductor layer disposed on the insertion layer. The first conductivity type and the second conductivity type are different conductivity types. The semiconductor device disclosed by the invention can realize relatively high tunneling peak current and can meet relatively high tunneling current requirements.

The invention provides a solar cell and a cell module, and relates to the field of photovoltaic technology. The solar cell comprises a PN junction, the PN junction is formed by a base body layer and an inversion layer, the inversion layer is provided with a first heavily doped region, and the first heavily doped region extends into the inversion layer from the side, away from the base body layer, of the inversion layer; the thickness difference between the inversion layer and the first heavily doped region is 1-100 nm in the direction away from the substrate layer; and at room temperature Tm, the first heavily doped region forms a weak degenerate or degenerate semiconductor, the rest part of the inversion layer and the matrix layer are non-degenerate semiconductors, and the weak degenerate or degenerate semiconductor is set as follows: the energy level difference between the Fermi energy level and the conduction band bottom of the n-type semiconductor or the conduction band top of the p-type semiconductor is less than 2kB * Tm. Under the condition that reverse voltage is applied, the PN junction can serve as a tunnel junction, tunnel current is formed in the PN junction, reverse conduction is achieved, and a battery string does not need to be connected with a bypass diode in parallel; when abnormity occurs, normal current is allowed to pass through the rest of the solar cells in the cell string, current loss is low, and heat is little.