20results about How to "Improve gate control ability" patented technology

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The utility model belongs to the field of semiconductor power device manufacturing, and particularly relates to a GaN HEMT device with a back barrier structure with gradually changed components, which comprises a SiC substrate layer, a GaN buffer layer connected above the SiC substrate layer, a first AlGaN back barrier layer connected above the GaN buffer layer, and a GaN channel layer connected above the first AlGaN back barrier layer. According to the GaN-based HEMT device, the back barrier layer with gradually-changed components is introduced, so that the electron constraint in a channel is effectively enhanced, the short-channel effect of the device is inhibited, the direct-current characteristic of the device is improved, and the power characteristic of the GaN-based HEMT device is further improved. For the interface scattering problem caused by the back barrier structure, the gradient component back barrier structure can reduce interface scattering and parasitic parameters compared with a fixed component back barrier structure, the influence on a GaN main channel is reduced, and the small signal and large signal characteristics of the device are improved.

The utility model discloses an array substrate and a display panel, the array substrate comprises a substrate and a thin film transistor, the thin film transistor is arranged on one surface of the substrate, the thin film transistor comprises a semiconductor layer, a crystallized inorganic layer and a gate insulation layer, the semiconductor layer is arranged on one surface of the substrate, and the crystallized inorganic layer is arranged on the other surface of the substrate. The crystallized inorganic layer is disposed on a surface of the semiconductor layer away from the substrate. The gate insulating layer is disposed on a surface of the crystallized inorganic layer away from the substrate. The stability of the TFT device can be improved.

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

According to the field effect transistor based on component and gate voltage combined regulation and control and the preparation method thereof, a silicon dioxide layer is arranged on an intrinsic low-resistance silicon substrate, a source metal electrode and a drain metal electrode are arranged on the silicon dioxide layer, the source metal electrode and the drain metal electrode are metal composite electrodes and comprise a chromium electrode and a gold electrode, the bottom layer filled with channels of the source electrode and the drain electrode is a bismuth-selenium-oxygen nanosheet, and the bottom layer filled with the bismuth-selenium-oxygen nanosheet is a bismuth-selenium-oxygen nanosheet. A black arsenic-phosphorus nanosheet and a top gate bismuth-selenium-oxygen nanosheet dielectric layer are arranged on the bismuth-selenium-oxygen nanosheet, and the source electrode, the drain electrode and the gate electrode are connected with corresponding lead electrodes and are used for being connected with an external test circuit. According to the field effect transistor based on combined regulation and control of the components and the gate voltage and the preparation method of the field effect transistor, through packaging of the bismuth-selenium-oxygen nanosheets, the components of black arsenic and phosphorus and the gate voltage of the top gate are adjusted, so that the photoelectric performance of the device in the visible light, near-infrared and medium-wave infrared ranges is optimized.

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the substrate comprises a plurality of active columns arranged in an array, each active column comprises a channel region, and the side wall of each channel region is provided with a grid accommodating groove; a plurality of gates; the grid electrode wraps the channel region corresponding to the active column, and the grid electrode at least fills the grid electrode accommodating groove. The semiconductor structure has relatively good grid control capability and relatively high switch ratio, and is beneficial to improving the electrical performance of a semiconductor device.

The present invention discloses an enhanced HEMT device and a preparation method thereof, comprising a SiC substrate, an AlN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer with a gradient Al component, an AlGaN barrier layer with a gradient Al component doped with Mg, a SiC substrate, an AlN buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer with a gradient Al component, and a SiC substrate. X The invention adopts an AlGaN barrier layer with a gradient Al component to replace the AlGaN barrier layer, thereby reducing the difficulty of Mg diffusion, avoiding mechanical damage caused by etching of the traditional P-type gate, and improving the gate control capability of the device, which is conducive to realizing a GaN enhanced power device with a high threshold voltage.

The present invention provides a p-GaN HEMT device and a preparation method, a substrate layer; a buffer layer arranged on the substrate layer, a side of the buffer layer away from the substrate layer is provided with a P-type doping region; a channel layer arranged on the buffer layer, the channel layer is in contact with the P-type doping region; a barrier layer, a source electrode and a drain electrode arranged on the channel layer, the source electrode and the drain electrode are arranged on both sides of the barrier layer; a heat dissipation layer arranged on the barrier layer; a cap layer arranged on the barrier layer and on the heat dissipation layer; a passivation layer arranged on the heat dissipation layer, the passivation layer is arranged between the source electrode and the cap layer and between the drain electrode and the cap layer; a gate electrode arranged on the cap layer. The beneficial effects of the present invention are that the number of defects and the interface thermal resistance at the heterojunction interface can be effectively reduced, the heat dissipation capacity of 2DEG at the device channel can be improved, and the mechanical properties of the device can be enhanced, the influence of interface reaction and defects on the working performance of the device can be reduced, the electric field at the 2DEG channel can be effectively modulated, the thermal management capability of the device itself can be improved, and the stability and reliability of the device operation can be improved.

The invention discloses a heterojunction HEMT (High Electron Mobility Transistor) device based on an AlN buffer layer on an AlN substrate and a preparation method, and mainly solves the problems of high dislocation density, large electric leakage, poor heat conductivity, serious current collapse and low channel two-dimensional electron gas concentration of the buffer layer of the existing similar device. The device comprises a substrate, a buffer layer, a channel layer, a barrier layer and a cap layer from bottom to top, a drain electrode and a source electrode are arranged on the two sides of the cap layer, a gate electrode is arranged in the middle of the cap layer, a passivation layer covers the top of the device, and the substrate is an AlN single crystal substrate; the buffer layer adopts an AlN thin film with the thickness of 60 nm to 400 nm; the barrier layer is one or a combination of more of AlGaN, InAlN, AlN, AlScN and Si doped AlGaN; and the passivation layer is one or a combination of more of air, SiO2, Al2O3 and SiNx. The high-power microwave radio frequency device has the advantages of low on resistance, high reverse voltage resistance, high output power, small grid electric leakage and higher grid control capability, and can be used as a high-power microwave radio frequency device.

This invention discloses a method for manufacturing a semiconductor device, relating to the field of semiconductor technology, for simultaneously improving the carrier mobility of NMOS and PMOS transistors, both of which have a gate-around-the-loop (GOP) transistor structure. The manufacturing method includes: forming a first GOP transistor on a first well region of a substrate, and forming a second GOP transistor on a second well region of the substrate. The crystal orientation of a first channel region of the first GOP transistor is perpendicular to the crystal orientation of a second channel region of the second GOP transistor. Forming the first GOP transistor on the first well region includes: forming a first stacked structure on the first well region. The first stacked structure includes a pre-formed layer and alternating first and second material layers formed on the pre-formed layer. The second material layer is the topmost layer in the first stacked structure. Each first material layer is laterally thinned so that the width of the remaining portion of each first material layer is equal to the width of the first channel region.

The application provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method of the semiconductor device comprises the following steps: manufacturing a plurality of bit lines, the plurality of bit lines are sequentially distributed along a second direction; manufacturing a first dielectric layer covering the plurality of bit lines; sequentially manufacturing a sacrificial layer and a second dielectric layer covering the first dielectric layer; forming a plurality of first through holes penetrating through the second dielectric layer, the sacrificial layer and the first dielectric layer and being arrayed and distributed; the bottom of the first through hole is exposed to the bit line; removing part of the second dielectric layer and part of the first dielectric layer arranged around the periphery of the first through hole to form a first channel; manufacturing a plurality of semiconductor columns; the semiconductor columns correspond to fill the first through hole and the first channel arranged around the periphery of the first through hole; replacing the sacrificial layer with a plurality of gate insulating layers and a plurality of gates arranged around the periphery of the plurality of semiconductor columns to obtain a plurality of transistors. The application realizes the improvement of the gate control area and the gate control ability, effectively increases the on-state current, and improves the on-off ratio of the device.

The utility model provides a composite trench gate silicon carbide VDMOS capable of improving gate reliability, which is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate, a well region is arranged on the drift layer, a p-type source region and an N-type source region are arranged in the well region, and the side surface of the P-type source region is connected with the side surface of the N-type source region; a groove is formed in the drift layer; the high-K gate dielectric layer is arranged in the groove, and the groove is formed in the high-K gate dielectric layer; the first gate dielectric layer is arranged in the groove, the first gate dielectric layer is located above the high-K gate dielectric layer, a through hole is formed in the first gate dielectric layer, and the through hole is connected with the groove; the gate metal layer is arranged in the through hole and the groove; the source metal layer is connected to the N-type source region and the P-type source region; the drain electrode metal layer is connected to the lower side face of the silicon carbide substrate, electric field concentration at the corner of the bottom of the grid electrode has higher tolerance, and therefore the reliability of the grid electrode is improved.

The invention discloses a gallium nitride planar micro-nano vacuum triode based on a trapezoidal gate structure. The triode comprises an anode, a cathode, a first grid electrode, a second grid electrode, an insulating layer and a base, the insulating layer is arranged on the upper surface of the base; the anode, the cathode, the first grid electrode and the second grid electrode are arranged on the upper surface of the insulating layer; the anode and the cathode are arranged on the same straight line of the insulating layer, and the first grid electrode and the second grid electrode are symmetrically arranged relative to the straight line; a gap is formed between the first grid electrode and the second grid electrode, and one end of the cathode extends into the gap. The triode improves the shielding of the grid electrode to the anode electric field, and has high grid control capability and low grid electrode leakage current.

The invention provides a semiconductor device and a manufacturing method thereof and a memory system, and the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a first transistor which comprises a first semiconductor layer and a first grid electrode; wherein the first semiconductor layer comprises a first source electrode and a first drain electrode, the first grid electrode surrounds the first drain electrode, and the first source electrode surrounds the first grid electrode. According to the semiconductor device, the manufacturing method thereof and the memory system provided by the invention, the grid control capability of the transistor can be improved.

The invention discloses a cell structure of an MOSFET device and a preparation method of the cell structure. The cell structure comprises a substrate; the first epitaxial layer is provided with a first surface on one side away from the substrate, and the first epitaxial layer is provided with a first doping type; the first doped region is located in the first epitaxial layer, the first doped region is formed by ion implantation from the first surface to the substrate direction, the first surface is provided with a plurality of interval regions where the first doped region is not formed, and the first doped region is located between any two adjacent interval regions; the second epitaxial layer is located on the first surface, the second epitaxial layer at least covers part of the first doped region, the doping concentration of the second epitaxial layer is lower than that of the first doped region, and the first doped region or the second epitaxial layer is provided with a plurality of protruding parts. The doping configuration below the channel and the width of the channel are optimized, and the forward conduction characteristic of the MOS device is improved.

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the following steps: forming an active structure; forming a first pseudo gate structure of the first transistor based on the first active structure; reversing the wafer and thinning the substrate; forming a second pseudo gate structure of the second transistor based on the second active structure; etching a second interlayer dielectric layer with a preset height in a second source-drain region of the second transistor to form a first groove; depositing a first mask material in the first groove to form a first hard mask; exposing a first active structure in a first gate region of the first transistor and a second active structure in a second gate region of the second transistor; forming a first gate dielectric layer of the first transistor and a second gate dielectric layer of the second transistor; forming a second gate structure and a second metal interconnection layer of a second transistor; reversing and exposing the first active structure; and forming a first gate structure and a first metal interconnection layer of the first transistor.

The application provides a power semiconductor device, for example comprising: a substrate, a first-conductivity-type epitaxial layer, a plurality of second-conductivity-type well regions, a plurality of first-conductivity-type doped regions, and a gate. The first-conductivity-type epitaxial layer is configured with a trench, and the trench is recessed in a top surface of the first-conductivity-type epitaxial layer away from the substrate along a first direction, and the opening size of the trench presents a decreasing trend from the top surface along the first direction; the plurality of second-conductivity-type well regions are arranged in the first-conductivity-type epitaxial layer and extend from the top surface towards the substrate, and the trench is located between two adjacent second-conductivity-type well regions, and each second-conductivity-type well region has a spacing portion exposed to the trench; each first-conductivity-type doped region is arranged in a corresponding one of the second-conductivity-type well regions and is located on one side of the corresponding second-conductivity-type well region and is spaced apart from the trench by the spacing portion. In this way, the influence of the JFET region on the on-resistance can be reduced or even eliminated, so as to improve the device performance.

The embodiment of the invention provides a memory device, a memory system and a manufacturing method of the memory device. The memory device includes a first electrode layer; the first stacking structure is located on one side of the first electrode layer and comprises first dielectric layers and plate line layers which are alternately arranged; the storage column penetrates through the first stacking structure and the first electrode layer and protrudes out of the first electrode layer, and the storage column comprises a storage function layer and an inner electrode which are sequentially arranged from outside to inside; the first channel layer covers the part, protruding out of the first electrode layer, of the storage function layer and the first electrode layer; and the second electrode is positioned on one side, far away from the first electrode layer, of the first channel layer and is electrically connected with the first channel layer.

This invention provides a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation, comprising a substrate, a buffer layer, and a multilayer heterostructure of at least two alternating layers of barrier and channel layers. Source and drain electrodes are located on either side of the barrier layer and extend into the buffer layer. A passivation layer is formed on the upper surface of the barrier layer. A gate trench is formed in the middle region of the passivation layer, extending through the passivation layer to the upper surface of the barrier layer. The gate electrode includes multiple discrete gate pillars and a gate cap. The multiple discrete gate pillars are periodically arranged along the gate width direction, located within the gate trench, and extend through at least two alternating layers of barrier and channel layers into the buffer layer. The gate cap is located on the upper surface of the multiple discrete gate pillars, supported by the pillars, and has no contact with the passivation and barrier layers. A metal interconnect layer is electrically connected to the source and drain electrodes. This design achieves both low subthreshold swing and meets the application requirements of low power consumption and high linearity.

The invention discloses a monolithic integrated GaN cascode structure based on a thin film transistor technology and a preparation method, and relates to the technical field of semiconductor devices. The GaN cascode structure comprises a thin film transistor (TFT) and a gallium nitride transistor (GaN HEMT) which are integrated in a monolithic heterogeneous mode, a drain electrode of the TFT is electrically connected with a source electrode of the GaN HEMT, and the source electrode of the TFT is electrically connected with a grid electrode of the GaN HEMT. The TFT and GaN HEMT monolithic heterogeneous integration is adopted, the TFT serves as a normally-closed device in a Cascode structure, the technological process of the TFT can be compatible with a back-end manufacturing process, and the TFT and the GaN HEMT can be normally integrated at low temperature (lt; production is completed in equipment in the back-end process of the GaN-enhanced Cascode structure, the integration level is high, interconnection parasitic parameters are greatly reduced, the switching frequency of the GaN-enhanced Cascode structure can be remarkably improved, and the static power consumption of the switch can be reduced.