13 results about "BiCMOS" patented technology

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The invention relates to an on-chip fully-integrated terahertz signal spread spectrum device based on a SiGe BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) process. The on-chip fully-integrated terahertz signal spread spectrum device comprises a filtering frequency doubler, a single-ended differential Balun, a differential filtering frequency tripler, a differential driving amplifier, a differential power divider, a differential power amplifier, a differential filtering frequency doubler, a terahertz power combiner and a transmission line waveguide converter. Radio frequency input of 9.16 GHz-13.75 GHz is externally provided, the radio frequency input is converted into a differential signal through the single-ended differential Balun after being subjected to frequency doubling twice through the two filtering frequency doublers, the differential signal is subjected to frequency doubling triple through the differential filtering frequency tripler, the single-path differential signal obtains gain through the differential driving amplifier, the single-path differential signal is converted into two-path signals through the differential power divider, and the two-path signals are transmitted to the output end of the output end of the output end of the output end of the output end of the output end of the output end of the output end of the output end. Differential power amplification and differential filtering frequency doubling are respectively carried out, and then the signals are combined into one path by a terahertz power combiner, so that a terahertz signal of 220GHz-330GHz is obtained.

The application discloses a microwave wideband differential variable gain amplifier and relates to the technical field of electronic circuits.The amplifier comprises a differential structure variable gain amplification circuit, an additional phase shift phase offset numerical control bias circuit and a power consumption control bias circuit.The application is applicable to BiCMOS and other processes, the differential variable gain amplification circuit adopts a current steering type Cascode amplifier structure to realize gain adjustment, two control voltages which make the phase change trends opposite when the VGA gain is reduced (increased) are designed, and a phase compensation resistor is designed to realize the low additional phase shift characteristic of the VGA.The two control voltages are generated by the additional phase shift phase offset numerical control bias circuit, and a plurality of digital control bits are set to select a target gain state from the two control voltages to reduce the gain error of the VGA.

A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and / or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

The invention discloses an anti-radiation integrated device based on a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process platform, an anti-radiation structure and a preparation method. The device comprises a low-voltage MOS (Metal Oxide Semiconductor) device, a low-voltage BJT (Bipolar Junction Transistor) device, a resistor and an MOS capacitor which are integrated on a substrate of one type, high-dielectric-constant dielectric regions are arranged in interlayer dielectric layers of the low-voltage MOS device, the low-voltage BJT device, the resistor and the MOS capacitor respectively, and the high-dielectric-constant dielectric regions and the interlayer dielectric layers below the high-dielectric-constant dielectric regions form a stacked structure. And a metal copper buried layer is arranged on the upper surface of each high-dielectric-constant medium region, and the high-dielectric-constant medium regions and the metal copper buried layers form a laminated structure. The preparation method comprises the following steps: growing an epitaxial layer on a substrate, forming a well region through ion implantation, forming a buried oxide layer through high-energy oxygen ion implantation, forming a doped region through ion implantation, growing a gate oxide medium through wet oxidation after high-temperature annealing, sequentially depositing a high-dielectric-constant material, a copper buried layer and aluminum, and respectively etching. And depositing an oxide to form an interlayer medium, etching a through hole, finally depositing aluminum, and etching to form a metal electrode.

The application discloses a kind of for silicon-based optical receiver chip integrated photodiode response current monitoring circuit, belong to optical communication integrated circuit technical field, it includes transimpedance current detection unit, AGC current detection unit and current summation and output unit.The architecture is matched by voltage clamping and proportional device, respectively replicates transimpedance branch and AGC branch current, and is summed according to uniform proportion, and the monitoring current of linear relationship with original light response current is output.The application does not interfere with main signal path, does not introduce front-end noise, is suitable for CMOS / BiCMOS etc.standard process, and high-precision monitoring and receiver sensitivity are considered.

This invention relates to the field of wireless communication technology, specifically to a dynamic bias circuit for improving the DEVM (Digital Source Bipolar Transmission). Utilizing the high density of BiCMOS, a reference voltage VREF that varies with the junction temperature of the high-voltage transformer (HBT) is provided to the output stage dynamic bias circuit. When the amplifier operates in long data packet transmission mode, the HBT junction temperature increases, and the amplifier's power gain begins to decrease. The voltage source bias circuit PTAT detects the temperature rise, and the reference voltage VREF increases to compensate for the gain decrease. The gain remains stable throughout the long data packet transmission, thereby optimizing the DEVM's performance.

This invention discloses a low-dielectric-absorption, low-mismatch precision linear MIM capacitor and its integration technology. The integration steps are as follows: 1) Forming an active region and an isolation field oxide region. 2) Forming a thick gate oxide layer and a thin gate oxide layer. 3) Depositing a polysilicon layer and constructing the polysilicon gate of the MOSFET. 4) Completing photolithographic implantation of the multi-mode gate oxide high and low voltage BiCMOS / CMOS source and drain electrodes. 5) Chemical mechanical planarization to improve the flatness of the surface region under the metal thin film resistor. 6) High resistivity microcrystalline titanium thin film sputtering of the lower electrode of the metal MIM capacitor using PVD method. 7) PECVD silicon nitride Si for the dielectric layer of the metal MIM capacitor. x N y H z 8) Sputtering of high resistivity microcrystalline titanium thin film on the top electrode of the metal MIM capacitor using PVD method. 9) Sputtering of aluminum-copper film layer and completion of metal interconnect etching. This invention not only optimizes the precision matching problem of metal MIM capacitors, but also improves the packaging functional density and device density of integrated circuits, promoting the miniaturization and lightweighting of high-performance integrated circuits.

The invention relates to the technical field of wireless communication, in particular to a dynamic biasing circuit for improving DEVM. And a reference voltage VREF which changes along with the junction temperature of the HBT is provided for the output-stage dynamic biasing circuit by utilizing the high set degree of the BiCMOS. When the amplifier works in a long data packet transmission mode, the junction temperature of the HBT is increased, the power gain of the amplifier starts to drop, the voltage source bias circuit PTAT detects that the temperature is increased, the reference voltage VREF is increased, and the drop of the gain is compensated. And the gain is kept stable in the whole long data packet transmission period, so that the DEVM performance is optimized.

The invention discloses an integrated photodiode response current monitoring circuit for a silicon-based optical receiver chip, which belongs to the technical field of optical communication integrated circuits and comprises a transimpedance current detection unit, an AGC (Automatic Gain Control) current detection unit and a current summation and output unit. The architecture is matched with a proportional device through a voltage clamp, copies a transimpedance branch current and an AGC branch current respectively, sums the transimpedance branch current and the AGC branch current according to a uniform proportion, and outputs a monitoring current which is in a linear relation with an original light response current. The method does not interfere with a main signal channel, does not introduce front-end noise, is suitable for standard processes such as CMOS (Complementary Metal Oxide Semiconductor) / BiCMOS (Bipolar Complementary Metal Oxide Semiconductor), and gives consideration to high-precision monitoring and receiver sensitivity.

The invention relates to a MOS, BiCMOS or CMOS-based analog circuit (1). The analog circuit (1) is designed to implement a predetermined circuit function in a normal state of the analog circuit (1). The analog circuit (1) has an analog input or output signal, or has an analog signal inside the analog circuit (1). The analog circuit (1) is connected to test logic (38). The test logic (38) is designed to bring the analog circuit (1) into the normal state and into at least a first test state. The analog circuit (1) comprises a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which is designed to perform a function of the analog circuit (1) in accordance with the predetermined circuit function during normal operation. According to the invention, the analog circuit (1) further comprises a second component (S1 to S9; G1 to G9) which is designed to enable the test logic (38) to set a switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in at least the first test state of the analog circuit (1).

The invention discloses a linear wide tuning voltage range LC oscillator with temperature compensation, which belongs to the field of integrated circuits and comprises PMOS (P-channel Metal Oxide Semiconductor) tubes Q1 and Q2, an array capacitor unit, a variable capacitor unit, inductors L1 and L2 and an array resistor unit, and the design of the linear LC oscillator with the temperature compensation variable capacitance for controlling the voltage VCTRL from 0 to 2.5 V can be realized. A tape-out is designed by adopting a BICMOS (Bipolar Complementary Metal Oxide Semiconductor) process, the power supply voltage is 3.3 V, the frequency regulation range is 2.5 GHz-3. 3GHz, the phase noise is-139dBc / Hz at the 2.7 GHz, the variable capacitor adopts a linear voltage interpolation temperature compensation technology, the capacitance value of a variable capacitor unit is controlled to linearly change within the voltage VCTRL 0-2.5 V, and the frequency deviation is less than 0.5 M within the temperature change range of-55 DEG C to 125 DEG C.

The application discloses a BiCMOS integration method based on standard bipolar devices, which comprises the following steps: 1) forming A buried layer regions and a plurality of isolation regions on a substrate; 2) forming a field region; 3) forming a first base region and a second base region; 4) etching a first gate oxide layer by using a mask pattern, and then growing a second gate oxide layer and a third gate oxide layer by oxidation to form thick and thin gate oxides; 5) forming a gate oxide polycrystal of a MOS tube; 6) forming a first emitter region, a first base heavy contact region, a first CMOS source-drain region and a second DMOS source-drain region; 7) forming a second emitter region, a second base heavy contact region, a second CMOS source-drain region and a third DMOS source-drain region; 8) forming a first dielectric layer; 9) etching a CT hole by using a mask; performing metal deposition, etching a metal end by using a mask pattern, and forming BJT, CMOS and DMOS devices. The application realizes complementary bipolar technology without increasing the number of photolithography layers, and enriches the selectable types of devices to meet more extensive and higher demand application technical fields.