50 results about "Thin gate oxide" patented technology

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a high-voltage SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) under-gate anti-radiation reinforcing structure which comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate electrode, the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and a heavily doped N well layer; wherein the diffusion layer comprises a low-doped N body region I and a carrier storage layer; a groove structure is etched in the surface area of the semiconductor epitaxial layer between the adjacent lightly doped P well layers I; a P-type doped region is formed on the inner surface of the groove structure through ion implantation; and a dielectric layer is formed in the inner cavity of the P-type doped region through deposition. A groove structure is introduced into a JFET region of the SiC MOSFET device, P-type impurities are injected into the side wall and the bottom of the groove to form a P-type doped region, the groove is filled with dielectric materials such as SiO2, the groove structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, the electric field intensity in thin gate oxide is greatly reduced, and therefore the single-particle gate penetration resistance of the SiC MOSFET device is improved.

The invention discloses a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integration method based on a standard bipolar device. The method comprises the following steps of: 1) forming A buried layer regions and a plurality of isolation regions on a substrate; and 2) forming a field region. And 3) forming a first base region and a second base region. And 4) etching the first gate oxide layer by using the mask pattern, and oxidizing and growing a second gate oxide layer and a third gate oxide layer again to form thick and thin gate oxides. And 5) forming gate oxide polycrystal of the MOS tube. And 6) forming a first emitter region, a first base electrode heavy contact region, a first CMOS source-drain region and a second DMOS source-drain region. And 7) forming a second emitter region, a second base electrode heavy contact, a second CMOS source-drain region and a third DMOS source-drain region. And 8) forming a first dielectric layer. And 9) etching the CT hole by using the mask. And carrying out metal deposition, and etching a metal end by using the mask pattern to form BJT, CMOS and DMOS devices. Under the condition that a photoetching layer is not added, the complementary bipolar process is realized, the selectable types of devices are enriched, and the application technical field with wider and higher requirements is met.

The invention relates to a low-power-consumption high-voltage switching circuit suitable for a thin gate oxide process, which belongs to the field of high-voltage domain analog integrated circuits and comprises a charge pump, a delay self-locking switch and a high-voltage switch. The charge pump, the delay self-locking switch and the high-voltage switch are connected in sequence; the charge pump is used for sampling the source end voltage of the high-voltage switch and generating a corresponding boost control signal; the delay self-locking switch is used for outputting a grid end control signal according to the boost control signal so as to control on and off of the high-voltage switch; the delay self-locking switch is provided with a short-circuit switch module; and the short-circuit switch module is used for short-circuiting the gate end and the source end of the high-voltage switch to turn off the high-voltage switch and discharging after the high-voltage switch is turned off. When the high-voltage switch is turned off, the gate end and the source end of the high-voltage switch are quickly short-circuited through the short-circuit switch module arranged in the delay self-locking switch, and then slow discharging is performed, so that the problem of voltage resistance of a pure charge pump structure in the high-voltage switch turn-off action is solved, and quick turn-off of the high-voltage switch is realized.

The invention discloses a preparation method of an ultralow gate charge shield gate MOSFET device and the device, and the method comprises the steps: depositing a layer of oxide on the surface of a wafer to be etched, then covering photoresist, and etching the oxide to the surface of the wafer; etching the oxide on the surface of the wafer, and growing an oxide layer in the groove and on the surface of the wafer to obtain an oxide film serving as an isolation layer; depositing an oxide with a first thickness in the groove and on the surface of the groove, and grinding the oxide to a position with a second thickness from the surface of the wafer; growing a layer of oxide on the top of the polycrystalline silicon through a thermal oxidation process again, so that the thickness of the oxide between the polycrystalline silicon on the top reaches a first target thickness; and etching all the silicon nitride and the oxide on the side wall of the groove, and then growing the gate oxide until the thickness of the gate oxide reaches a second target thickness. According to the invention, thick inter-polycrystalline silicon oxide and a thinner gate oxide layer can be obtained, the dynamic parameters of the device are reduced, and the cost is reduced.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device for improving single-particle radiation recombination efficiency, which comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode, and is characterized in that an isolation medium is deposited on the outer surface of the grid electrode; the semiconductor epitaxial layer comprises a substrate layer, an epitaxial layer, a P well layer and a heavily doped N well layer; the P well layer comprises a lightly doped P well layer and a heavily doped P well layer; p-type doped regions are formed between the adjacent lightly doped P well layers through ion implantation, and N-type impurity ions are injected into the P-type doped regions to form N-type polycrystalline silicon. According to the invention, the P-type doped region is formed by injecting P-type impurities in the SiC MOSFET device, the N-type polycrystalline silicon is formed by ion injection in the P-type doped region, and the N-type polycrystalline silicon is in short circuit with the source metal, so that the trench structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, the electric field intensity in the thin gate oxide is greatly reduced, and the single-particle gate penetration resistance of the SiC MOSFET device is improved.

The invention relates to a method for preparing a low dark current silicon drift detector based on a double-sided temporary bonding process, which comprises the following steps of: after a front surface process of an SDD wafer is finished, carrying out temporary bonding on the front surface of the SDD wafer by adopting a temporary bonding adhesive and a temporary bonding glass slide; thinning and polishing the back surface of the SDD wafer after the temporary bonding is completed, and carrying out a CMP (Chemical Mechanical Polishing) process on the back surface of the SDD wafer after the thinning and polishing to eliminate a damaged layer and reduce the dark current of a device; then, process manufacturing is carried out on the back face of the SDD wafer, after manufacturing is completed, the glass sheet and the SDD wafer are stripped off through a laser debonding process, and the front face of the wafer is exposed; when the active region of the SDD wafer is manufactured, a thin gate oxide layer is adopted for doping for shielding injection, the shielding oxide layer is removed after injection is completed, furnace tube oxidation and annealing are carried out, and the dark current of a device is reduced; when the oxide layer of the SDD contact hole is removed, a manufacturing process combining dry etching and wet etching is adopted, so that damage to a silicon substrate is avoided, and dark current of a device is reduced.

The invention discloses a trench gate SiC MOSFET chip and a manufacturing method thereof.The trench gate SiC MOSFET chip uses a composite trench gate structure, the thicknesses of gate oxide layers at the bottom and the side wall of a trench can be controlled respectively, the gate oxide layer at the bottom of the trench at the position where the electric field intensity is large is thickened, and therefore the long-term reliability of a device in the using process is improved, and the reliability of the device is improved. And a thin gate oxide layer is reserved on the side wall groove part, so that the channel resistance and the conduction loss of the device can be reduced. Therefore, the channel resistance and the conduction loss can be effectively reduced while the high reliability of the device is ensured.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The utility model provides a double-gate oxide MOS (Metal Oxide Semiconductor) structure, which comprises a substrate, a high-voltage well region and a low-voltage well region, the low-voltage well region comprises a thin gate oxide layer and a low-voltage side gate which are located on the surface of the low-voltage well region, and low-voltage side source / drain regions which are located in the low-voltage well region and located on the two sides of the low-voltage side gate, and the high-voltage well region comprises a high-voltage side gate oxide layer and a high-voltage side gate which are located on the surface, a drift region located in the high-voltage well region, and high-voltage side source / drain regions located on the two sides of the high-voltage side gate oxide layer; the high-voltage side gate oxide layer comprises a thick gate oxide layer and a first field oxide layer which are arranged in an overlapped mode in the gate length direction and only covers the high-voltage side gate instead of covering the whole high-voltage well region, so that a thick film layer exists in a region corresponding to the high-voltage side gate in the follow-up manufacturing process of the polycrystalline silicon gate, and when the polycrystalline silicon layer is etched to form the two gates, the high-voltage side gate oxide layer is formed. The residual film difference of other regions is small, so that LDD injection and the injection dose and depth of the source / drain region can be accurately controlled, and the electrical performance and reliability of the double-gate oxide MOS structure are further improved.

The application provides a manufacturing method of a semiconductor device, before an active region manufacturing process, a substrate region to be manufactured into a high-voltage transistor is subjected to groove etching to form at least a gate oxide groove and a first depth adjusting groove and define an active region horn, the depth of the first depth adjusting groove is used to increase the bottom depth of a shallow trench isolation structure for isolating a source / drain region and a channel region of the high-voltage transistor, the breakdown voltage of the high-voltage transistor is increased, and by ion implantation and oxidation on the active region horn, a relatively thick first gate oxide layer is formed, the problem of the thin gate oxide layer of the high-voltage transistor at the top corner of the active region is solved, the leakage at the top corner of the active region is reduced, the hot carrier effect and the gate-induced drain leakage are reduced, and the first gate oxide layer can also be used as a barrier layer to block the lateral diffusion of oxygen in the process of forming a second gate oxide layer, thereby improving the beak effect on the source / drain region of the high-voltage transistor.

The application relates to the technical field of semiconductor power devices, and discloses a SiC MOSFET structure with a low input capacitance and a STI structure and a manufacturing method thereof. The structure comprises a silicon carbide substrate, an N-type drift layer, a P well, and a heavily doped N region and a P region. A shallow groove is embedded in the surface of a JFET region between adjacent P wells, and a silicon dioxide layer is filled in the shallow groove to form a STI structure. The upper surface of the structure is flush with the upper surface of the unetched drift layer. The sidewall and the bottom of the shallow groove are covered with an N-type charge compensation layer with a higher doping concentration. A thin gate oxide layer covers the surface of the P well and the STI structure, and a gate electrode is arranged on the thin gate oxide layer. The application increases the insulating physical distance between the gate and the epitaxial layer by introducing the STI structure, reduces the parasitic capacitance and the high-frequency switching loss, compensates for the problem of the rise of the conduction resistance caused by the narrowing of the channel by using the N-type charge compensation layer, eliminates the physical step through surface planarization treatment, and improves the blocking withstand voltage level of the device.

The invention discloses an ultra-thin gate oxide breakdown resistance test method under ESD stress, and the method comprises the steps: applying voltage to a gate electrode and a drain electrode of a to-be-tested semiconductor device, and carrying out the measurement to obtain a transfer characteristic curve of the to-be-tested device; applying an electrostatic pulse of which the amplitude increases progressively to the grid of the to-be-tested device, performing a TLP test, obtaining a grid stress voltage and a leakage current of the to-be-tested device under TLP stress, performing the TLP test circularly until the leakage current changes by more than three orders of magnitude, and regarding that a gate oxide layer of the to-be-tested device is broken down; and according to a channel carrier number fluctuation model and drain current noise, calculating the defect density of the gate oxide layer of the to-be-tested device after each round of TLP stress application, and utilizing the stress voltage and the defect density under each round of TLP stress to obtain a fitting curve of the stress voltage and the defect density for predicting the breakdown voltage of the gate oxide layer of the device of the same type. According to the method, the breakdown voltage of the gate oxide layer of the ESD to-be-protected device can be predicted in a large-scale and batch manner.

The invention discloses a band-gap reference circuit with high precision and low temperature coefficient, which can achieve good curvature compensation in a wider temperature range, and the curvature correction is finer, so that the correction precision is greatly improved. And the curvature correction progress is not influenced by the leakage current of the transistor, so that the method can be suitable for the transistor with a thin gate oxide layer with relatively high leakage current.

The application relates to a preparation method of a low-dark-current silicon drift detector based on a double-sided temporary bonding process, wherein after the front surface process of an SDD wafer is completed, the front surface of the SDD wafer is temporarily bonded by using temporary bonding glue and a temporary bonding glass slide; then the back surface of the SDD wafer after the temporary bonding is thinned and polished, the back surface of the SDD wafer after the thinning and polishing is subjected to a CMP process to remove a damage layer and reduce the dark current of the device; then the back surface of the SDD wafer is subjected to process manufacturing, after the manufacturing is completed, the glass slide is peeled off from the SDD wafer by using a laser debonding process, and the front surface of the wafer is exposed; wherein when the active area of the SDD wafer is manufactured, doping is shielded by using a thin gate oxide layer to be injected, the shielding oxide layer is removed after the injection is completed, and the dark current of the device is reduced by performing furnace tube oxidation and annealing; when the SDD contact hole oxide layer is removed, a manufacturing process combining dry etching and wet etching is used to avoid damage to the silicon substrate and reduce the dark current of the device.

The application discloses a high-voltage linear charging circuit based on a thin gate oxide process and with reverse connection protection, which comprises a voltage stabilizing module, a PMOS charging tube, a self-turn-off gate voltage clamping circuit, a voltage conversion current circuit with current limiting, a current detection setting circuit and a charging controller; the output end of the voltage stabilizing module is connected with the input ends of the voltage conversion current circuit with current limiting, the current detection setting circuit and the charging controller; the output end of the current detection setting circuit is connected with the input end of the charging controller; the output end of the charging controller is connected with the input end of the voltage conversion current circuit with current limiting; the output end of the voltage conversion current circuit with current limiting is connected with the input end of the self-turn-off gate voltage clamping circuit; and the output end of the self-turn-off gate voltage clamping circuit is connected with the input end of the PMOS charging tube. The application realizes a linear charging circuit which can bear high-voltage input and output and has battery reverse connection protection on the basis of a thin gate oxide process; and the linear charging circuit has the characteristics of high density and easy integration.

The application provides a semiconductor structure and a preparation method thereof, and a high-voltage MOS device. The semiconductor structure comprises: a substrate; a source-drain region and a channel active region between the source-drain region are formed in the substrate; a field oxide layer is located between the channel active region and the source-drain region and defines a boundary of the channel active region; a gate oxide layer covers the channel active region and the field oxide layer; wherein a recess is formed on the surface of the gate oxide layer at a position corresponding to the adjacent boundary of the channel active region; the thickness of the gate oxide layer at the recess position is smaller than that at other positions; a gate layer is located on the surface of the gate oxide layer; wherein the gate layer forms a through opening at a position corresponding to the recess. In this way, the leakage and breakdown caused by the thinner gate oxide layer at the recess position can be reduced to a certain extent, and the reliability is improved.

The application discloses a linear voltage stabilizing circuit based on NMOS regulating tube, comprising a bias voltage generating circuit, a voltage division feedback circuit, an oscillator circuit, a charge pump circuit and a pre-voltage stabilizing circuit, wherein the bias voltage is generated through the bias voltage generating circuit; the output voltage is divided to obtain a feedback voltage through the voltage division feedback circuit; the feedback voltage is amplified and then input to the oscillator circuit to generate an oscillation signal; the generated oscillation signal is input to the charge pump circuit; the gate voltage of the NMOS regulating tube is adjusted through the charge pump circuit, so as to obtain the output voltage; the pre-voltage stabilizing circuit widens the input voltage range, so that the linear voltage stabilizing circuit can work in a high input voltage environment; the linear voltage stabilizing circuit based on the NMOS regulating tube has the characteristics of wide input range and low voltage difference, fast transient response speed, and is fully compatible with the thin gate oxide process.

The present invention discloses a gate driving circuit, which includes a left circuit and a driving circuit. The left circuit includes a high-voltage power supply VCC, a Q1 triode, a Q2 triode, a d1 diode, a dz1 Zener diode, a dz2 Zener diode, a dz3 Zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1 MOS transistor, an N2 MOS transistor, an N3 MOS transistor, and an N4 MOS transistor. The driving circuit includes an INV1 driver, the INV1 driver is connected to an INV2 driver, the INV2 driver is connected to an HN1 driving transistor, the drain of the HN1 driving transistor is connected to the source of an HP3 driving transistor, the drain of the HP3 driving transistor is connected to the source of an HP1 driving transistor and the gate of an HP2 driving transistor, the source of the HP2 driving transistor is connected to the drain of an HP4 driving transistor, the source of the HP4 driving transistor is connected to the drain of an HN2 driving transistor, the drain of the HP4 driving transistor is connected to the gate of the HP1 driving transistor. The HN1 driving transistor, the HN2 driving transistor, the HP1 driving transistor, the HP2 driving transistor, the HP3 driving transistor, and the HP4 driving transistor form a level shift circuit. This driving circuit can ensure safe operation even in a thin gate oxide process.

The invention provides a semiconductor structure and a preparation method thereof, and a high-voltage MOS device. The semiconductor structure comprises a substrate; a source region, a drain region and a channel active region between the source region and the drain region are formed in the substrate; the field oxide layer is located between the channel active region and the source-drain region and defines the boundary of the channel active region; the gate oxide layer covers the channel active region and the field oxide layer; wherein the surface of the gate oxide layer is provided with a recess at a position corresponding to the junction of the adjacent boundaries of the channel active region; the thickness of the gate oxide layer at the sunken position is smaller than that of the gate oxide layer at other positions; the gate layer is located on the surface of the gate oxide layer; wherein a through hole is formed in a position, corresponding to the recess, of the gate layer. In this way, electric leakage and breakdown caused by the fact that the gate oxide layer at the sunken position is thin can be reduced to a certain extent, and reliability is improved.

The utility model provides a high-low voltage MOS structure comprising a low voltage region provided with a low voltage well region and a high voltage region provided with a high voltage well region. The low-voltage MOS device in the low-voltage region comprises a thin gate oxide layer and a low-voltage side grid electrode which are stacked, and low-voltage side source / drain regions located on the two sides of the low-voltage side grid electrode; the high-voltage MOS device in the high-voltage region comprises a high-voltage side gate oxide layer and a high-voltage side grid electrode which are stacked; the first drift region and the second drift region are located in the high-voltage well region; a high-voltage side source region and a high-voltage side drain region are arranged in the first drift region and the second drift region respectively, and the high-voltage side source region and the high-voltage side drain region are located on two sides of the high-voltage side gate oxide layer respectively; the high-voltage side gate oxide layer comprises a first field oxide layer, a thick gate oxide layer and a second field oxide layer which are sequentially overlapped along the gate length direction, the thickness of the thick gate oxide layer is greater than that of the thin gate oxide layer, and the thicknesses of the first and second field oxide layers are greater than that of the thick gate oxide layer. According to the design of the high-voltage side gate oxide layer, the implantation dose and depth of the source / drain region can be accurately controlled, and the electrical performance and reliability of a product are improved.

The invention discloses a method and a structure for integrating thick and thin gate oxide CMOS (Complementary Metal Oxide Semiconductor) devices in a double polycrystal self-aligned bipolar junction transistor process. The method comprises the following steps of: providing an SOI (Silicon On Insulator) silicon substrate; sequentially forming an N-type primary buried layer (103) of the double polycrystal self-aligned bipolar junction transistor, a P-type primary buried layer (104) of the thin gate oxide NMOS and a P-type secondary buried layer (105) of the thick gate oxide NMOS; forming an epitaxial layer (106) on the SOI silicon substrate; and forming a P-type primary well region (107) of the thin gate oxide NMOS and a P-type secondary well region (108) of the thick gate oxide NMOS in the epitaxial layer. According to the semiconductor device, various combinations of high-performance NPN / PNP and thick and thin gate oxide CMOS devices can be achieved, the overall device characteristics of the process are effectively improved, the application technical field with wider and higher requirements is met, and the electrical performance of a chip is improved.

The invention discloses a shield gate MOSFET structure and a process method, a shield gate dielectric layer at the lower part has a thickness change with a thick lower part and a thin upper part, the shield gate dielectric layer is matched with a shield gate with a wider section to form a field plate structure, and the upper top surface of the shield gate forms an arc protruding upwards; meanwhile, an arc-shaped concave surface is formed at the bottom of the upper grid to half wrap the upper part of the shield grid, the thicker shield grid in the middle section serves as an internal field plate, and the electric field distribution of a drift region is optimized; and the thinner gate oxide layer at the middle section of the shielding gate is enhanced and assisted to deplete, so that a new electric field peak value is formed, the withstand voltage of the device is improved, and meanwhile, higher doping concentration of a drift region is allowed, so that lower on-resistance is obtained. After the bottom of the complete gate polycrystalline silicon is removed, a certain hollow structure is formed, and the parasitic capacitance of the gate is reduced, so that the withstand voltage BVDS of the device is higher, the on resistance Rdson is lower, the RSP is smaller, and the dynamic characteristic is better.

The present invention provides an RC-IGBT device, comprising: an IGBT region is provided with an IGBT device; a diode region is adjacent to the IGBT region, the diode region is provided in a cell, a deep groove is provided in the diode region, a thin gate oxide layer is provided on the sidewall of the deep groove to form an SBR diode, and a thick oxide layer is provided at the bottom of the deep groove. The PN diode in the RC-IGBT provided by the present invention is replaced by an SBR diode, which effectively reduces VF, improves the performance of reverse recovery of the RC-IGBT, and can save the area of ​​the diode, maximizing the area utilization.

The invention provides a super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and the super-junction MOSFET structure comprises a semiconductor substrate, an epitaxial layer, a gate oxide layer, a gate electrode, a matrix region, a source region, a source electrode and a drain electrode. The semiconductor substrate comprises a front face and a back face, and the straight line direction from the front face to the back face is the vertical direction. The epitaxial layer is arranged on the front surface of the semiconductor substrate and comprises first and second conductive columns which vertically extend from the front surface to the back surface and are alternately arranged in the horizontal direction; the gate oxide layer is arranged on the surface of the first conductive column, the gate electrode is arranged on the gate oxide layer, the matrix region is arranged in the upper region of the second conductive column, and at least one source region is formed in the matrix region. The source electrode is formed on the base body region and electrically connected to at least one source region, the source electrode and the gate electrode are insulated and isolated, and the drain electrode is arranged on the back face of the semiconductor substrate. According to the super-junction MOSFET structure, the thick and thin gate oxide region design is adopted, the gate-drain capacitance is reduced, the turn-off delay is shortened, the transition loss is reduced, and the dynamic performance is optimized.

This invention discloses a low-dielectric-absorption, low-mismatch precision linear MIM capacitor and its integration technology. The integration steps are as follows: 1) Forming an active region and an isolation field oxide region. 2) Forming a thick gate oxide layer and a thin gate oxide layer. 3) Depositing a polysilicon layer and constructing the polysilicon gate of the MOSFET. 4) Completing photolithographic implantation of the multi-mode gate oxide high and low voltage BiCMOS / CMOS source and drain electrodes. 5) Chemical mechanical planarization to improve the flatness of the surface region under the metal thin film resistor. 6) High resistivity microcrystalline titanium thin film sputtering of the lower electrode of the metal MIM capacitor using PVD method. 7) PECVD silicon nitride Si for the dielectric layer of the metal MIM capacitor. x N y H z 8) Sputtering of high resistivity microcrystalline titanium thin film on the top electrode of the metal MIM capacitor using PVD method. 9) Sputtering of aluminum-copper film layer and completion of metal interconnect etching. This invention not only optimizes the precision matching problem of metal MIM capacitors, but also improves the packaging functional density and device density of integrated circuits, promoting the miniaturization and lightweighting of high-performance integrated circuits.

The present disclosure provides a kind of detection substrate and flat panel detector, two diodes made by the same manufacturing process of photodiode of detection area are used to build the ESD discharge circuit of periphery, compared with the ESD discharge circuit of traditional transistor built by source-gate shorting, diode forward conduction is more superior than source-gate shorting TFT, it can be opened instantly in positive bias state, the cross-sectional area of current flow is much larger than the cross-sectional area of TFT thin layer channel, the path length of carrier transport is much shorter than the length of TFT channel;Diode reverse cut-off characteristic is more superior than source-gate shorting TFT, leakage current is lower;Since diode does not have the thin gate oxide layer structure of TFT, there is no ESD gate oxide breakdown problem, and the ability to resist large current ablation is much better than TFT.The present disclosure uses diode to build ESD discharge circuit to achieve better static discharge effect, and has stronger ESD breakdown and ablation resistance, which greatly reduces the probability of subsequent laser cutting repair.

The application provides an electrostatic protection device. The electrostatic protection device comprises an N-type epitaxial region, an N-type buffer region and a P-type body region; the N-type buffer region and the P-type body region are respectively embedded on two sides of an upper surface of the N-type epitaxial region, a metal anode arranged on the N-type buffer region is connected with a circuit interface, and a metal cathode is arranged on the N-type epitaxial region and / or the P-type body region; a first N+ region and a first P+ region are embedded on an upper surface of the N-type buffer region, a second P+ region and a second N+ region are embedded on an upper surface between the N-type buffer region and the P-type body region of the N-type epitaxial region, and a third N+ region and a third P+ region are embedded on an upper surface of the P-type body region; a thin gate oxide layer is arranged between the second N+ region and the third N+ region, and the thin gate oxide layer is arranged on a connection between the upper surfaces of the N-type epitaxial region and the P-type body region; a gate electrode is further arranged on the thin gate oxide layer, and the second P+ region, the second N+ region and the gate electrode are electrically connected. The application can reduce the trigger voltage of the electrostatic protection device.

Circuits and methods for high-quality amplifiers (e.g., low-noise amplifiers and power amplifiers) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. Some embodiments include a thin gate oxide N-type MOSFET device or N-type Extended Drain MOSFET (NEDMOS) device co-fabricated with one or more serially-coupled thick gate oxide P-type Extended Drain MOSFET (PEDMOS) devices of several types. Some embodiments include one or more multi-gate NEDMOS devices. Embodiments includes PEDMOS devices having at least source and drain regions that include germanium (e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si and graded Ge and Si mixtures), particularly PEDMOS devices having a strained channel region. A significant benefit of the inventive IC structures and variants is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain / source regions.

The application discloses a dynamic high-voltage signal transmission switch circuit suitable for a thin gate oxide layer process, which comprises a symmetric double NMOS tube switch, a floating power rail generation module and a LevelShift level conversion module; the symmetric double NMOS tube switch comprises two N-type transistors, the gate and the source of the two N-type transistors are connected respectively, and the drain of the two N-type transistors is used as an input end of a high-voltage signal; the floating power rail generation module is connected to the source of the two N-type transistors in the symmetric double NMOS tube switch and is used for generating a floating power rail by tracking the amplitude of the dynamic high-voltage signal; the LevelShift level conversion module is connected to the floating power rail generation module and the gate of the two N-type transistors in the symmetric double NMOS tube switch and is used for converting a digital control signal corresponding to an input low power rail 0V-5V into an analog control signal corresponding to the floating power rail so as to control the conduction and the turn-off of the symmetric double NMOS tube switch. The application ensures that the thin gate oxide layer MOS tube switch is in a safe voltage-withstanding range when transmitting the dynamic high-voltage signal.

The present invention relates to a gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit. The structure comprises a primary drive module, a secondary drive module, and a port drive module. The primary drive module, the secondary drive module, and the port drive module are sequentially connected. The primary drive module is responsible for driving the second PMOS tube P2 on and off; the secondary drive module is used to control the on and off of the built-in power tube P1 in the drive circuit; and the port drive module is used to drive an external power MOS tube. The gate drive circuit structure for increasing the gate voltage of a power MOS tube in a bootstrap circuit of the present invention is used. Under the condition of using a thin gate oxide device, the gate drive voltage is increased to reduce the R of driving the external power MOS tube. DS(ON) , improving the overall working efficiency, this structure can be used to drive different power tubes on the high and low sides at the same time. It can adapt to different working voltages by simply adjusting the value of the internal resistance or current reference, and has broad application prospects.