23 results about "Thin gate oxide" patented technology

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

The application provides a manufacturing method of a semiconductor device, before an active region manufacturing process, a substrate region to be manufactured into a high-voltage transistor is subjected to groove etching to form at least a gate oxide groove and a first depth adjusting groove and define an active region horn, the depth of the first depth adjusting groove is used to increase the bottom depth of a shallow trench isolation structure for isolating a source / drain region and a channel region of the high-voltage transistor, the breakdown voltage of the high-voltage transistor is increased, and by ion implantation and oxidation on the active region horn, a relatively thick first gate oxide layer is formed, the problem of the thin gate oxide layer of the high-voltage transistor at the top corner of the active region is solved, the leakage at the top corner of the active region is reduced, the hot carrier effect and the gate-induced drain leakage are reduced, and the first gate oxide layer can also be used as a barrier layer to block the lateral diffusion of oxygen in the process of forming a second gate oxide layer, thereby improving the beak effect on the source / drain region of the high-voltage transistor.

The application relates to the technical field of semiconductor power devices, and discloses a SiC MOSFET structure with a low input capacitance and a STI structure and a manufacturing method thereof. The structure comprises a silicon carbide substrate, an N-type drift layer, a P well, and a heavily doped N region and a P region. A shallow groove is embedded in the surface of a JFET region between adjacent P wells, and a silicon dioxide layer is filled in the shallow groove to form a STI structure. The upper surface of the structure is flush with the upper surface of the unetched drift layer. The sidewall and the bottom of the shallow groove are covered with an N-type charge compensation layer with a higher doping concentration. A thin gate oxide layer covers the surface of the P well and the STI structure, and a gate electrode is arranged on the thin gate oxide layer. The application increases the insulating physical distance between the gate and the epitaxial layer by introducing the STI structure, reduces the parasitic capacitance and the high-frequency switching loss, compensates for the problem of the rise of the conduction resistance caused by the narrowing of the channel by using the N-type charge compensation layer, eliminates the physical step through surface planarization treatment, and improves the blocking withstand voltage level of the device.

The invention discloses an ultra-thin gate oxide breakdown resistance test method under ESD stress, and the method comprises the steps: applying voltage to a gate electrode and a drain electrode of a to-be-tested semiconductor device, and carrying out the measurement to obtain a transfer characteristic curve of the to-be-tested device; applying an electrostatic pulse of which the amplitude increases progressively to the grid of the to-be-tested device, performing a TLP test, obtaining a grid stress voltage and a leakage current of the to-be-tested device under TLP stress, performing the TLP test circularly until the leakage current changes by more than three orders of magnitude, and regarding that a gate oxide layer of the to-be-tested device is broken down; and according to a channel carrier number fluctuation model and drain current noise, calculating the defect density of the gate oxide layer of the to-be-tested device after each round of TLP stress application, and utilizing the stress voltage and the defect density under each round of TLP stress to obtain a fitting curve of the stress voltage and the defect density for predicting the breakdown voltage of the gate oxide layer of the device of the same type. According to the method, the breakdown voltage of the gate oxide layer of the ESD to-be-protected device can be predicted in a large-scale and batch manner.

The invention discloses a band-gap reference circuit with high precision and low temperature coefficient, which can achieve good curvature compensation in a wider temperature range, and the curvature correction is finer, so that the correction precision is greatly improved. And the curvature correction progress is not influenced by the leakage current of the transistor, so that the method can be suitable for the transistor with a thin gate oxide layer with relatively high leakage current.

The application relates to a preparation method of a low-dark-current silicon drift detector based on a double-sided temporary bonding process, wherein after the front surface process of an SDD wafer is completed, the front surface of the SDD wafer is temporarily bonded by using temporary bonding glue and a temporary bonding glass slide; then the back surface of the SDD wafer after the temporary bonding is thinned and polished, the back surface of the SDD wafer after the thinning and polishing is subjected to a CMP process to remove a damage layer and reduce the dark current of the device; then the back surface of the SDD wafer is subjected to process manufacturing, after the manufacturing is completed, the glass slide is peeled off from the SDD wafer by using a laser debonding process, and the front surface of the wafer is exposed; wherein when the active area of the SDD wafer is manufactured, doping is shielded by using a thin gate oxide layer to be injected, the shielding oxide layer is removed after the injection is completed, and the dark current of the device is reduced by performing furnace tube oxidation and annealing; when the SDD contact hole oxide layer is removed, a manufacturing process combining dry etching and wet etching is used to avoid damage to the silicon substrate and reduce the dark current of the device.

The application discloses a high-voltage linear charging circuit based on a thin gate oxide process and with reverse connection protection, which comprises a voltage stabilizing module, a PMOS charging tube, a self-turn-off gate voltage clamping circuit, a voltage conversion current circuit with current limiting, a current detection setting circuit and a charging controller; the output end of the voltage stabilizing module is connected with the input ends of the voltage conversion current circuit with current limiting, the current detection setting circuit and the charging controller; the output end of the current detection setting circuit is connected with the input end of the charging controller; the output end of the charging controller is connected with the input end of the voltage conversion current circuit with current limiting; the output end of the voltage conversion current circuit with current limiting is connected with the input end of the self-turn-off gate voltage clamping circuit; and the output end of the self-turn-off gate voltage clamping circuit is connected with the input end of the PMOS charging tube. The application realizes a linear charging circuit which can bear high-voltage input and output and has battery reverse connection protection on the basis of a thin gate oxide process; and the linear charging circuit has the characteristics of high density and easy integration.

The application provides a semiconductor structure and a preparation method thereof, and a high-voltage MOS device. The semiconductor structure comprises: a substrate; a source-drain region and a channel active region between the source-drain region are formed in the substrate; a field oxide layer is located between the channel active region and the source-drain region and defines a boundary of the channel active region; a gate oxide layer covers the channel active region and the field oxide layer; wherein a recess is formed on the surface of the gate oxide layer at a position corresponding to the adjacent boundary of the channel active region; the thickness of the gate oxide layer at the recess position is smaller than that at other positions; a gate layer is located on the surface of the gate oxide layer; wherein the gate layer forms a through opening at a position corresponding to the recess. In this way, the leakage and breakdown caused by the thinner gate oxide layer at the recess position can be reduced to a certain extent, and the reliability is improved.

The application discloses a linear voltage stabilizing circuit based on NMOS regulating tube, comprising a bias voltage generating circuit, a voltage division feedback circuit, an oscillator circuit, a charge pump circuit and a pre-voltage stabilizing circuit, wherein the bias voltage is generated through the bias voltage generating circuit; the output voltage is divided to obtain a feedback voltage through the voltage division feedback circuit; the feedback voltage is amplified and then input to the oscillator circuit to generate an oscillation signal; the generated oscillation signal is input to the charge pump circuit; the gate voltage of the NMOS regulating tube is adjusted through the charge pump circuit, so as to obtain the output voltage; the pre-voltage stabilizing circuit widens the input voltage range, so that the linear voltage stabilizing circuit can work in a high input voltage environment; the linear voltage stabilizing circuit based on the NMOS regulating tube has the characteristics of wide input range and low voltage difference, fast transient response speed, and is fully compatible with the thin gate oxide process.

The invention provides a semiconductor structure and a preparation method thereof, and a high-voltage MOS device. The semiconductor structure comprises a substrate; a source region, a drain region and a channel active region between the source region and the drain region are formed in the substrate; the field oxide layer is located between the channel active region and the source-drain region and defines the boundary of the channel active region; the gate oxide layer covers the channel active region and the field oxide layer; wherein the surface of the gate oxide layer is provided with a recess at a position corresponding to the junction of the adjacent boundaries of the channel active region; the thickness of the gate oxide layer at the sunken position is smaller than that of the gate oxide layer at other positions; the gate layer is located on the surface of the gate oxide layer; wherein a through hole is formed in a position, corresponding to the recess, of the gate layer. In this way, electric leakage and breakdown caused by the fact that the gate oxide layer at the sunken position is thin can be reduced to a certain extent, and reliability is improved.

The invention provides a super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and the super-junction MOSFET structure comprises a semiconductor substrate, an epitaxial layer, a gate oxide layer, a gate electrode, a matrix region, a source region, a source electrode and a drain electrode. The semiconductor substrate comprises a front face and a back face, and the straight line direction from the front face to the back face is the vertical direction. The epitaxial layer is arranged on the front surface of the semiconductor substrate and comprises first and second conductive columns which vertically extend from the front surface to the back surface and are alternately arranged in the horizontal direction; the gate oxide layer is arranged on the surface of the first conductive column, the gate electrode is arranged on the gate oxide layer, the matrix region is arranged in the upper region of the second conductive column, and at least one source region is formed in the matrix region. The source electrode is formed on the base body region and electrically connected to at least one source region, the source electrode and the gate electrode are insulated and isolated, and the drain electrode is arranged on the back face of the semiconductor substrate. According to the super-junction MOSFET structure, the thick and thin gate oxide region design is adopted, the gate-drain capacitance is reduced, the turn-off delay is shortened, the transition loss is reduced, and the dynamic performance is optimized.

This invention discloses a low-dielectric-absorption, low-mismatch precision linear MIM capacitor and its integration technology. The integration steps are as follows: 1) Forming an active region and an isolation field oxide region. 2) Forming a thick gate oxide layer and a thin gate oxide layer. 3) Depositing a polysilicon layer and constructing the polysilicon gate of the MOSFET. 4) Completing photolithographic implantation of the multi-mode gate oxide high and low voltage BiCMOS / CMOS source and drain electrodes. 5) Chemical mechanical planarization to improve the flatness of the surface region under the metal thin film resistor. 6) High resistivity microcrystalline titanium thin film sputtering of the lower electrode of the metal MIM capacitor using PVD method. 7) PECVD silicon nitride Si for the dielectric layer of the metal MIM capacitor. x N y H z 8) Sputtering of high resistivity microcrystalline titanium thin film on the top electrode of the metal MIM capacitor using PVD method. 9) Sputtering of aluminum-copper film layer and completion of metal interconnect etching. This invention not only optimizes the precision matching problem of metal MIM capacitors, but also improves the packaging functional density and device density of integrated circuits, promoting the miniaturization and lightweighting of high-performance integrated circuits.

The application provides an electrostatic protection device. The electrostatic protection device comprises an N-type epitaxial region, an N-type buffer region and a P-type body region; the N-type buffer region and the P-type body region are respectively embedded on two sides of an upper surface of the N-type epitaxial region, a metal anode arranged on the N-type buffer region is connected with a circuit interface, and a metal cathode is arranged on the N-type epitaxial region and / or the P-type body region; a first N+ region and a first P+ region are embedded on an upper surface of the N-type buffer region, a second P+ region and a second N+ region are embedded on an upper surface between the N-type buffer region and the P-type body region of the N-type epitaxial region, and a third N+ region and a third P+ region are embedded on an upper surface of the P-type body region; a thin gate oxide layer is arranged between the second N+ region and the third N+ region, and the thin gate oxide layer is arranged on a connection between the upper surfaces of the N-type epitaxial region and the P-type body region; a gate electrode is further arranged on the thin gate oxide layer, and the second P+ region, the second N+ region and the gate electrode are electrically connected. The application can reduce the trigger voltage of the electrostatic protection device.

Circuits and methods for high-quality amplifiers (e.g., low-noise amplifiers and power amplifiers) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. Some embodiments include a thin gate oxide N-type MOSFET device or N-type Extended Drain MOSFET (NEDMOS) device co-fabricated with one or more serially-coupled thick gate oxide P-type Extended Drain MOSFET (PEDMOS) devices of several types. Some embodiments include one or more multi-gate NEDMOS devices. Embodiments includes PEDMOS devices having at least source and drain regions that include germanium (e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si and graded Ge and Si mixtures), particularly PEDMOS devices having a strained channel region. A significant benefit of the inventive IC structures and variants is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain / source regions.

The application discloses a dynamic high-voltage signal transmission switch circuit suitable for a thin gate oxide layer process, which comprises a symmetric double NMOS tube switch, a floating power rail generation module and a LevelShift level conversion module; the symmetric double NMOS tube switch comprises two N-type transistors, the gate and the source of the two N-type transistors are connected respectively, and the drain of the two N-type transistors is used as an input end of a high-voltage signal; the floating power rail generation module is connected to the source of the two N-type transistors in the symmetric double NMOS tube switch and is used for generating a floating power rail by tracking the amplitude of the dynamic high-voltage signal; the LevelShift level conversion module is connected to the floating power rail generation module and the gate of the two N-type transistors in the symmetric double NMOS tube switch and is used for converting a digital control signal corresponding to an input low power rail 0V-5V into an analog control signal corresponding to the floating power rail so as to control the conduction and the turn-off of the symmetric double NMOS tube switch. The application ensures that the thin gate oxide layer MOS tube switch is in a safe voltage-withstanding range when transmitting the dynamic high-voltage signal.

The invention discloses a true random number generator and method of a stepped gate-oxide anti-fuse transistor, and the true random number generator comprises at least one logic unit which is designed based on a stepped gate-oxide anti-fuse PROM transistor, a reading unit and a power circuit, and has a symmetrical structure. Under the action of programming high voltage, one-time breakdown with equal opportunities can occur at the thin gate oxide region on the left side or the right side to form a breakdown channel, the probability of the breakdown channel occurring in the thin gate oxide region on the left side and the probability of the breakdown channel occurring in the thin gate oxide region on the right side are equal, and the probability of changing a storage state into a low-resistance state and a high-resistance state are half. By detecting the storage state of the anti-fuse PROM transistor, a binary random number can be obtained to realize high-encryption security key data generation and management.

A radiation-hardened silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) device structure and a preparation method thereof, comprising an N− drift layer, an N+ substrate layer is arranged beneath the N− drift layer, a carrier storage layer is arranged above the N− drift layer, a source metal layer is arranged above the carrier storage layer, a junction field-effect transistor (JFET) region is arranged in a middle beneath the source metal layer, a trench is introduced inside the JFET region, an interior of the trench is provided with a P-type doped region and a filling region, P-base regions are arranged on both sides of the trench, N+ source regions and P+ regions are arranged in the P-base regions. The invention significantly reduces electric field strength in the thin gate oxide, thereby enhancing the single-event gate rupture immunity of the device.

The invention provides a voltage conversion circuit based on a thin gate oxide device, which comprises a charge pump circuit and a level conversion circuit connected with the control end of the charge pump circuit, and is characterized in that the level conversion circuit converts a plurality of input control signals in a power domain from 0 to VDD into output control signals in a plurality of target power domains, the charge pump circuit boosts the VDD based on the plurality of output control signals to obtain an output voltage. The voltage difference between the lowest voltage and the highest voltage of each target power supply domain is set to be smaller than the gate-source breakdown voltage of the thin gate-oxide device, so that the absolute value of the gate-source voltage of each transistor in the charge pump circuit is smaller than the gate-source breakdown voltage of the thin gate-oxide device, and the thin gate-oxide device can be adopted by each transistor in the charge pump circuit; according to the invention, the high-voltage output charge pump based on the thin gate oxide device can be realized, the area occupied by the circuit can be reduced to realize circuit miniaturization, and the circuit cost can also be reduced.

This invention discloses a method and structure for integrating thick and thin gate oxide CMOS devices in a dual polycrystalline self-aligned bipolar junction transistor (DPT) process. The method includes providing an SOI silicon substrate; sequentially forming an N-type primary buried layer (103) of the dual polycrystalline self-aligned bipolar junction transistor, a P-type primary buried layer (104) of the thin gate oxide NMOS, and a P-type secondary buried layer (105) of the thick gate oxide NMOS; forming an epitaxial layer (106) on the SOI silicon substrate; and forming a P-type primary well region (107) of the thin gate oxide NMOS and a P-type secondary well region (108) of the thick gate oxide NMOS in the epitaxial layer. The semiconductor device of this invention can realize various combinations of high-performance NPN / PNP and thick and thin gate oxide CMOS devices, effectively improving the overall device characteristics of the process to meet the needs of a wider range of applications and enhance the electrical performance of the chip.

The application relates to a semiconductor structure and a preparation method thereof, which comprises a substrate, a voltage adjustment layer, a thin gate oxide layer and a thick gate oxide layer. The substrate comprises a first transistor region and a second transistor region. The voltage adjustment layer is located in the first transistor region. The thin gate oxide layer is located on the voltage adjustment layer. The thick gate oxide layer is located in the second transistor region. The density of at least part of the thick gate oxide layer is different from that of the thin gate oxide layer. The application is beneficial to the threshold voltage of a thin gate PMOS reaching the device requirement.

The application discloses a BiCMOS integration method based on standard bipolar devices, which comprises the following steps: 1) forming A buried layer regions and a plurality of isolation regions on a substrate; 2) forming a field region; 3) forming a first base region and a second base region; 4) etching a first gate oxide layer by using a mask pattern, and then growing a second gate oxide layer and a third gate oxide layer by oxidation to form thick and thin gate oxides; 5) forming a gate oxide polycrystal of a MOS tube; 6) forming a first emitter region, a first base heavy contact region, a first CMOS source-drain region and a second DMOS source-drain region; 7) forming a second emitter region, a second base heavy contact region, a second CMOS source-drain region and a third DMOS source-drain region; 8) forming a first dielectric layer; 9) etching a CT hole by using a mask; performing metal deposition, etching a metal end by using a mask pattern, and forming BJT, CMOS and DMOS devices. The application realizes complementary bipolar technology without increasing the number of photolithography layers, and enriches the selectable types of devices to meet more extensive and higher demand application technical fields.

The invention discloses a structure for enhancing the capability of a safe working region of a shield gate trench MOSFET device and a preparation method, and the structure is characterized in that a thick gate oxide layer region and a thin gate oxide layer region are formed in an active region trench of the MOSFET device, so that a high-threshold-voltage cell and a low-threshold-voltage cell are formed; when the gate-source voltage is small in the using process of the device, the low-threshold-voltage cells are opened, the high-threshold-voltage cells are not opened, and a part of cells are not opened, so that the power density of the whole device is reduced, the heat dissipation capability is enhanced, the zero-temperature coefficient point of the device is reduced, the safe working area of the device is improved, and the service life of the device is prolonged. A device structure with a wide safe working area characteristic is integrated in an active area, so that the performance of the safe working area is enhanced, the conduction loss of the device is still not influenced after the device is completely started, and the device has a wider application prospect; in addition, the manufacturing process method is simple and can be compatible with a traditional MOSFET manufacturing process.

The application provides a shield gate trench structure and a preparation method thereof. Since a plurality of SBR devices are simultaneously integrated in an epitaxial layer corresponding to an active region of the shield gate trench structure, when the shield gate trench structure is normally working, the opening voltage of the thin gate oxide layer of the SBR device is lower than that of the PN junction formed between the epitaxial layer and the body region, so that when the device is turned off, the current of the parasitic capacitor is rapidly released from the barrier MOS channel of the SBR device, and the current does not pass through the parasitic PN junction, thereby greatly improving the reverse recovery characteristic of the device compared with the conventional SGTMOSFET device, effectively reducing the loss caused by the high opening voltage, reducing the switching loss in the high-frequency switching process, and finally achieving the purpose of improving the conversion efficiency of the direct-current-direct-current conversion control circuit.