Apparatus for providing SRAM and CAM bit cell

A technology of bit cells and storage cells, applied in electrical components, static memory, instruments, etc., to improve access speed, reduce standby power consumption, and improve Vcc

Active Publication Date: 2011-04-20
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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  • Apparatus for providing SRAM and CAM bit cell
  • Apparatus for providing SRAM and CAM bit cell
  • Apparatus for providing SRAM and CAM bit cell

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Embodiment Construction

[0069] The method of making and using the preferred embodiment of the present invention will be described in detail as follows. The many inventive application concepts provided by the present invention can be implemented in a wide variety of specific contexts. The specific embodiments discussed below are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0070] Figure 4 is an embodiment of the present invention, showing a circuit diagram of an 8T SRAM bit cell 40, which incorporates the features of the double gate oxide layer of the present invention. exist Figure 4 The 6T memory cell section 42 is equipped with 2 such Figure 1-Figure 3 PMOS pull-up transistors PU1 and PU2 shown, and 4 as Figure 1-Figure 3 NMOS transistors PG1, PG2, PD1 and PD2 are shown. In this invention, thick gate dielectric layers are used to form the four NMOS transistors. By using a thick gate dielectric layer, the standby current ...

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Abstract

The invention provides circuits and methods for providing an SRAM and CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.

Description

technical field [0001] The present invention relates to a static random access memory (Static Random Access Memory, SRAM) bit cell structure and a method for providing a bit cell with improved standby leakage current (Isb) to obtain improved standby action, improved Vcc,min, Reduced supply levels have minimum power, high read times. [0002] The bitcell includes a new layout with multiple thickness gate oxides in the cell transistors. The use of the present invention provides the advantage of using SRAM for integrated circuits with logic circuits or user-specified circuits. In addition to SRAM arrays of SRAM bit cells, SRAM cells also possess improved stability and provide reliable operation in a wide range of conditions. Methods of fabricating SRAM bit cells incorporating features of the present invention are compatible with existing state of the art and planned semiconductor processes. Background technique [0003] Today's general requirement for electronic circuits, es...

Claims

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Application Information

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IPC IPC(8): H01L27/11H01L29/10
CPCG11C11/412G11C15/04
Inventor 王屏薇杨昌达米玉杰
Owner TAIWAN SEMICON MFG CO LTD
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