363 results about "Standby current" patented technology

A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and precharge standby currents in memory input buffers may be reduced by turning off the input buffers when the CS signal is in an inactive state. A memory controller may supply the CS signal to the memory device at least one clock cycle earlier than other control signals including the RAS (row address strobe) signal, the CAS (column address strobe) signal, the WE (write enable) signal, etc. A modified I/O circuit in the memory device may internally delay the CS signal by at least one clock cycle to coincide its timing with the RAS/CAS signals for normal data access operation whereas the turning on/off of the memory input buffers may be performed by the CS signal received from the memory controller on the previous cycle. Thus, activation and deactivation of memory input buffers may be performed without forcing the memory device into power down mode and without employing complex circuits for power management. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

An integrated circuit (100) includes a first input (108) to receive a first operating voltage Vcc and a second input (110) to receive a second operating voltage Vss. Operating circuitry (102) of the integrated circuit is coupled to the first input to power the operating circuitry. A transistor (104) is coupled between the second input and the operating circuitry to selectively provide the second operating voltage to the operating circuitry of the integrated circuit. The well containing the transistor is biased to provide a reverse body effect and reduce the threshold voltage of the transistor to allow operation at very low Vcc.

An electrical control unit for an automobile of which standby current is smaller. In an electrical control unit for an automobile having a microcomputer, an input circuit, a driver circuit, and a power supply circuit, which is started by a wake-up signal from the circuit other than the ignition switch even when the ignition switch of the automobile is cut off, the microcomputer is started by shifting the power supply circuit from an inert state to an active state to generate the voltage for operating the microcomputer, and the predetermined processing is executed.

A precharge voltage generating circuit outputs any of a plurality of kinds of precharge voltages in accordance with an ambient temperature. A precharge circuit supplies the precharge voltage to a bit line during the nonaccess of a dynamic memory cell. A sense amplifier amplifies a difference between the voltage of a data signal read from the dynamic memory cell onto the bit line and the supplied precharge voltage. The precharge voltage is altered in accordance with the ambient temperature, whereby the read margin of the sense amplifier can be changed, and the worst value of the data retaining time of the memory cell can be improved. As a result, the frequency of refreshing of the memory cell can be lowered, reducing power consumption and a standby current.

A memory device (200) can include a memory cell block (202), a standby current source (206), an active current source (208), and a clamping device (212). In a standby mode, a standby current source (206) can provide constant standby current I_STBY to memory cell block (202) via block supply node (204). In an active mode, active current source (208) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit (212) can provide additional current in the event a block supply node (204) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well (454) to source (404) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (454), reducing overall leakage.

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Background scan for 802.11 client devices allows them to keep most of its components in low power mode when certain criteria are not met. A method for changing dynamically those criteria according to the air data traffic conditions is described in the present invention. This increases the time the system remains in sleep mode and consequently improves the standby current consumption to portable 802.11 enabled media.

It is herein described a battery monitoring system, in particular for a vehicle battery, which comprises the steps of: calculating, based on the battery voltage (1), the parameters of the battery state of health (SoH), battery state of charge (SoC) and stand-by current (IOD); comparing the battery state of health (SoH), the battery state of charge (SoC) and stand-by current (IOD) parameters with their previously established limits; and providing a warning sign when any parameter is different from its previously pre-defined limit. The system allows monitoring a vehicle battery (1) beginning from its installation and provides the driver indications about the necessity of maintenance or replacement thereof, exclusively based on the battery voltage, measured at specific times of the vehicle operation.

A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.

An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

A high gain, highly linear mixer includes an input section, mixing section, at least one tuning component, and at least one stand by current source. The input section is operably coupled to receive an input voltage signal and perform a linear transconductance thereon to produce an input current signal. The mixing section is operably coupled to mix a local oscillation with the input current to produce a mixed current signal. The tuning component is operably coupled to the mixing section and to convert the mixed current signal into a mixed voltage signal that function as the output of the mixer. The standby current source is operably coupled to the mixing section and provides a standby current to the mixing section.

A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N₂ plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

The invention discloses a testing system and a testing method for a standby current of a movable terminal; the testing system includes a sampling resistance, a multimeter, a power and a movable terminal which are connected in series for forming a testing loop as well as a data collector connected in parallel with the sampling resistance; the invention further includes a comprehensive measuring device connected with the movable terminal and a shielding box which shields the movable terminal inside the shielding box. During testing, the movable terminal is arranged in a testing network environment and the movable terminal is started into a standby state; then the testing is started, the voltage at the two ends of the sampling resistance connected in series with the movable terminal is collected in real time by the data collector; the voltage data of the whole standby measuring process is preserved; after the measurement is finished, a real time standby current value in the whole standby process is obtained according to the relation formula of the voltage that I is equal to U/R; and the average standby current value during the standby measuring process is further obtained by an integral mean of (1/t) multiply the integral of f from 0 to t. The invention has the advantages of high technical precision, high flexibility and being capable of tracing the state change of a mobile phone terminal.

Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.