The utility model discloses a
delay power-off and power-on
impact current suppression circuit, which comprises a PMOS tube Q15, an NPN tube Q10, an NPN tube Q13 and an NPN tube Q14, the source
electrode of the PMOS tube Q15 is connected with a power supply end Vbat +, the drain
electrode of the PMOS tube Q15 is connected with a load, a
capacitor C60 is connected between the source
electrode and the grid electrode of the PMOS tube Q15, the grid electrode
voltage of the PMOS tube Q15 is loaded on the collector electrode of the NPN tube Q10 and the collector electrode of the NPN tube Q13, and the NPN tube Q14 is connected with the NPN tube Q13. The emitter electrode of the NPN tube Q10 is grounded, the base electrode of the NPN tube Q10 is used for accessing a DSP enable
signal sent by a controller, the emitter electrode of the NPN tube Q13 is grounded, the collector electrode of the NPN tube Q14 is connected with a
high potential + 3.3 V through a
resistor R218, the collector electrode of the NPN tube Q14 is used for transmitting an
activation detection signal to the controller, and the emitter electrode of the NPN tube Q14 is grounded. And the base electrode of the NPN tube Q13 and the base electrode of the NPN tube Q14 are used for accessing an external activation
signal. The power-on
impact current suppression circuit has a power-on
impact current suppression function, has no
standby current and can
delay power-off.