130 results about "Sram cell" patented technology

The invention relates to the technical field of static storage, and particularly discloses an anti-radiation SRAM (Static Random Access Memory) unit, array and storage and calculation integrated system, which realizes the balance of anti-radiation capability and engineering feasibility through the collaborative design of a circuit and the system. A polarity-reinforced RHCIM-16T unit structure is adopted as the core, and directional conductive constraint is introduced, so that complex multi-node flipping is simplified into a single'lock 0 'error, and the error rate is reduced from the source. On the basis, a lightweight single error correction code is combined to form an efficient fault-tolerant mechanism of circuit simplification and SEC coding. According to the scheme, through the design of splitting word lines and the like, logic operations such as AND and NOR are compatible, and stable execution of the storage and calculation integrated function in a radiation environment is ensured. Simulation and experiment results show that the robustness and the expandability of the memory array in the radiation environment can be remarkably enhanced while the relatively low area and the relatively low power consumption overhead are maintained.

A sub-threshold monostable PUF circuit with an SRAM function and an entropy source extraction function includes a mode configuration circuit, a decoding circuit, a PUF array and a reading circuit. The PUF array has a SRAM storage mode and a PUF mode for generating an entropy source voltage. The PUF array includes m*n PUF cells and n pre-charge modules. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor. The monostable PUF array formed by PUF cells is constructed only by adding a first PMOS transistor, a first NMOS transistor and a fourth NMOS transistor in each SRAM cell of an original SRAM storage array of IoT equipment.

A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source / drain (S / D) epi regions, a top FET including a plurality of top S / D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S / D epi region of the plurality of bottom S / D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).

A charge-domain IMC circuit is disclosed and includes: a cluster of 6T SRAM cells; a charge-domain MAC circuit; and an LBL connected to a bit-line of each of the 6T SRAM cells. The MAC circuit includes: a MOS transistor; an input switch; an output switch; an input port; an output port; and a capacitor. The LBL is connected to a gate of the MOS transistor. A first terminal of the MOS transistor is connected to a DC voltage, and a second terminal of the MOS transistor is connected to the output port via the output switch. The second terminal of the MOS transistor is connected to the input port via the input switch and to a first side of the capacitor. A second side of the capacitor is grounded. Other variants of the IMC circuit are disclosed, some of which having a ciSAR ADC or a TD-ADC.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

The utility model provides an SRAM (Static Random Access Memory) unit, an SRAM circuit and a memory, comprising ten MOS (Metal Oxide Semiconductor) tubes, namely M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10; m1, M3, M5, M6, M7, M8 and M10 are NMOS (N-channel Metal Oxide Semiconductor), and M2, M4 and M9 are PMOS (P-channel Metal Oxide Semiconductor). The SRAM cell may be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOS (Metal Oxide Semiconductor) tubes on the basis of the existing 6T SRAM. When the 10T SRAM reads and writes data, the 10T SRAM is similar to an 8T SRAM, and the read-write speed of the 10T SRAM is slightly slower than that of the 8T SRAM, but is higher than that of a 6T SRAM. After the 10T SRAM is combined, the 10T SRAM can be directly used for copying the data, an ALU is not needed when the data is copied, and the speed of copying the data is obviously improved.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory), comprising: a first pull-up MOS device (PU-1) (MOS: metal oxide semiconductor) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2), forming inverters cross-locked to the first pull-up MOS device (PU-1) and the second pull-up MOS device (PD-2); an elongated contact (54) located over and electrically connected to a source of the first pull-down MOS device (PD-1); a first metal layer (M1) containing a bit line and a CVdd line; a first CVss contact island (52B) overlapping the elongated contact (54) and is electrically connected to this, wherein the first CVss contact island (52B) has a part in the SRAM cell (10) which has a first length and a first width,which are smaller than a second length and a second width of the SRAM cell (10), wherein the SRAM cell (10) has a first boundary (10A) and a second boundary (10B) that are parallel to each other, and a third boundary (10C) and a fourth boundary (10D) that are parallel to each other, and the first CVss contact island (52B) overlaps the first boundary (10A) and the fourth boundary (10D) but does not extend beyond the second boundary (10B) and the third boundary (10C); a first word line (50) having a first longitudinal direction, wherein the first word line (50) extends from the third boundary (10C) to the fourth boundary (10D), wherein the first word line (50) and the first CVss contact island (52B) are located in a second metal layer (M2) above the first metal layer (M1), and wherein the first word line (50) forms a strip portion (50A) and has a protruding part (50B),which is connected to a part of a first side wall of the strip section (50A) in the first longitudinal direction and extends in a direction perpendicular to the first longitudinal direction, wherein the projecting part (50B) extends in the direction of the first boundary (10A) and is spaced from the first boundary (10A) and further extends from the third boundary (10C) in the direction of the fourth boundary (10D) and is spaced from the fourth boundary (10D), wherein the CVss contact island (52B) and the projecting part (50B) are spaced apart by a distance S1 so that they do not electrically short-circuit, wherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 <= W2 / W1 <= 0.5,wherein the width of the first word line (50) is increased by the projecting part (50B) and thereby the resistance of the first word line (50) is reduced; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2), wherein the first CVss line (58) is electrically connected to the first CVss contact island (52B) and has a second longitudinal direction that is perpendicular to the direction of the first longitudinal direction.

Fast low leakage SRAM cells, e.g., for digital display systems, are disclosed herein. In one embodiment, a bit memory circuit includes a latch coupled between a supply voltage and ground, and first to fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the supply voltage based at least in part on a first control signal. The second transistor may selectively couple an input of the first inverter to ground based at least in part on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the supply voltage based at least in part on the second control signal. The fourth transistor may selectively couple an input of the second inverter to ground based at least in part on the first control signal.

The invention provides a static random access memory unit, a preparation method thereof and electronic equipment. The static random access memory unit comprises a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor; a first transfer transistor and a second transfer transistor; a first power rail and a second power rail disposed on a back surface of the SRAM cell; in the vertical direction, the position of the first power supply rail corresponds to the first pull-up transistor and the second pull-up transistor, and the first power supply rail is electrically connected with the first pull-up transistor and the second pull-up transistor through back source drain contact metal; the position of the second power rail corresponds to the first pull-down transistor and the second pull-down transistor, and the second power rail is electrically connected with the first pull-down transistor and the second pull-down transistor through the back source drain contact metal. According to the invention, the unit height of the SRAM unit is reduced, and high-density integration of the SRAM unit is realized.

The invention provides an 8T SRAM (Static Random Access Memory) unit, an 8T SRAM and a preparation method thereof, the 8T SRAM unit comprises a substrate, a pull-up transistor group, a pull-down transistor group and a transmission gate transistor group, the pull-up transistor group and the transmission gate transistor group are integrated on the front surface of the substrate, the pull-down transistor group is integrated on the back surface of the substrate, and the transmission gate transistor group is integrated on the back surface of the substrate. The first pull-down group comprises a first pull-down transistor and a second pull-down transistor which are arranged in parallel, and the second pull-down group comprises a third pull-down transistor and a fourth pull-down transistor which are arranged in parallel; the first pull-up transistor and the first pull-down group form a first phase inverter, the second pull-up transistor and the second pull-down group form a second phase inverter, and the first phase inverter and the second phase inverter are in cross coupling; the transmission gate transistor group comprises a first transmission gate transistor and a second transmission gate transistor, the first transmission gate transistor is connected with the first phase inverter, and the second transmission gate transistor is connected with the second phase inverter. According to the invention, the stability of the SRAM unit is improved.

An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source / drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source / drain contact region is over a source / drain of the write-assist transistor and a source / drain of the pull-up transistor.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

Embodiments of the present disclosure relate to circuitry for regulating a hold voltage of a static random access memory. A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between a first voltage and a second voltage. A reference voltage generator generates a reference voltage proportional to absolute temperature, an amplitude curve of the reference voltage is based on a control word. A low dropout amplifier sets and maintains the second voltage equal to the reference voltage. A control circuitry generates the control word based on process variation information about the SRAM device. In one example, the control circuitry monitors an alarm bit cell and increments the control word, thereby increasing the amplitude curve of the reference voltage, until the alarm bit cell fails. In another example, the control circuitry measures an oscillation frequency of a ring oscillator, and selects the control word based on the measured oscillation frequency.

Provided is an SRAM cell structure having 3 P-channel transistors and 3 N-channel transistors. The SRAM cell device includes a first inverter composed of a CMOS; a second inverter composed of a CMOS, the input terminal of which is connected to the output terminal of the first inverter, and the output terminal of which is connected to the input terminal of the first inverter; a first access transistor connected between the bit line (BL) and the input terminal of the first inverter; and a second access transistor connected in parallel with the first access transistor. The first access transistor is composed of an N-channel transistor and is switched by the WL signal. The second access transistor is composed of a P-channel transistor and is switched by the inverse signal (WWL) of the WRITE signal.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Embodiments of the invention relate to computing devices and computing methods. In some examples, a computing device in a memory includes a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a current-based nine-transistor SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switch transistor, controlled by an input signal on an input line, associated with the column of memory cells in which the memory cell resides. The current source includes a switch transistor controlled by the state of the six-transistor SRAM cell, and a current regulation transistor to produce a current level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line in each successive column of memory cells increases by a factor of 2.

An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input / output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De / Ds equals to 2 or is less than 2.

A method for fabricating a semiconductor device is disclosed, the method comprising: forming a first stack of a first transistor structure on a substrate; and forming a second stack of a second transistor structure adjacent to the first stack on the substrate. The second stack is formed adjacent to the first stack such that a stacked S / D region at one end of the first stack faces a corresponding stacked S / D region at one end of the second stack. A first pair of facing S / D regions of the first stack and the second stack are connected by forming an interconnect structure extending horizontally to physically connect the first pair of facing S / D regions to each other. Second pairs of facing S / D regions of the first stack and the second stack are maintained as a pair of physically separated facing S / D regions. A first metal interconnect structure and a second metal interconnect structure are connected to corresponding S / D regions in the second pair of facing S / D regions.

Systems and methods for limiting negative bit line voltage in SRAM cells are provided. A voltage limiter circuit can be implemented in a write driver to control the magnitude of negative voltage applied on a bit line. The voltage limiter circuit can generate a negative bit line voltage of a desired magnitude at a lower operating voltage level. The voltage limiter circuit can also limit the magnitude of the negative bit line voltage to not exceed a predetermined value. The reduction in the negative bit line voltage magnitude can reduce the effective power supply of the SRAM cell. Embodiments of the present application also provide memory circuits, write drivers, and methods of operating the same.

An IC device includes a first complementary field-effect transistor (CFET) static random-access memory (SRAM) cell in a semiconductor wafer, the first CFET SRAM cell including a first internal node and a first pass gate including a first source / drain (S / D) region and a second S / D region electrically connected to the first internal node, and a second CFET SRAM cell in the semiconductor wafer, the second CFET SRAM cell including a second internal node and a second pass gate including a third S / D region and a fourth S / D region electrically connected to the second internal node, wherein the first S / D region is aligned with the third S / D region in a direction perpendicular to a frontside of the semiconductor wafer and a backside of the semiconductor wafer

A method includes forming a first read pull-down transistor and a first read pass-gate transistor over a substrate at a first level height, wherein the first read pull-down and first read pass-gate transistors are of a first read port of a static random access memory (SRAM) cell; forming a second read pull-down transistor and a second read pass-gate transistor over the substrate at a second level height higher than the first level height, wherein the second read pull-down and second read pass-gate transistors are of a second read port of the SRAM cell.

An example is a method. A first logical value is written to a latch node of a latch circuit of a half static random access memory (SRAM) cell. A second logical value is read from the latch node. The latch circuit is non-inverter-based. The latch circuit includes a p-type transistor and an n-type transistor. A drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor, and a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor. According to some examples, the half SRAM cell may be implemented as a storage node, for a physical unclonable function (PUF), and / or for data padding.

Technology for generating an SRAM-based in-memory computing macro includes replacing a SRAM cell cluster defined by a generic SRAM macro with a single-bit multi-bank cluster, the single-bit multi-bank cluster including a plurality of CiM SRAM cells and a plurality of C-2C capacitor ladder cells, arranging a plurality of single-bit multi-bank clusters to form a multi-bit multi-bank cluster, and arranging a plurality of multi-bit multi-bank clusters into a multi-dimensional MAC computational unit within a region of the generic SRAM macro, where an output of at least two of the multi-bit multi-bank clusters are electrically coupled to form an output analog activation line, and where a plurality of bit lines and a plurality of word lines remain at the same grid locations as provided in the generic SRAM macro. Embodiments include arranging a plurality of multi-dimensional MAC computational units into an in-memory MAC computing array.

Embodiment herein describe read and write assists for SRAM cells. When performing a write operation, a write assist technique can be performed on the SRAM macro where a word line (WL) for the selected row is boosted to a voltage above the voltage supply. In addition, cell supply voltages for unselected columns are boosted to prevent the boosted WL from flipping bit values in unselected cells. When performing a read operation, a read assist technique can be performed on the SRAM macro, where the Vcell for the selected column is boosted to a voltage above the voltage supply. In another embodiment, the WL for the selected row of the read operation can also be boosted for enhancing the read performance.

This invention relates to an in-memory computing circuit in the field of integrated circuits, and particularly to a multifunctional in-memory computing circuit and chip based on a 9T1C-SRAM cell. The multifunctional in-memory computing circuit includes five NMOS transistors N1-N5, four PMOS transistors P1-P4, and a capacitor C0. P1, P2, N1, and N2 form a latch structure; N3 controls row-direction read / write operations via word line WL and bit line BL; P3, P4, N4, and N5 are used to implement Boolean logic write-back, row-direction read / write, and multiply-accumulate functions. This invention's multifunctional in-memory computing circuit simultaneously supports Boolean logic write-back, signed multiply-accumulate (MAC) operations, and bidirectional row and column read / write, achieving deep integration of logical operations, arithmetic operations, and data movement within the same memory cell.

This application provides an SRAM cell and an SRAM memory device. The SRAM cell includes a substrate, and a latch module, a write module, and a read module integrated on the substrate. The latch module includes a pull-up transistor group and a pull-down transistor group, forming a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first memory node and a second memory node. The write module includes a first transmission gate transistor group, which connects a first write word line and a first write bit line pair. The first transmission gate transistor group includes a first transmission gate transistor and a second transmission gate transistor. The first transmission gate transistor is connected to the first memory node, and the second transmission gate transistor is connected to the second memory node. The read module includes a first read module and a second read module, which are connected to the first memory node and the second read module is connected to the second memory node. This application improves parallel access capabilities.