252 results about "Sram cell" patented technology

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.

The invention relates to the technical field of static storage, and particularly discloses an anti-radiation SRAM (Static Random Access Memory) unit, array and storage and calculation integrated system, which realizes the balance of anti-radiation capability and engineering feasibility through the collaborative design of a circuit and the system. A polarity-reinforced RHCIM-16T unit structure is adopted as the core, and directional conductive constraint is introduced, so that complex multi-node flipping is simplified into a single'lock 0 'error, and the error rate is reduced from the source. On the basis, a lightweight single error correction code is combined to form an efficient fault-tolerant mechanism of circuit simplification and SEC coding. According to the scheme, through the design of splitting word lines and the like, logic operations such as AND and NOR are compatible, and stable execution of the storage and calculation integrated function in a radiation environment is ensured. Simulation and experiment results show that the robustness and the expandability of the memory array in the radiation environment can be remarkably enhanced while the relatively low area and the relatively low power consumption overhead are maintained.

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.

A sub-threshold monostable PUF circuit with an SRAM function and an entropy source extraction function includes a mode configuration circuit, a decoding circuit, a PUF array and a reading circuit. The PUF array has a SRAM storage mode and a PUF mode for generating an entropy source voltage. The PUF array includes m*n PUF cells and n pre-charge modules. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor. The monostable PUF array formed by PUF cells is constructed only by adding a first PMOS transistor, a first NMOS transistor and a fourth NMOS transistor in each SRAM cell of an original SRAM storage array of IoT equipment.

A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source / drain (S / D) epi regions, a top FET including a plurality of top S / D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S / D epi region of the plurality of bottom S / D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and / or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source / drain (S / D) epi regions, a top FET including a plurality of top S / D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S / D epi region of the plurality of bottom S / D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass- gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

A semiconductor structure is provided comprising a bottom field-effect transistor (FET) including a plurality of bottom source / drain (S / D) epitaxial regions, an top FET including a plurality of top S / D epitaxial regions, a dielectric interconnect layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S / D epitaxial region of the plurality of bottom S / D epitaxial regions of the bottom FET through the dielectric interconnect layer and into the top FET. The bottom FET includes an inverter gate. The top FET is electrically connected to back-end-of-line (BEOL) components, and the bottom FET is electrically connected to a back-side power supply network (BSPDN).

A charge-domain IMC circuit is disclosed and includes: a cluster of 6T SRAM cells; a charge-domain MAC circuit; and an LBL connected to a bit-line of each of the 6T SRAM cells. The MAC circuit includes: a MOS transistor; an input switch; an output switch; an input port; an output port; and a capacitor. The LBL is connected to a gate of the MOS transistor. A first terminal of the MOS transistor is connected to a DC voltage, and a second terminal of the MOS transistor is connected to the output port via the output switch. The second terminal of the MOS transistor is connected to the input port via the input switch and to a first side of the capacitor. A second side of the capacitor is grounded. Other variants of the IMC circuit are disclosed, some of which having a ciSAR ADC or a TD-ADC.

An integrated circuit (IC) structure includes a device layer, a first word line, a second word line, a first bit line, and a second bit line. The device layer includes first and second static random access memory (SRAM) cells arranged along a first direction in a top view. The first and second word lines extend along the first direction and respectively electrically coupled to the first and second SRAM cells. The first bit line is over a frontside of the device layer. The first bit line extends along a second direction and electrically coupled to the first and second SRAM cells. The second direction is different from the first direction in the top view. The second bit line is over a backside of the device layer. The second bit line extend along the second direction and electrically coupled to the first and second SRAM cells.

The invention relates to the field of integrated circuits, and discloses a reconfigurable 10T SRAM (Static Random Access Memory) unit circuit for energy-saving CAM (Content Addressable Memory) operation and memory calculation. The 10T SRAM circuit comprises reading ports which are decoupled in the horizontal direction and the vertical direction, supports cross-row and cross-column reading operation, and realizes matrix transposition, logic operation and parallel search functions. The invention provides a self-suppression discharge mechanism, the discharge swing of the matching line is obviously reduced, the sneak current problem caused by multi-row activation is effectively solved, and the anti-interference capability of the circuit is improved. Aiming at storage and calculation requirements, the invention provides three working modes, namely a conventional SRAM (Static Random Access Memory) mode, an in-memory logic operation mode and a content addressable memory mode. Especially in a content addressable memory mode, line-by-line search is adopted, additional data movement caused by vertical data storage is avoided, and compatibility among different working modes is enhanced.

Provided are a static random access memory (SRAM) cell, a memory, and an electronic device. The SRAM cell may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor on a substrate. The first and second pull-up transistors are provided at a first height relative to the substrate. The first and second pull-down transistors and the first and second pass-gate transistors are provided at a second height different from the first height relative to the substrate. Each of the transistors includes a channel nanosheet extending in a first direction and source / drain portions provided above and below the channel nanosheet respectively. The first pull-down transistor is aligned with the first pull-up transistor in a vertical direction, and the second pull-down transistor is aligned with the second pull-up transistor in the vertical direction.

An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

A static random access memory (SRAM) and its formation method are disclosed, comprising a substrate; a plurality of SRAM cells on the substrate, each SRAM cell including a plurality of channel layers, a plurality of gate structures, and a plurality of source / drain doped layers; a first dielectric layer on the substrate; a first conductive structure electrically connected to a portion of the gate structures and a portion of the source / drain doped layers; and a shared conductive structure including a second conductive structure and a shared conductive layer on the second conductive structure, wherein the top surface of the shared conductive structure is lower than the top surface of the first conductive structure. Because the top surface of the shared conductive structure is lower than the top surface of the first conductive structure, a larger formation space is provided for the subsequently formed power conductive layer, thereby increasing the process window of the power conductive layer, reducing the contact resistance between the power conductive layer and the subsequently formed second pull-up conductive layer, and effectively improving the performance of the SRAM.

The invention provides a memory device and a reading method thereof. The memory device comprises a four-transistor (4T-SRAM) unit and a sensing circuit. The 4T-SRAM cell comprises two P-type MOSFET devices used for data bit storage and two N-type MOSFET devices used for access switches, and the 4T-SRAM cell has the advantages that the number of the MOSFET devices is small, and smaller cell size and low leakage current can be achieved. The sensing circuit comprises a switching device, a sensing latch and a discharging device. The switching device coupled between the sense latch and a ground voltage rail is designed to reduce read disturbances of the sense circuit to the 4T SRM cell by cutting off a channel leakage current path from an NMOSFET transistor in the sense latch to the ground voltage rail. A differential voltage signal for reading digital data stored in a 4T SRAM cell is enhanced by increasing sensing time. The read margin of the 4T SRAM is then greatly improved, thereby achieving an excellent and reliable read.

An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

The utility model provides an SRAM (Static Random Access Memory) unit, an SRAM circuit and a memory, comprising ten MOS (Metal Oxide Semiconductor) tubes, namely M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10; m1, M3, M5, M6, M7, M8 and M10 are NMOS (N-channel Metal Oxide Semiconductor), and M2, M4 and M9 are PMOS (P-channel Metal Oxide Semiconductor). The SRAM cell may be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOS (Metal Oxide Semiconductor) tubes on the basis of the existing 6T SRAM. When the 10T SRAM reads and writes data, the 10T SRAM is similar to an 8T SRAM, and the read-write speed of the 10T SRAM is slightly slower than that of the 8T SRAM, but is higher than that of a 6T SRAM. After the 10T SRAM is combined, the 10T SRAM can be directly used for copying the data, an ALU is not needed when the data is copied, and the speed of copying the data is obviously improved.

An integrated circuit device includes a plurality of static random access memory (SRAM) cells, a first bit line, a capacitor, a write driver transistor, and a negative voltage generator circuit. The first bit line is coupled with a column of the SRAM cells, wherein the first bit line extends substantially along a first direction. The capacitor includes a first electrode and a second electrode spaced apart from the first electrode. The first electrode has at least one first metal line extending substantially along the first direction, and a length of the at least one first metal line is less than a length of the first bit line in a top view. The write driver transistor is coupled between the first bit line and the first electrode of the capacitor. The negative voltage generator circuit is coupled to the second electrode of the capacitor.

This application provides a storage circuit, a storage chip, and an electronic device. The storage circuit includes a sub-read circuit, read bit lines, at least one read auxiliary unit, and multiple static random access memory (SRAM) cells. The read bit lines are connected to the sub-read circuit, the at least one read auxiliary unit, and the multiple SRAM cells. The sub-read circuit performs read operations through the multiple SRAM cells. The read auxiliary unit is obtained by updating the circuit connections of the SRAM cells and is used to adjust the potential of the read bit lines. This not only improves the success rate of reading 1 operations and accelerates the speed of reading 0 operations, but also avoids excessive area overhead in the storage circuit.

Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Integrated circuit structure, comprising: an SRAM cell (10) (SRAM: static random access memory), comprising: a first pull-up MOS device (PU-1) (MOS: metal oxide semiconductor) and a second pull-up MOS device (PU-2), and a first pull-down MOS device (PD-1) and a second pull-down MOS device (PD-2), forming inverters cross-locked to the first pull-up MOS device (PU-1) and the second pull-up MOS device (PD-2); an elongated contact (54) located over and electrically connected to a source of the first pull-down MOS device (PD-1); a first metal layer (M1) containing a bit line and a CVdd line; a first CVss contact island (52B) overlapping the elongated contact (54) and is electrically connected to this, wherein the first CVss contact island (52B) has a part in the SRAM cell (10) which has a first length and a first width,which are smaller than a second length and a second width of the SRAM cell (10), wherein the SRAM cell (10) has a first boundary (10A) and a second boundary (10B) that are parallel to each other, and a third boundary (10C) and a fourth boundary (10D) that are parallel to each other, and the first CVss contact island (52B) overlaps the first boundary (10A) and the fourth boundary (10D) but does not extend beyond the second boundary (10B) and the third boundary (10C); a first word line (50) having a first longitudinal direction, wherein the first word line (50) extends from the third boundary (10C) to the fourth boundary (10D), wherein the first word line (50) and the first CVss contact island (52B) are located in a second metal layer (M2) above the first metal layer (M1), and wherein the first word line (50) forms a strip portion (50A) and has a protruding part (50B),which is connected to a part of a first side wall of the strip section (50A) in the first longitudinal direction and extends in a direction perpendicular to the first longitudinal direction, wherein the projecting part (50B) extends in the direction of the first boundary (10A) and is spaced from the first boundary (10A) and further extends from the third boundary (10C) in the direction of the fourth boundary (10D) and is spaced from the fourth boundary (10D), wherein the CVss contact island (52B) and the projecting part (50B) are spaced apart by a distance S1 so that they do not electrically short-circuit, wherein the word line has a width W1 and the projecting part (50B) has a width W2 and wherein 0.1 <= W2 / W1 <= 0.5,wherein the width of the first word line (50) is increased by the projecting part (50B) and thereby the resistance of the first word line (50) is reduced; and a first CVss line (58) in a third metal layer (M3) above the second metal layer (M2), wherein the first CVss line (58) is electrically connected to the first CVss contact island (52B) and has a second longitudinal direction that is perpendicular to the direction of the first longitudinal direction.

An integrated circuit (IC) includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The IC further includes n-type source / drain (S / D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S / D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S / D contacts physically contacting each of the p-type S / D epitaxial features and the second portion of each of the first and the second hybrid fins.

The present invention relates to a bitline leakage current compensation and BCAM multiplexing circuit and compensation method. The bitline leakage current compensation and BCAM multiplexing circuit includes a storage array composed of multiple SRAM cells and a compensation module. Each column of SRAM cells shares a bit line and constitutes a basic storage module. The compensation module includes eight PMOS transistors P0 to P7 and two compensation capacitors C1 and C2. The drains of P0, P1, P2, and P3 serve as the four input terminals of the compensation module and are connected to the four bit lines of the storage module. The upper plate connection terminals out and outb of C1 and C2 serve as the result output terminals when the storage module performs normal read and write operations. The lower plate connection terminals bout and boutb of C1 and C2 serve as the result output terminals when the storage module performs BCAM addressing operations. The compensation module of the present invention can reduce addressing or reading errors caused by leakage current.

The present invention relates to a CMOS SRAM cell having a trench structure and, more specifically, to a CMOS SRAM cell having a trench structure, the CMOS SRAM cell being manufactured using a vertical MOSFET of a trench structure having a gate, a source, and a drain that form a vertical structure, such that there is a current flow in an active region between trench gate electrodes and vertical source and drain regions, and thus being capable of exhibiting various advantages with respect to density, operating frequency, noise margin, current handling capacity, power consumption, and manufacturing steps, compared to a conventional CMOS SRAM cell having a planar structure.

Fast low leakage SRAM cells, e.g., for digital display systems, are disclosed herein. In one embodiment, a bit memory circuit includes a latch coupled between a supply voltage and ground, and first to fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the supply voltage based at least in part on a first control signal. The second transistor may selectively couple an input of the first inverter to ground based at least in part on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the supply voltage based at least in part on the second control signal. The fourth transistor may selectively couple an input of the second inverter to ground based at least in part on the first control signal.