537 results about "Cross coupled" patented technology

The invention relates to the technical field of servo control, in particular to a high-precision current closed-loop control system and method for a servo driver, and the method comprises the steps: collecting three-phase current, rotor position, winding temperature and bus voltage, and constructing a state data set; constructing a parameter identification model fusing physical prior and an attention mechanism, deducing inductance and flux linkage parameters influenced by temperature, saturation and cross coupling, and correcting a motor model in real time; the correction parameters are injected into an FOC decoupling and feedforward link, and a self-adaptive PI regulator is linked to set the gain of a current loop on line; calculating a d-q axis voltage command according to the update model to respectively control excitation and torque components; an extended state observer is introduced to estimate load abrupt change and parameter disturbance, feed-forward compensation is carried out, and three-phase PWM is generated through anti-Parker and SVPWM; and an inverter nonlinear compensation model of a dead zone and switch delay is constructed, PWM is pre-distorted and output to a power device, and robust and low-ripple current closed-loop control of the servo motor is realized.

The invention provides a wide-angle scanning dual-circularly-polarized phased-array antenna unit, which belongs to the field of dual-circularly-polarized antennas and comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially stacked, the antenna radiator is arranged on the side, away from the second dielectric layer, of the first dielectric layer, the antenna radiator comprises four radiation patches, each radiation patch comprises a metal patch and a loading branch knot, and each metal patch is provided with a slotted structure; the first metal ground layer is clamped between the first dielectric layer and the second dielectric layer, and a cross coupling gap and a first coupling gap and a second coupling gap which are perpendicular to each other are formed in the first metal ground layer; the U-shaped feeder line is clamped between the second dielectric layer and the third dielectric layer, and two ends of the U-shaped feeder line are respectively connected with a coaxial feed column penetrating through the third dielectric layer; the second metal ground layer is arranged on the side, away from the second dielectric layer, of the third dielectric layer; an array is also provided; the problem that a traditional circularly polarized antenna is narrow in impedance bandwidth and limited in polarization is solved.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention provides a voltage stability control method for a multi-output switching power supply, which comprises the following steps of: sampling a main output channel in real time to obtain a voltage signal; the voltage signal is processed through a wide bandwidth error amplifier, a main channel adjusting signal is generated, and the main channel adjusting signal is used for driving a main power switch device; receiving an input voltage fluctuation frequency band of an auxiliary channel, a load current transient change gradient and a frequency spectrum coupling characteristic of a main channel adjusting signal through a dynamic prediction model, and generating an auxiliary channel adjusting signal with a phase lead compensation characteristic; a cross coupling active offset mechanism is constructed, time domain-frequency domain characteristics of coupling interference are extracted through a high-precision differential detection circuit, amplitude-frequency adjustable reverse correction signals are generated in real time through an adaptive compensation algorithm and injected into control nodes of an auxiliary output channel, and dynamic decoupling and ripple suppression are carried out. According to the method, high-stability control of multi-channel voltage under all working conditions is realized, and the dynamic response speed and the anti-interference capability are improved.

The present invention belongs to the technical field of parameter identification for permanent-magnet synchronous motors. Disclosed are a parameter identification method and apparatus for a permanent-magnet synchronous motor, and a storage medium and a device. The method comprises: using a variable step-size feedback neural network algorithm to solve a voltage equation and a d-q axis current discrete state equation, which take cross-coupled inductance into consideration, of a permanent-magnet synchronous motor in a dq coordinate system, so as to obtain intermediate parameters generated in the process of constructing the d-q axis current discrete state equation; and performing calculation on the basis of the intermediate parameters, so as to obtain the stator resistance, the d-axis inductance, the q-axis inductance, the cross-coupled inductance and the permanent-magnet flux linkage of the permanent-magnet synchronous motor, and thereby completing parameter identification. The present invention takes cross-coupled inductance into consideration and uses the variable step-size feedback neural network algorithm, such that the computational load is extremely small, the degree of complexity is reduced, rapid and effective identification can be realized, and errors can be reduced; in different convergence time periods, the algorithm adjusts the step size on the basis of the magnitude of steady-state errors, such that identification results approach stable values more quickly, thereby improving the speed and stability of convergence.

An electronic device may include wireless circuitry. The wireless circuitry can include a first input transistor, a first capacitance neutralization having a source terminal coupled to a tail node, and a second order intermodulation generation circuit configured to produce second order intermodulation signals at the tail node. The wireless circuitry can further include a second input transistor and a second capacitance neutralization transistor having a source terminal coupled to the tail node. The first and second capacitance neutralization transistors can be cross-coupled with the input transistors. A fixed or adjustable current source can be coupled to the tail node. The second order intermodulation generation circuit can include a transistor biased in a weak inversion mode.

A multi-port memory cell has a write-only cell and a buffered read port. The write-only cell has cross-coupled inverters and transmission gates to write bit lines. Each transmission gate has n-channel and p-channel transistors in parallel that both turn on during writing but remain off for reading. A node in the cross-coupled inverters is applied to a gate of a buffer transistor that has a channel in series with a channel of a read pass transistor to a read bit line. The buffered read port can be an inverter and a transmission gate, or can have p-channel and n-channel buffer and pass transistors in a four-transistor stack. The number of p-channel and n-channel transistors can be equal for use in a standard-cell or macro library layout, and the standard-cell logic power supply can be used for the memory cells even for ultra-low supply voltages.

An electronic device may include a display that generates light for an optical system that redirects the light towards an eye box. The optical system may include a waveguide, a non-diffractive input coupler, a cross coupler, and an output coupler. The cross coupler may expand the light in a first direction. The cross coupler may perform an even number of diffractions on the light and may couple the light back into the waveguide at an angle suitable for total internal reflection. The output coupler may expand the light in a second direction while coupling the light out of the waveguide. The cross coupler may include surface relief gratings or holographic gratings embedded within the waveguide or formed in a separate substrate. The optical system may direct the light towards the eye box without chromatic dispersion and while supporting an expanded field of view and optical bandwidth.

The invention relates to the technical field of integrated circuits, in particular to a capacitive coupling type current steering digital-to-analog converter for transmitting switch control signals, which comprises a current steering unit and a switch signal control unit. The switching signal control unit comprises two capacitance coupling type level shifters; the current steering unit comprises a current source and transistors M1-M4, source electrodes of the transistors M1-M4 are connected with one end of the current source, and the other end of the current source is grounded; drain electrodes of the transistors M1-M2 are connected to form a positive output signal, and drain electrodes of the transistors M3-M4 are connected to form a negative output signal; the grid electrodes of the transistors M1-M2 are connected with a first capacitive coupling type level shifter, and the transistors M3-M4 are connected with a second capacitive coupling type level shifter; the on and off of the transistors M1-M4 are controlled through the two capacitance coupling type level shifters; the cross coupling unit is introduced to assist in transmitting switch control signals, and the dynamic performance of the digital-to-analog converter is improved.

A memory device includes a storage element formed of a first inverter and a second inverter cross-coupled to each other, a first transistor having a first conductive type, and connected between a first bit line and a first storage node of the storage element; a second transistor having the first conductive type, and connected between a second bit line and a second storage node of the storage element; and a third transistor having a second conductive type opposite to the first conductive type, and connected between the first storage node and a third bit line.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a low-noise voltage-controlled oscillator circuit which comprises a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration and a source electrode following low-noise bias circuit with digital calibration, the cross-coupled amplifier array is composed of a plurality of units, and the source electrode of the cross-coupled amplifier array suppresses low-frequency noise through a resistance-capacitance feedback network and receives a digital amplitude calibration signal so as to dynamically adjust the number of working units and stabilize the output amplitude; the amplitude self-calibration loop consists of digital logic and a peak detector; the switched capacitor unit array is provided with stable direct-current bias; and a wide linear variable capacitor array driven by the stepped bias voltage. Through deep fusion of digital and analog technologies, the phase noise is remarkably reduced, the linear tuning range is widened, the amplitude stability is ensured, the power consumption is reduced, and the method is particularly suitable for a high-performance radio frequency communication chip of the Internet of Things.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The invention discloses a device and method for improving synchronous tracking precision of a double-permanent-magnet synchronous motor motion platform servo system, and belongs to the technical field of numerical control. Synchronous control of the double permanent magnet synchronous motors is realized by using the preset performance cross coupling controller; estimating system lumped disturbance through a self-adaptive extended state observer, and inhibiting the system lumped disturbance by adopting a novel sliding mode maker; according to the novel sliding mode controller, an exponential function term and a power function term are added in the reaching law to enable the system state to converge rapidly, when the system state is close to a sliding mode surface, the exponential term in the reaching law is attenuated rapidly, the improved power function term plays a leading role, convergence stagnation caused by premature reduction of the reaching rate is avoided, the adaptability of the reaching rate is enhanced, and the control precision is improved. The arrival time is reduced. A sigmoid function is used for replacing a switching function, continuous control input is achieved, and high-frequency buffeting is weakened. And the high-performance Hall sensor and the incremental encoder are adopted, so that the signal acquisition precision is improved.

The invention discloses a dual three-phase permanent magnet synchronous motor harmonic suppression method based on virtual back electromotive force identification, and the method comprises the following steps: S1, building a driving system model of a DTP-PMSM; s2, constructing a harmonic model of the DTP-PMSM, analytically decomposing the nonlinear characteristic and the non-sinusoidal counter electromotive force of the inverter into dq and dqz subspaces, introducing the concept of virtual harmonic counter electromotive force, and unifying the nonlinearity of the inverter, the space harmonic counter electromotive force and cross coupling terms related to harmonic current into a single expression form; and S3, developing an identification principle based on current mapping, including amplitude and phase estimation, gain design and delay compensation, so as to estimate the amplitude and phase deviation of the virtual harmonic back electromotive force on line to realize harmonic suppression and avoid a complex algorithm and a large amount of parameter adjustment. According to the method, the operation effect is good in a wide rotating speed range, and meanwhile complex algorithms and a large amount of parameter adjustment are avoided.

An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

The invention provides a band-gap reference circuit without an operational amplifier, and the circuit comprises a positive temperature coefficient generation module which generates negative feedback current with a positive temperature coefficient through a cross coupling structure composed of four transistors; the reference voltage generation module copies the output of the positive temperature coefficient generation module through a mirror image so as to generate a positive temperature coefficient voltage on an internal resistor and superposes a negative temperature coefficient voltage so as to obtain a band-gap reference voltage with a zero temperature coefficient; the starting module is connected with the output of the positive temperature coefficient generation module and injects current into the reference voltage generation module at the initial stage of establishing the band-gap reference voltage; and the current output module copies the output of the positive temperature coefficient generation module through a mirror image so as to generate zero temperature coefficient output current. An operational amplifier does not need to be introduced, so that extra device noise is not introduced, and the circuit can be widely applied to circuits sensitive to noise, such as phase-locked loops and oscillators.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The invention discloses an omnidirectional wireless electric energy transmission device, and belongs to the technical field of wireless electric energy transmission. The device comprises a regular octahedron framework and a transmitting coil which is continuously and unidirectionally wound along the edge of the regular octahedron framework, and the winding directions of adjacent triangular frameworks are opposite so as to generate an enhanced magnetic field which is matched with a first resonance compensation network and a high-frequency power supply system to work. A receiving end adopts three groups of coil units which are orthogonally arranged in the same plane and are mutually isolated to form a receiving coil, and each group is connected with an independent second resonance compensation network to form a resonance rectification branch. According to the structure, an omnidirectional uniform magnetic field is generated through unique regular octahedron coil arrangement, so that receiving equipment can be efficiently charged at any angle and position in a large range, and the structure has high tolerance to rotation and offset. The planar orthogonal receiving coil can capture more magnetic flux in a three-dimensional space, the transmission efficiency is improved, cross coupling is effectively restrained, and meanwhile the planar orthogonal receiving coil can be conveniently integrated in a mobile phone, a computer and other devices through the flat design.

According to an embodiment, a bootstrap drive circuit for driving a bootstrap switch in a DC-DC converter is proposed. The bootstrap drive circuit includes a non-overlapping circuit, a first and a second capacitor, and a first and a second n-channel transistor. The non-overlapping circuit is configured to receive an input signal, the input signal being a function of a pulse width modulated (PWM) signal, wherein the input signal and the PWM signal are characterized by a first logic level, generate a first control signal from the input signal at a first output terminal of the non-overlapping circuit, the first control signal having the first logic level, and generate a second control signal from the input signal at a second output terminal of the non-overlapping circuit, the second control signal being characterized by a second logic level different from the first logic level.

A dual tank LC-tuned Voltage Controller Oscillator (LC VCO) comprising a differential pair of cross-coupled transistors (M1, M2, M3, M4) produces a negative impedance by keeping a lower drain swing and a sufficient gate swing. The gate terminals of first and second transistors M1, M2 and third and fourth transistors M3, M4 are separated through a series of two inductors L1, L2 and two cross-coupled capacitors are connected between the drain and gate terminals of cross-coupled transistors to attenuate the output swing. The VCO tank further comprises two R2R Digital to Analog Converters (DAC) to bias both NMOS and PMOS cross-coupled pairs of transistors, to produce a common mode noise.

The invention provides a tool state monitoring method, a tool state monitoring model construction method, a tool state monitoring model construction system and electronic equipment. The model construction method comprises the steps of obtaining machining data of a cutter under a normal working condition, wherein the machining data comprises a power signal of a cutter spindle; the power signals are segmented according to the segmentation lines, and the machining time period of the cutter is determined according to the segmentation result; the parting line is used for defining a machining state and a non-machining state of the cutter; extracting characteristic indexes of the processing data in each processing time period; and determining a cutter state monitoring threshold value of each processing period according to the characteristic value of the characteristic index, and constructing a cutter state monitoring model according to the cutter state monitoring threshold value. According to the method, the influence of non-machining period interference and cross-working-condition cross coupling can be effectively eliminated, so that the constructed cutter state monitoring model has higher working condition adaptive capacity, precise evaluation and real-time monitoring of the cutter state are realized, and the accuracy and timeliness of a monitoring result are remarkably improved.

The invention discloses an enhanced power decoupling control method for a virtual synchronous generator, relates to the technical field of virtual synchronous generators, and solves the problems that a systematic analysis method for a resistance-inductance line power coupling mechanism is lacked and a collaborative design framework of a dynamic power decoupling condition and a steady-state power transmission requirement cannot be established in the prior art. According to the method, firstly, a dynamic coupling coefficient is accurately quantified through small signal modeling, then a voltage amplitude compensation mechanism based on virtual impedance is established, steady-state power transmission constraints are embedded into dynamic decoupling conditions, and virtual impedance parameters have the dual functions of eliminating dynamic coupling and guaranteeing steady-state tracking. The method does not depend on ideal working condition assumption, can calculate the optimal virtual resistance and virtual reactance on line according to real-time line parameters and operation working conditions, improves the adaptability of the VSG to a weak power grid resistance-inductance line, effectively inhibits dynamic cross coupling between power, and enhances the frequency support and voltage support capability of the VSG under a complex power grid condition.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

The invention belongs to the technical field of magnetic suspension control, and provides a multi-point cross-coupling suspension control method for a sliding-mode-driven RBF network, and the method comprises the steps: constructing a sliding-mode surface and a radial basis function neural network according to the suspension gap error of a single-point electromagnet, and obtaining a sliding-mode-driven RBF neural network control method for the single-point electromagnet; independent sliding mode driving RBF neural network control is respectively carried out at four electromagnets, gap and speed dual cross coupling terms are designed according to errors among points in a four-point suspension frame, error terms are superposed in control input, and finally a sliding mode surface driving RBF controller combined with cross coupling control is formed. According to the method, the tracking performance of the target gap and the synchronization performance between the suspension points are improved, stable suspension of the suspension frame is achieved, and it is verified that the method still has a remarkable control effect under the operation conditions that the track is not smooth and faults occur.

The invention discloses a unit cascade type motor speed regulation control compensation method and system, relates to the technical field of motor control, and solves the problems that during motor operation, temperature rise, magnetic saturation or load sudden change can cause dynamic parameter change, parameters are not identified in real time, the reluctance torque compensation error is large, and the stability of the motor is poor. And the motor speed regulation control compensation accuracy is influenced. The reluctance torque is strongly correlated with the difference value of the Ld-Lq, and the difference value of the Ld-Lq is influenced by the motor design and the working condition. The RLS can accurately quantify the nonlinear part of the reluctance torque through online identification of the Ld-Lq difference value, and the limitation of a traditional table look-up method or offline calibration is avoided. Through cross coupling of a d-q axis current loop, the RLS can decouple mutual influence among parameters by identifying inductance parameters at the same time, and the bandwidth of the current loop is improved; meanwhile, the temperature rise of the motor can cause inductance drift, and the compensation amount is adjusted by continuously monitoring the inductance change, so that the torque attenuation caused by the temperature rise is avoided.

The invention provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, and relates to the technical field of circuits, the frequency divider comprises a master latch and a slave latch; each of the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross coupling pair and a load resistor pair; the current source is connected with the first current branch and the second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, the first current branch is provided with a first switching tube, and the second current branch is provided with a second switching tube and an adjustable resistor unit which are connected in series. Thus, the adjustable resistor unit is configured on the second current branch, association between the resistance value of the adjustable resistor unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustability, and frequency requirements of different scenes are met by adjusting the resistance value of the adjustable resistor unit and adjusting the self-resonant frequency of the frequency divider.

According to embodiments, a structure for a qubit architecture is presented. The structure can include a plurality of qubits. The structure can include a plurality of couplings between each qubit. The couplings are arranged based on a relationship between each qubit and its placement on a torus. The couplings of each qubit include couplings to four nearest neighbor qubits on the torus and couplings to two cross-coupled qubits based on a definition of a bivariate bicycle code and a set of parameters. Methods for using and manufacturing the qubit architecture are also presented.

The invention discloses a low-noise low-power-consumption cascade input comparator which comprises a pre-amplification stage and a latch stage, the pre-amplification stage is used for amplifying a pair of differential signals input from the outside, the amplified differential signals are obtained and output to the latch stage, and the latch stage is used for latching the amplified differential signals. The latch stage is used for keeping a latch state and outputting a differential comparison result, the pre-amplification stage is used for inputting a pair of differential signals by arranging a three-stage cascade structure consisting of three pairs of input geminate transistors, and is used for preventing all connection nodes of the pre-amplification stage and the latch stage from being completely discharged to the ground by arranging a pair of cross coupling geminate transistors, so that charge storage is realized; the circuit has the advantages of low input reference noise, no consumption of a large amount of extra area and power consumption, small area and low power consumption.