178 results about "MESFET" patented technology

An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.

A monolithic electronic device includes a substrate, a semi-insulating, piezoelectric Group III-nitride epitaxial layer formed on the substrate, a pair of input and output interdigital transducers forming a surface acoustic wave device on the epitaxial layer and at least one electronic device (such as a HEMT, MESFET, JFET, MOSFET, photodiode, LED or the like) formed on the substrate. Isolation means are disclosed to electrically and acoustically isolate the electronic device from the SAW device and vice versa. In some embodiments, a trench is formed between the SAW device and the electronic device. Ion implantation is also disclosed to form a semi-insulating Group III-nitride epitaxial layer on which the SAW device may be fabricated. Absorbing and/or reflecting elements adjacent the interdigital transducers reduce unwanted reflections that may interfere with the operation of the SAW device.

A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed on the main semiconductor region, preferably between gate and drain, is a Schottky electrode electrically coupled to the source. The Schottky electrode provides a Schottky diode in combination with the main semiconductor region. A current flow is assured from Schottky electrode to drain without interruption by a depletion region expanding from the gate.

A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.

A series of gate drive circuits for MESFETs are provided. The gate drive circuits are intended to be used in switching regulators where at least one switching device is an N-channel MESFET. For regulators of this type, the gate drive circuits provide gate drive at the correct voltage to ensure that MESFETs are neither under driven (resulting in incorrect circuit operation) nor over driven (resulting in MESFET damage or excess current or power loss).

The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.

A main semiconductor region of semiconducting nitrides is formed on a silicon substrate via a buffer region of semiconducting nitrides to provide devices such as HEMTs, MESFETs and LEDs. In order to render the wafer proof against warping, the buffer region is divided into a first and a second multilayered buffer subregion. The first buffer subregion comprises multiple alterations of a multi-sublayered first buffer layer and a non-sublayered second buffer layer. Each multi-sublayered first buffer layer of the first buffer subregion comprises multiple alternations of a first and a second buffer sublayer. The second buffer sublayers of each multi-sublayered first buffer layer either do not contain aluminum or do contain it in a higher proportion than do the first buffer sublayers. The second multilayered buffer subregion comprises multiple alternations of a first and a second buffer layer. The first buffer layers of the second multilayered buffer subregion are less in aluminum proportion than the fourth buffer layers of the second multilayered buffer subregion.

A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second. The low aluminum proportion of the third buffer sublayer serves to prevent two-dimensional electron gas from generating in the buffer region and hence to make this region sufficiently high in resistance to inhibit current leakage from the HEMTs or MESFETs.

A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the MESFET.

A doubly balanced upconverter mixer includes a local oscillator balun circuit comprising juxtaposed foil elements on opposite sides of an insulated substrate with electrical interconnections between the foil elements. An IF balun circuit also comprises series tuned and parallel tuned foil elements on opposite sides of the substrate in juxtaposition to each other. A diode switching network interconnects the baluns. A local oscillator signal is connected to the foil elements of the local oscillator balun circuit, an RF signal is coupled to one foil element of the IF balun circuit and an IF signal is taken from the other foil element of the IF balun circuit. Another embodiment incorporates MESFET type switches, the gates of which are supplied directly with a symmetrical local oscillator signal. This arrangement eliminates the need for the local oscillator balun.

Switchmode DC—DC power converters using one or more non-Silicon-based switching transistors and a Silicon-based (e.g. CMOS) controller are disclosed. The non-Silicon-based switching transistors may comprise, but are not necessarily limited to, III-V compound semiconductor devices such as gallium arsenide (GaAs) metal-semiconductor field effect transistors (MESFETS) or heterostructure FETs such as high electron mobility transistors (HEMTs). According to an embodiment of the invention, the low figure of merit (FoM), τ_FET, of the non-Silicon-based switching transistors allows the converters of the present invention to be employed in envelope tracking amplifier circuits of wireless devices designed for high-bandwidth technologies such as, for example, EDGE and UMTS, thereby improving the efficiency and battery saving capabilities of the wireless devices.

A rectifier MESFET includes an N-channel MESFET having its gate connected to its source, and at the same current density having a voltage drop lower than the gate Schottky diode. A Schottky diode may be connected in parallel with the N-channel device to provide over current protection. A Zener may also be connected in parallel to provide reverse voltage protection. A second N-channel device may be connected in parallel. The addition of the second N-channel provides two different operational mode: synchronous rectification where the majority of current flows through the low resistance first N-channel device and asynchronous rectification where the majority of current flows through the somewhat higher resistance first N-channel device.

A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed on the main semiconductor region, preferably between gate and drain, is a Schottky electrode electrically coupled to the source. The Schottky electrode provides a Schottky diode in combination with the main semiconductor region. A current flow is assured from Schottky electrode to drain without interruption by a depletion region expanding from the gate.

A method of manufacturing a transistor, typically a MESFET, includes providing a substrate including single crystal diamond material having a growth surface on which further layers of diamond material can be deposited. The substrate is preferably formed by a CVD process and has high purity. The growth surface has a root-mean-square roughness of 3 nm or less, or is free of steps or protrusions larger than 3 nm. Further diamond layers are deposited on the growth surface to define the active regions of the transistor. An optional n+ shielding layer can be formed in or on the substrate, following which an additional layer of high purity diamond is deposited. A layer of intrinsic diamond may be formed directly on the upper surface of the high purity layer, followed by a boron doped (“delta doped”) layer. A trench is formed in the delta doped layer to define a gate region.

A method for fabricating a guard ring structure for JFETs and MESFETs. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. At time the gate trenches are etched, concentric guard ring trenches are also etched. The process used to fabricate the gate p-h junction or Schottky barrier at the bottom of the gate trenches is also used to fabricate the guard ring at bottom of the guard ring trenches. The separation between the guard ring trenches is 1.0 to 3.0 times greater than the separation between the gate trenches.

A first type of merged power MESFET device includes two monolithically integrated MESFETS. The MESFETS share common sources and gates, and are sized so that one MESFET may be used as a power device while the other is used as a current-sense device. A second type of merged power MESFET device includes two monolithically integrated MESFETS. The MESFETS share a common region which serves as the source for one MESFET and the drain for the second MESFET. This allows the two MESFETS to function as the high and low-side switches for a buck or boost regulator. A third type of merged power MESFET device combines the high and low-side switches with a current-sensing device.

The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a delta doped silicon carbide MESFET having a source, a drain and a gate. The gate is situated between the source and the drain and extends into a doped channel layer of a first conductivity type. Regions of silicon carbide adjacent to the source and the drain extend between the source and the gate and the drain and the gate, respectively. The regions of silicon carbide have carrier concentrations that are greater than a carrier concentration of the doped channel layer and are spaced apart from the gate.