262 results about "Depletion region" patented technology

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

Disclosed are a neuron and a neuromorphic system including the same. More particularly, a neuron according to an embodiment of the present invention includes a completely depleted Silicon-On-Insulator (SOI) device whose a depletion region is controlled according to an inputted electrical signal to perform integration and leakage.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The invention discloses a defect detection method and a defect detection device based on a semiconductor structure, and the method comprises the steps: applying a voltage to the semiconductor structure to form a stable depletion layer, recording an initial capacitance value, applying a pulse voltage to the semiconductor structure, and closing the pulse voltage, acquiring multiple groups of capacitance parameters of the capacitor of the semiconductor structure under the multiple groups of time parameters; obtaining a characteristic value and a characteristic temperature through the function relation model, the time parameter and the capacitance parameter; a curve of the characteristic value and the characteristic temperature reciprocal is established, and the capture cross section and the defect energy level of the defect are obtained through curve linear fitting; each group of time parameters comprises a first moment and a second moment, and the difference between the second moment and the first moment of each group of time parameters is an arithmetic progression. According to the method and the device, the uniformly distributed characteristic values are obtained through the multiple groups of time parameters with the arithmetic progression relation, so that a more reliable result can be linearly fitted.

The invention discloses a particle deposition prevention shielding piece for coating equipment, which is arranged in a coating cavity and comprises an annular upper plate and an annular lower plate, and a labyrinth type airflow channel is formed between the upper plate and the lower plate through baffles which are staggered up and down and arranged at intervals; a gap of 0-2mm exists between the outer edge of the shielding piece and the inner wall of the film coating cavity, the cavity wall of the film coating cavity is grounded, and the gap is constructed into an electron depletion region mainly comprising positive charges; according to the utility model, particles entering by mistake are intercepted through the labyrinth type channel, particles escaping along the gap are blocked through the electron depletion region, the pollution frequency of the lower cavity can be greatly reduced, and thus the downtime and the maintenance cost of equipment are reduced; the labyrinth type airflow channel and the electron depletion area are both designed in a non-blocking mode, the labyrinth type airflow channel does not hinder normal conveying of reaction gas, the electron depletion area does not affect lifting of the wafer and the shielding piece, the anti-pollution function is achieved, meanwhile, the technological rhythm of existing coating equipment is completely adapted, and the main body structure of the equipment does not need to be changed.

Glass-based substrates have a depletion layer extending from a first major surface to a first depth from 300 nanometers to 10.0 micrometers. The depletion layer is depleted in one or more alkali metal oxide, alkaline earth metal oxide, alumina, or combinations thereof relative to a bulk. In aspects, the glass-based substrates can exhibit a porosity less than or equal to 1.0% for the first major surface and / or a cross-section perpendicular to the first major surface. In aspects, the glass-based substrates can exhibit one or more of a total reflectance from 0.1% to 2.0%, a total transmittance from 94% to 100%, a scattering from 0.1% to 5.0%, or a combination thereof. Methods of treating a glass-based substrate includes contacting the glass-based substrate with treatment solution maintained at 80°C to 180°C for from 1 hour to 168 hours to form the depletion layer.

Some embodiments of the disclosure provide an apparatus comprising a memory cell array region, and a peripheral region including a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor. The SOI CMOS transistor pair includes a buried oxide (BOX) layer in a semiconductor substrate, and an SOI layer on the BOX layer. The SOI layer has a thickness such that a depletion layer when formed in the SOI layer fills the SOI layer between a gate and the BOX layer and between source / drain regions.

The application belongs to the technical field of power semiconductors, and particularly relates to a GaN power device with multiple bias signals controlling multiple islands. The application increases multiple islands on the surface of an AlGaN barrier layer on the basis of a PGaN gate enhancement GaN HEMT device structure, and controls the multiple islands by a bias circuit. The normal turn-on and turn-off of the device are the same as those of the PGaN gate enhancement GaN HEMT, and due to the existence of P islands, the depletion region can be effectively expanded, thereby improving the device voltage resistance, so that the application has an improvement in voltage resistance compared with the conventional PGaN gate enhancement GaN HEMT device. The bias circuit is controlled by the dynamic change of the density or concentration of traps, electrons and holes, the multiple islands controlled by digitalized bias can inject carriers into the device, and the dynamic compensation of charges in the working of the device is realized through controllable carrier injection and trap capture, thereby achieving the effect of inhibiting dynamic on-resistance degradation.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

The invention discloses a p-channel gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The p-channel gallium nitride transistor comprises a substrate; the barrier layer and the p-type gallium nitride layer are located on one side of the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; the p-type gallium nitride layer comprises a first groove, and a first bulge and a second bulge which are positioned on two opposite sides of the first groove; the ratio range of the thickness L1 of the groove bottom of the first groove to the thickness L2 of the p-type gallium nitride layer at the first bulge and / or the second bulge is 1 / 14 < = L1 / L2 < = 3 / 14; a depletion layer located in the first groove; the depletion layer comprises a titanium metal layer and a titanium nitride layer which are laminated, and the titanium nitride layer is located between the titanium metal layer and the p-type gallium nitride layer; the source electrode and the drain electrode are located on the sides, away from the substrate, of the first protrusion and the second protrusion respectively; the grid electrode is located in the first groove and located on the side, away from the p-type gallium nitride layer, of the depletion layer. The stability and the electrical performance of the transistor are improved.

An article that includes a substrate with a first surface and a second surface and that has a bulk region and a surface modified region, the bulk region being integral with the surface modified region, and the surface modified region being at the first surface of the substrate. The bulk region including a higher concentration of at least one alkali than the surface modified region, and where a metal coating is disposed on the first surface of the substrate.

Aspects provide a device comprising: a substrate doped to form a first well; a first deep trench etched in the substrate; a dielectric in the first deep trench; a first conductor within the dielectric in the first deep trench and biased to create a first depletion region in the substrate proximate the first deep trench, wherein the substrate forms a bottom electrode of a first deep trench isolation varactor and the conductor in the first deep trench forms a top electrode of the first deep trench isolation varactor; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the first deep trench isolation varactor; and a fluid property measurement circuit operable to determine a change in the capacitance of the first deep trench isolation varactor and output a fluid property signal.

The invention relates to the technical field of variable capacitors, and discloses a grid-controlled semiconductor depletion layer modulation vacuum variable capacitor and a preparation method thereof, and the capacitor comprises an upper electrode which is made of high-purity oxygen-free copper and has a rounding edge structure; the lower electrode is made of oxygen-free copper and also serves as a mechanical support and a heat sink; the vacuum insulating layer is arranged between the upper electrode and the lower electrode; the semiconductor layer is N-type monocrystalline silicon, the thickness of the semiconductor layer is 200 micrometers, the resistivity of the semiconductor layer is 4-6, and impurity concentration of the semiconductor layer is 4-6. According to the invention, the high-voltage-withstanding vacuum gap capacitor and the semiconductor depletion layer capacitor based on MOS gate voltage regulation and control are connected in series and integrated, so that the single device has high-voltage insulation and rapid electric regulation capabilities at the same time creatively; the capacitance value can be continuously and accurately adjusted in the order of tens of nanoseconds to microseconds only by applying a small-amplitude low-voltage signal.

To improve the degree of freedom in controlling the depletion layer. [Solution] The semiconductor device comprises a channel stopper region of a first conductivity type formed on the surface of the drift layer in the termination region, a first termination trench formed in the drift layer in the termination region, a plurality of termination electrodes provided within the first termination trench surrounded by a first termination insulating film, and a channel stopper electrode provided on the upper surface of the drift layer in an electrically connected state to the channel stopper region and the termination electrodes, wherein the plurality of termination electrodes include a first termination electrode and a second termination electrode.

The application discloses a deep trench isolation structure and a manufacturing process method thereof. The deep trench isolation structure comprises the following steps: a first conductive type substrate is provided; a second conductive type injection layer is formed on the substrate; a second conductive type deep well is formed on the injection layer; a shallow trench isolation structure is formed on the surface of the deep well; a second conductive type well region is formed outside the shallow trench isolation structure; a deep trench is formed in the shallow trench isolation structure by etching; and a segmented filling material is filled in the deep trench. The lower part of the deep trench is filled with silicon oxide, and the upper part of the deep trench is filled with polysilicon. The filling material in the deep trench is divided into two segments with different materials. The lower part of the deep trench is filled with silicon oxide, and the upper part of the deep trench is filled with polysilicon. The DTI polysilicon bottom is shortened to below the injection layer by further optimizing the structure. The DTI polysilicon bottom can pull up a higher peak electric field in the depletion region, thereby improving the breakdown voltage of the device.

The embodiments of the present disclosure disclose a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate, a gate electrode on the substrate, source-drain doped regions on the substrate on both sides of the gate electrode, a contact plug on the substrate, a bottom of the contact plug being electrically connected with the source-drain doped regions, and an isolation layer in the source-drain doped regions, the isolation layer being below the contact plug, an upper surface of the isolation layer being higher than a lower surface of the source-drain doped regions, and a material of the isolation layer comprising an insulating material. By introducing an insulating layer between the contact plug and the lower surface of the source-drain doped regions, a depletion layer generated at a junction interface between the source-drain doped regions and the substrate is blocked, the distance between the depletion layer and the contact plug is increased, and thus the junction interface leakage can be reduced without affecting the current conduction path of the device.

A disclosed electron source includes: (A) a graphene layer having an electron emission area on a surface of the graphene layer; and (B) a p-type semiconductor layer that is in direct contact with the graphene layer and forms a Schottky junction with the graphene layer. In this way, the electrons are accelerated in the depletion layer in the p-type semiconductor layer. Moreover, unlike the MIS type electron source, since the electrons are not accelerated in the insulator layer, the dielectric breakdown caused by a large number of electrons travelling in the valence band of the insulator does not occur, and a long lifespan electron source can be realized. Note that the aforementioned p-type semiconductor layer preferably has a depletion layer having a width of 2.91 nm or more and 30 nm or less.

The invention discloses a grid leakage current model of an MOS device. The expression of the grid leakage current model is shown in the specification. Wherein the gate-substrate voltage Vgb is used as a functional expression of an independent variable, and the functional expression is used for describing the change trend of the gate leakage current Igate along with the gate-substrate voltage Vgb; the functional expression takes gate-substrate voltage Vgb and gate oxide layer thickness tox of the device as independent variables and is used for describing the difference phenomenon of the gate leakage current Igate in an accumulation region and a depletion region; the temperature compensation function takes the current temperature T as an independent variable. According to the scheme, the fitting precision of the gate leakage current in the depletion region can be improved.

The invention discloses a Schottky diode and a preparation method thereof, the Schottky diode comprises a heavily doped N-type substrate layer and a lightly doped N-type epitaxial layer formed on the upper surface of the heavily doped N-type substrate layer, the upper part of the lightly doped N-type epitaxial layer is provided with a groove structure, the groove structure is filled with doped polycrystalline silicon, the doped polycrystalline silicon is polycrystalline silicon doped with P-type impurities, and the doped polycrystalline silicon is doped with P-type impurities. Doped polycrystalline silicon is used as a solid phase diffusion source, and solid phase diffusion is carried out on the doped polycrystalline silicon to diffuse P-type impurities to the lightly doped N-type epitaxial layer, so that P-type regions are formed on the side wall and the bottom of the groove structure. According to the Schottky diode and the preparation method thereof, the P-type region is formed on the side wall and the bottom of the groove structure, the P-type region and the lightly doped N-type epitaxial layer form the depletion region, a good three-dimensional heat dissipation channel is formed, the heat dissipation burden is reduced, the P-type region is formed through solid-phase diffusion, and compared with ion implantation, the junction depth is easier to control.

The application relates to the field of semiconductors and discloses a semiconductor device and a forming method of the semiconductor device. The semiconductor device comprises a substrate, a source region and a drain region, and a halo injection region. The halo injection region comprises a first halo injection sub-region for preventing direct channel penetration and a second halo injection sub-region for adjusting junction leakage current. The first halo injection sub-region covers the bottom and / or side of a preset region, the preset region comprising the source region and / or the drain region, and a depletion layer ends in the first halo injection sub-region. The second halo injection sub-region covers the bottom and / or side of the first halo injection sub-region, and a minority carrier diffusion layer ends in the second halo injection sub-region. The doping concentration of the second halo injection sub-region is greater than that of the first halo injection sub-region. The semiconductor device provided by the application can adjust the interface performance between the substrate and the source region and / or the drain region by setting the halo injection region, and can solve the contradiction between direct channel penetration and pn junction leakage.

The invention discloses a single-photon avalanche detector with high detection efficiency and a preparation method of the single-photon avalanche detector. The single-photon avalanche detector comprises a semi-insulating substrate, an n + InGaAs substrate epitaxial layer, an n + InAlAs substrate epitaxial layer, an i: InAlAs epitaxial multiplication layer, a p + InAlAs charge layer, an InAlAs / InAlGaAs superlattice gradient layer, an InAlGaAs / InGaAs superlattice absorption layer, a p +: InAlAs epitaxial layer and a p +: InP epitaxial layer which are sequentially arranged from bottom to top, the InAlAs / InAlGaAs superlattice gradient layer is arranged in a periodic cycle mode, and the InAlGaAs / InGaAs superlattice absorption layer is arranged in a periodic cycle mode. Compared with the prior art, the quantum efficiency of the device can be improved, the width of a depletion region can be increased, the electric field of the absorption layer is reduced, and the carrier collection efficiency is improved.

A near infrared sensitivity enhanced non-isolated substrate silicon-based single photon avalanche diode is disclosed, comprising a p-well layer (101), a high voltage n-well (102), the p-well layer and the high voltage n-well layer positioned against each other and configured to form a main junction (100) defining an active region (104), the p-well layer comprising a doping according to a doping concentration profile, the p-well layer is configured to have a first double peak in a doping concentration profile of the p-well layer throughout the active region, the first double peak corresponding to a respective p-type doped region, and the high voltage n-well is configured to have a second double peak corresponding to a respective n-type doped region, the second double peak corresponding to a respective p-type doped region, and the second double peak corresponding to a respective n-type doped region. The n-doped region is configured to achieve an n-p-n-p type device junction distribution, whereby further, the p-well layer is lightly doped and configured to obtain a wide depletion region, i.e., at least 1 [mu] m wide, and the high voltage n-well layer is further configured to extend beyond the p-well layer to form a guard ring (103) around the active region.

This application relates to the field of terahertz emission, specifically providing a low-frequency terahertz emitting device and its fabrication and usage methods. The device includes an excitation material, which is a heterojunction formed by a perovskite layer and a high-resistivity silicon layer. It also includes a first metal layer disposed outside the perovskite layer and a second metal layer disposed outside the high-resistivity silicon layer. During fabrication, a perovskite solution is first spin-coated onto the high-resistivity silicon to form a perovskite layer, and finally, the metal layers are deposited by vapor deposition. During use, a femtosecond laser is incident from one side of the perovskite layer, and a voltage is applied between the first and second metal layers. The applied electric field of this application enhances the interfacial band bending and widens the depletion layer, while simultaneously forming a stable potential gradient in the thickness direction. This makes the transient current change smoother, increases the time constant, and reduces the rate of change of the transient current over time, thereby increasing the proportion of the low-frequency terahertz component and achieving enhanced low-frequency radiation.

The invention discloses a Ga2O3 diode adopting an inclined field plate and a NiO heterojunction and a preparation method of the Ga2O3 diode, and the diode sequentially comprises a cathode ohmic contact electrode, an n-type Ga2O3 substrate, an n-type Ga2O3 epitaxial layer, a composite dielectric layer, and an anode ohmic contact electrode located on a p-type oxide layer and a part of the surface of the inclined field plate from bottom to top, the composite dielectric layer comprises a p-type oxide layer and an inclined field plate, the orthographic projection of the inclined field plate surrounds the orthographic projection of the p-type oxide layer in the direction perpendicular to the plane where the n-type Ga2O3 substrate is located, the cross section of the p-type oxide layer is in an inverted trapezoid shape, and the side wall of the junction of the inclined field plate and the p-type oxide layer has an inclined angle. According to the invention, surface leakage current is inhibited by using a depletion region of a pn junction formed by the P-type oxide layer and the n-type Ga2O3 epitaxial layer, and an edge electric field of the anode ohmic contact electrode is dispersed by using the inclined field plate, so that dual homogenization of a bulk electric field and a surface electric field is realized.

A preparation method of a hole heavily-doped InSb photodiode relates to the technical field of semiconductor processes, and specifically comprises the following steps: carrying out Be ion implantation barrier layer deposition on an InSb wafer after surface treatment, placing the InSb wafer deposited with the barrier layer in an ion implanter, and carrying out ion implantation on the InSb wafer; the method comprises the following steps of: performing injection on an InSb wafer by setting parameters of injection energy, injection dose and deflection angle to obtain hole heavily-doped InSb, removing a barrier layer injected on the surface of the InSb wafer through hydrofluoric acid corrosion, depositing an annealing protective film, and annealing in a high-temperature annealing furnace to obtain the hole heavily-doped InSb wafer. Removing an annealing protection film on the surface through corrosion, carrying out surface lactic acid corrosion to remove a damaged layer, and finally preparing the focal plane array of the photodiode through mesa photoetching and etching, surface passivation, window photoetching and etching, electrode photoetching and stripping processes of the InSb wafer. Good ohmic contact between the electrode and InSb is achieved, series resistance of the diode is reduced, and better depletion region distribution is achieved.

An apparatus, system, and method for the manufacturing of an inductor having a high quality factor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include an inductor coil above a surface of the substrate. The apparatus may further include a trench etched in the substrate, a dielectric in the trench, and a conductor within the dielectric in the trench. The conductor may be biased to create a depletion region below the inductor coil.