385 results about "Depletion region" patented technology

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a high-temperature-resistant VDMOS power transistor used in an extreme environment and a preparation method, the high-temperature-resistant VDMOS power transistor used in the extreme environment comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a lower P + layer, a P well layer and an N well layer, side P + layers are formed on the two sides of the single MOS cell and located between the source electrode and the lower P + layer through ion implantation. The side P + layer and the N well layer are distributed in an axial symmetry mode, and the profile of the section formed after the side P + layer and the N well layer are combined is in a shape like a Chinese character'ao '. According to the invention, through the axisymmetric concave deep junction structure formed by the side P + layer and the N well layer, the lateral expansion capability of a depletion region is obviously enhanced, the parasitic resistance of the P well layer is reduced, the conduction path of a parasitic bipolar transistor is blocked by the structure, and the latch-up effect at high temperature is avoided.

The invention discloses a method for characterizing physical properties of a single-layer graphene / semiconductor heterojunction. The method comprises the following steps: providing a physical property model about a single-layer graphene-semiconductor heterojunction, wherein influence factors comprise the change of Fermi level of single-layer graphene after the heterojunction is formed and the influence of an interface state on a formation position of a contact potential difference; extracting heterojunction electrical characteristics by using a Kelvin probe force microscope; the interface layer spacing is obtained; and importing the heterojunction electrical characteristics and the interface interlayer spacing into a physical characteristic model, and analyzing to obtain physical characteristics. According to the new theoretical model and the method for realizing the nondestructive characterization of the physical characteristics of the heterojunction by using the Kelvin probe microscope based on the theoretical model, the influence of the change of the Fermi level of the single-layer graphene and the interface state on the formation position of the contact potential difference is fully considered; key interface physical properties, especially built-in potential and depletion region characteristics which are crucial to device performance, can be accurately analyzed.

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

The invention discloses an ultra-short channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure capable of resisting a short channel effect and a manufacturing process thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the core design is that a side symmetric P layer forms a strong depletion region, and drain induced barrier lowering (DIBL) and threshold voltage drift are directly inhibited; the top P-layer, the combined P-layer, the rectangular P-layer, the long-strip P-layer and the like form an auxiliary depletion region to further compress channel edge electric field distortion and cooperatively strengthen suppression on a short channel effect, so that the problem of performance degradation caused by shortening of the channel length in an ultra-short channel structure is solved, and the device can still keep stable electrical characteristics under the condition of small size.

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

A method of forming a graphene device includes: providing a glass substrate with a blocking layer disposed thereon to form a stack; providing a first electrode and a second electrode; increasing the temperature of the stack to at least 100° C.; applying an external electric field (VP) to the first electrode such that at least one metal ion of the glass substrate migrates toward the first electrode to create a depletion region in the glass substrate adjacent the second electrode; decreasing the temperature of the stack to room temperature while applying the external electric field to the first electrode; and after reaching room temperature, setting the external electric field to zero to create a frozen voltage region adjacent the second electrode.

Disclosed are a neuron and a neuromorphic system including the same. More particularly, a neuron according to an embodiment of the present invention includes a completely depleted Silicon-On-Insulator (SOI) device whose a depletion region is controlled according to an inputted electrical signal to perform integration and leakage.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The invention discloses a defect detection method and a defect detection device based on a semiconductor structure, and the method comprises the steps: applying a voltage to the semiconductor structure to form a stable depletion layer, recording an initial capacitance value, applying a pulse voltage to the semiconductor structure, and closing the pulse voltage, acquiring multiple groups of capacitance parameters of the capacitor of the semiconductor structure under the multiple groups of time parameters; obtaining a characteristic value and a characteristic temperature through the function relation model, the time parameter and the capacitance parameter; a curve of the characteristic value and the characteristic temperature reciprocal is established, and the capture cross section and the defect energy level of the defect are obtained through curve linear fitting; each group of time parameters comprises a first moment and a second moment, and the difference between the second moment and the first moment of each group of time parameters is an arithmetic progression. According to the method and the device, the uniformly distributed characteristic values are obtained through the multiple groups of time parameters with the arithmetic progression relation, so that a more reliable result can be linearly fitted.

The invention discloses an oxide semiconductor plane p / n superstructure and a preparation method thereof. According to the method, a latticed mask is formed on the surface of an oxide thin film based on a photoetching process, O2 atmosphere annealing (100-300 DEG C, 15-40 min) is combined, the local oxygen vacancy concentration of a mask covering area and an exposed area is precisely regulated and controlled, and precise in-situ conversion of a p type (oxygen-rich area) and an n type (oxygen-poor area) in a homogeneous material is achieved. The planar p / n superstructure breaks through the strict limitation of a traditional vertical multi-junction structure on material doping and interface quality, the width of a depletion region is expanded to the micron order through the p / n homojunction arrays alternately distributed in the plane, and the bulk recombination effect of photon-generated carriers is remarkably inhibited. According to the method, an innovative technical route of photoetching-assisted in-situ construction of the planar multi-junction photoelectrode is created, the method has the advantages of interface atomic-scale lattice matching, simple process, high compatibility, accurate and controllable space charge distribution and the like, and a technical foundation is laid for non-assisted solar water decomposition, research and development of self-driven optoelectronic devices and the like.

The invention belongs to the field of semiconductors, and discloses a novel ferroelectric memcapacitor based on an MFIS structure and a preparation method thereof, a substrate of the novel ferroelectric memcapacitor comprises a first doped region and a second doped region, and the doping type of the first doped region is p-type; the insulating layer, the ferroelectric layer and the top electrode layer are arranged on the substrate from bottom to top and cover the first doped region of the substrate; an uncovered area on the surface of the substrate is a second doped area, and the doping type of the second doped area is n type; the bottom electrode layer is located in the second doped region of the substrate and is far away from the first doped region; the channel is located in the second doped region of the substrate and is close to the first doped region; the invention also provides a corresponding preparation method, according to the ferroelectric memcapacitor prepared by using the method, because the semiconductor layer has a PN junction depletion region, the ferroelectric film can be fully overturned by using a band-to-band tunneling mechanism without large voltage, and meanwhile, the capacitance of the depletion region of the PN junction on one side of the semiconductor is adjusted, so that a relatively high capacitance-to-switch ratio is obtained while low power consumption is ensured.

The invention discloses a particle deposition prevention shielding piece for coating equipment, which is arranged in a coating cavity and comprises an annular upper plate and an annular lower plate, and a labyrinth type airflow channel is formed between the upper plate and the lower plate through baffles which are staggered up and down and arranged at intervals; a gap of 0-2mm exists between the outer edge of the shielding piece and the inner wall of the film coating cavity, the cavity wall of the film coating cavity is grounded, and the gap is constructed into an electron depletion region mainly comprising positive charges; according to the utility model, particles entering by mistake are intercepted through the labyrinth type channel, particles escaping along the gap are blocked through the electron depletion region, the pollution frequency of the lower cavity can be greatly reduced, and thus the downtime and the maintenance cost of equipment are reduced; the labyrinth type airflow channel and the electron depletion area are both designed in a non-blocking mode, the labyrinth type airflow channel does not hinder normal conveying of reaction gas, the electron depletion area does not affect lifting of the wafer and the shielding piece, the anti-pollution function is achieved, meanwhile, the technological rhythm of existing coating equipment is completely adapted, and the main body structure of the equipment does not need to be changed.

The embodiment of the invention provides a flexible gas sensor, a preparation method thereof and wearable electronic equipment, and the preparation method comprises the following steps: preparing a single-layer MoS2 film through a chemical vapor deposition method; the preparation method comprises the following steps: preparing a monoclinic phase WO3 nanosheet by a hydrothermal method; transferring the single-layer MoS2 thin film to a flexible substrate; preparing an electrode by using a magnetron sputtering instrument; and spin-coating the monoclinic phase WO3 nanosheet on the single-layer MoS2 thin film, so as to prepare the flexible WO3 / MoS2 gas sensor. The prepared gas sensor is suitable for detection of reducing gas, since the monoclinic phase WO3 nanosheet is spin-coated on the surface of MoS2, more active sites can be provided for gas adsorption, and a surface synergistic effect is generated after an n-n heterogeneous composite structure is formed between the two materials, so that the depletion layer and the conductivity of the single-layer MoS2 film are adjusted, and the gas sensor has a good application prospect. The response capability of the single-layer MoS2 film to ammonia gas is improved, and the method is particularly suitable for detection of low-concentration ammonia gas.

The invention discloses a charge regulation and control method and system for an ultrahigh-voltage planar MOS, and relates to the related field of semiconductor device performance regulation and control, and the method comprises the steps: pre-constructing a reconfigurable depletion layer function in a drift region of a device; state sensing of the reconfigurable depletion layer function is carried out based on a preset time window; performing driving initialization according to the real-time working state, and outputting an initial gate driving behavior; state transition prediction is carried out on the real-time working state, driving behavior matching is carried out after K predicted state features are output, and K transition driving behaviors are output; state tracking is carried out on the reconfigurable depletion layer function, and an update driving behavior is called from the K transfer driving behaviors according to the space-time correlation between a tracking result and the K predicted state features; and controlling the gate drive circuit to execute dynamic impedance switching of the multi-stage resistance path. The technical problem of poor regulation and control precision and adaptability of charge regulation and control of the existing ultrahigh-voltage planar MOS is solved, and the technical effect of improving the precision and adaptability of charge regulation and control is achieved.

The utility model provides a single-photon avalanche diode, a photoelectric detection device and electronic equipment. The single-photon avalanche diode comprises a substrate layer, a first doped region, a second doped region, an isolation region, a first electrode and a second electrode, the first doped region is located above the substrate layer, the second doped region is located above the first doped region, and the net doping type of the first doped region is opposite to that of the second doped region, so that a PN junction is formed between the first doped region and the second doped region, and depletion regions are formed on two sides of an interface of the PN junction; the isolation region is attached to the outer sides of the first doped region and the second doped region in the horizontal direction, and is constructed to at least cover the region between the upper interface of the second doped region and the lower interface of the first doped region in the height direction; the first electrode and the second electrode are configured to apply a reverse bias voltage to the PN junction to form an avalanche region in the depletion region. According to the single-photon avalanche diode, the size of a middle strong longitudinal electric field region cannot be affected when the overall size is reduced.

A switching element having multiple trench-type gate electrodes. The semiconductor substrate comprises: an n-type drift region in contact with a gate insulating film at the bottom and side surfaces of each trench; a p-type body region in contact with the gate insulating film above the drift region; multiple p-type bottom regions arranged directly below the trenches and spaced apart from the gate insulating film; and a p-type connection region connecting each of the bottom regions to the body region. Half the depletion layer extension distance required to deplete the gap between adjacent bottom regions is longer than both the depletion layer extension distance required to deplete the gap between the body region and the lower end of the trench and the depletion layer extension distance required to deplete the gap between the bottom region and the lower end of the trench.

The invention relates to a QWLED of a three-dimensional heterojunction quantum well composite light-emitting layer based on cadmium selenide and lead sulfide quantum dots and a preparation method of the QWLED, and belongs to the field of LED preparation. The QWLED sequentially comprises an electrode layer, an inorganic electron transport layer, a CdSe / PbS three-dimensional heterojunction quantum well composite light-emitting layer, an organic hole transport layer and an ITO glass substrate from top to bottom, and the CdSe / PbS three-dimensional heterojunction quantum well composite light-emitting layer is of a three-dimensional heterojunction quantum well structure formed by compounding wide bandgap cadmium selenide quantum dots and narrow bandgap lead sulfide quantum dots. The CdSe / PbS quantum well composite material prepared by the invention has a three-dimensional depletion region and a three-dimensional heterojunction structure, high quantum efficiency, good optical characteristics and structural stability, and the prepared LED device with the three-dimensional depletion region and the three-dimensional heterojunction quantum well structure has excellent electroluminescent efficiency and external quantum efficiency, and can be used as a light emitting diode device of the three-dimensional depletion region and the three-dimensional heterojunction quantum well structure. And the method has huge application potential in the fields of high-brightness, long-service-life and high-resolution display technology and the like.

The present invention belongs to the field of power semiconductor technology and relates to a lateral enhancement-mode gallium oxide field-effect transistor with an integrated freewheeling diode. When the gate-source voltage is zero, the work function difference between the gate-source metal and the gallium oxide semiconductor depletes the conductive channel, realizing a normally-off enhancement-mode device. During forward conduction, the voltage applied to the gate is greater than the threshold voltage, turning the transistor on; when the source voltage is zero, the work function difference between the source metal and the gallium oxide semiconductor depletes the conductive channel, turning the integrated diode off. During reverse freewheeling, the applied source voltage narrows the depletion region, turning the integrated diode on with a low turn-on voltage; when the source voltage is further increased, a high-concentration electron accumulation layer forms on the channel sidewalls, achieving a low on-state voltage drop. Compared to vertically separated field-effect transistors that need to be packaged into a chip or module with a freewheeling diode, the lateral power device of the present invention is easy to integrate, and the field-effect transistor and integrated diode processes are compatible, which facilitates widespread application in power integrated circuits and reduces parasitic parameters and module volume.

Consistent with the present disclosure, a DDR photodiode is provided on a substrate adjacent to a passive waveguide. In order to efficiently capture light output from the waveguide, the photodiode is coupled to the waveguide with a butt-joint. As a result, the photodiode and the waveguide abut one another such that the dominant mode of light propagating in the waveguide parallel to the substrate is supplied directly to a side of the absorber layer of the photodiode without, in one example, evanescent coupling, nor is a resonant coupler required to supply light to the photodiode. Thus, light is absorbed more efficiently in the photodiode such that the photodiode may have a shorter length. In addition, since substantially all light is input to the photodiode, nearly complete absorption and nearly ideal quantum efficiency can be achieved in a relatively short length. Further, the improved linearity associated with DDR photodiodes is preserved with the exemplary butt joint configurations disclosed herein.

Single-photon avalanche diode (SPAD) and image sensing devices are disclosed. In an embodiment, a single-photon avalanche diode (SPAD) includes: an impurity junction region configured to include a plurality of depletion regions, wherein, each depletion region is an junction formed between a first doped region doped with impurities of a first conductivity type and a second doped region doped with impurities of a second conductivity type; an output node formed above the impurity junction region and in contact with one surface of a substrate; a guard-ring region formed to surround the impurity junction region; and a biasing node spaced apart from the guard-ring region and disposed at one side of the guard-ring region.

Glass-based substrates have a depletion layer extending from a first major surface to a first depth from 300 nanometers to 10.0 micrometers. The depletion layer is depleted in one or more alkali metal oxide, alkaline earth metal oxide, alumina, or combinations thereof relative to a bulk. In aspects, the glass-based substrates can exhibit a porosity less than or equal to 1.0% for the first major surface and / or a cross-section perpendicular to the first major surface. In aspects, the glass-based substrates can exhibit one or more of a total reflectance from 0.1% to 2.0%, a total transmittance from 94% to 100%, a scattering from 0.1% to 5.0%, or a combination thereof. Methods of treating a glass-based substrate includes contacting the glass-based substrate with treatment solution maintained at 80°C to 180°C for from 1 hour to 168 hours to form the depletion layer.

Some embodiments of the disclosure provide an apparatus comprising a memory cell array region, and a peripheral region including a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor. The SOI CMOS transistor pair includes a buried oxide (BOX) layer in a semiconductor substrate, and an SOI layer on the BOX layer. The SOI layer has a thickness such that a depletion layer when formed in the SOI layer fills the SOI layer between a gate and the BOX layer and between source / drain regions.

The application belongs to the technical field of power semiconductors, and particularly relates to a GaN power device with multiple bias signals controlling multiple islands. The application increases multiple islands on the surface of an AlGaN barrier layer on the basis of a PGaN gate enhancement GaN HEMT device structure, and controls the multiple islands by a bias circuit. The normal turn-on and turn-off of the device are the same as those of the PGaN gate enhancement GaN HEMT, and due to the existence of P islands, the depletion region can be effectively expanded, thereby improving the device voltage resistance, so that the application has an improvement in voltage resistance compared with the conventional PGaN gate enhancement GaN HEMT device. The bias circuit is controlled by the dynamic change of the density or concentration of traps, electrons and holes, the multiple islands controlled by digitalized bias can inject carriers into the device, and the dynamic compensation of charges in the working of the device is realized through controllable carrier injection and trap capture, thereby achieving the effect of inhibiting dynamic on-resistance degradation.

The application provides a high-reliability silicon carbide MOSFET integrated with a reverse SBD and a preparation method, which comprises an N-type substrate, an N-type epitaxial layer, a P+shield region, a Schottky contact metal, a source electrode, a gate dielectric, a polysilicon gate, a P-body region, a P+contact region, an N+contact region and a drain; the silicon carbide MOSFET device provided by the application forms a P+shield region with self-regulating electric potential in the device body, protects the gate oxide layer without reducing the conduction capacity of the device, and enhances the blocking capacity of the device; when the device is short-circuited, the PN junction depletion region formed by the P+shield region and the N-type epitaxial layer clamps off the JFET region, reduces the saturation current of the device when short-circuited, and improves the short-circuit capacity of the device.

A termination structure of a super-junction power device has a novel polysilicon resistive field plate at the top of a termination region between a transition region and an edge of the device. By utilizing the regular distribution of potential in the field plate, an additional electric field is introduced at the top of the termination structure to limit the expansion of a non-depletion region and optimize the distribution of charges. The termination structure includes a first doping type epitaxial layer, a second doping type compensation region, a second doping type body region, a second doping type lateral connection layer, a second doping type body contact region, a first doping type source contact region, a gate oxide layer, a passivation layer, a field oxide layer, a gate electrode, a second doping type edge contact region, a polysilicon resistive field plate, a metal layer and the like.

The invention discloses a p-channel gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The p-channel gallium nitride transistor comprises a substrate; the barrier layer and the p-type gallium nitride layer are located on one side of the substrate; the p-type gallium nitride layer and the barrier layer form a hole heterojunction structure; the p-type gallium nitride layer comprises a first groove, and a first bulge and a second bulge which are positioned on two opposite sides of the first groove; the ratio range of the thickness L1 of the groove bottom of the first groove to the thickness L2 of the p-type gallium nitride layer at the first bulge and / or the second bulge is 1 / 14 < = L1 / L2 < = 3 / 14; a depletion layer located in the first groove; the depletion layer comprises a titanium metal layer and a titanium nitride layer which are laminated, and the titanium nitride layer is located between the titanium metal layer and the p-type gallium nitride layer; the source electrode and the drain electrode are located on the sides, away from the substrate, of the first protrusion and the second protrusion respectively; the grid electrode is located in the first groove and located on the side, away from the p-type gallium nitride layer, of the depletion layer. The stability and the electrical performance of the transistor are improved.

An article that includes a substrate with a first surface and a second surface and that has a bulk region and a surface modified region, the bulk region being integral with the surface modified region, and the surface modified region being at the first surface of the substrate. The bulk region including a higher concentration of at least one alkali than the surface modified region, and where a metal coating is disposed on the first surface of the substrate.

Aspects provide a device comprising: a substrate doped to form a first well; a first deep trench etched in the substrate; a dielectric in the first deep trench; a first conductor within the dielectric in the first deep trench and biased to create a first depletion region in the substrate proximate the first deep trench, wherein the substrate forms a bottom electrode of a first deep trench isolation varactor and the conductor in the first deep trench forms a top electrode of the first deep trench isolation varactor; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the first deep trench isolation varactor; and a fluid property measurement circuit operable to determine a change in the capacitance of the first deep trench isolation varactor and output a fluid property signal.

The invention relates to the technical field of variable capacitors, and discloses a grid-controlled semiconductor depletion layer modulation vacuum variable capacitor and a preparation method thereof, and the capacitor comprises an upper electrode which is made of high-purity oxygen-free copper and has a rounding edge structure; the lower electrode is made of oxygen-free copper and also serves as a mechanical support and a heat sink; the vacuum insulating layer is arranged between the upper electrode and the lower electrode; the semiconductor layer is N-type monocrystalline silicon, the thickness of the semiconductor layer is 200 micrometers, the resistivity of the semiconductor layer is 4-6, and impurity concentration of the semiconductor layer is 4-6. According to the invention, the high-voltage-withstanding vacuum gap capacitor and the semiconductor depletion layer capacitor based on MOS gate voltage regulation and control are connected in series and integrated, so that the single device has high-voltage insulation and rapid electric regulation capabilities at the same time creatively; the capacitance value can be continuously and accurately adjusted in the order of tens of nanoseconds to microseconds only by applying a small-amplitude low-voltage signal.