36 results about "Depletion region" patented technology

This application relates to the field of terahertz emission, specifically providing a low-frequency terahertz emitting device and its fabrication and usage methods. The device includes an excitation material, which is a heterojunction formed by a perovskite layer and a high-resistivity silicon layer. It also includes a first metal layer disposed outside the perovskite layer and a second metal layer disposed outside the high-resistivity silicon layer. During fabrication, a perovskite solution is first spin-coated onto the high-resistivity silicon to form a perovskite layer, and finally, the metal layers are deposited by vapor deposition. During use, a femtosecond laser is incident from one side of the perovskite layer, and a voltage is applied between the first and second metal layers. The applied electric field of this application enhances the interfacial band bending and widens the depletion layer, while simultaneously forming a stable potential gradient in the thickness direction. This makes the transient current change smoother, increases the time constant, and reduces the rate of change of the transient current over time, thereby increasing the proportion of the low-frequency terahertz component and achieving enhanced low-frequency radiation.

The application provides a building fire alarm, which comprises a semiconductor substrate, a PN junction formed in the semiconductor substrate, a depletion region in the PN junction, a first metal electrode and a second metal electrode in the depletion region of the PN junction, the first metal electrode and the second metal electrode arranged along a first direction and located on the same side of the depletion region, a bias voltage source coupled with the first metal electrode and the second metal electrode, wherein in a non-fire state, the first metal electrode and the second metal electrode are separated by the depletion region, and the circuit is in an off state; in a fire state, the PN junction generates unbalanced carriers, the width of the depletion region is narrowed, an electrically conductive path is formed between the first metal electrode and the second metal electrode, the circuit is connected, and an alarm current is generated. The light / heat signal generated by the fire is converted into the modulation of the width of the depletion region of the PN junction, and the interference of the environment on the alarm is reduced.

This invention provides a trench-type gallium oxide radiation detector and its manufacturing method, belonging to the field of semiconductor device technology. The detector, by designing a rectangular trench structure on the Ga2O3 epitaxial layer of an epitaxial wafer, achieves a more uniform electric field distribution under high reverse bias, effectively avoiding the electric field accumulation effect at the electrode edges and significantly improving the device's breakdown voltage. Simultaneously, the trench structure increases the effective area of ​​the heterojunction, enabling the device to obtain a wider longitudinal depletion region under the same reverse bias, making it easier to achieve full-energy alpha particle deposition, thereby improving the efficiency and energy resolution of radiation detection.

The utility model relates to the technical field of transistor protection, and discloses a high-voltage MOS terminal protection structure with high avalanche tolerance, which comprises a high-voltage MOS device, the high-voltage MOS device is provided with a cellular area and a terminal protection area, the cellular area is also provided with a shield grid used for reducing on-resistance and increasing breakdown voltage, and the terminal protection area is provided with a terminal protection area. The longitudinal section of the shield grid is arranged in a trapezoid shape, the field limiting rings with the gradually-decreased spacing can widen the width of a depletion region, improve the transverse voltage endurance capability of the MOS device, reduce the peak value of an edge electric field, transfer the peak point of an electric field through a slope field plate and eliminate a grid angle distortion electric field, and the shield grid reconstructs the electric field to be distributed in a trapezoid shape and optimizes a longitudinal electric field. Therefore, the breakdown voltage of the MOS device is improved, and the avalanche trigger threshold is remarkably improved; through the design of the drain buffer layer, a large amount of high-energy carrier kinetic energy can be absorbed, the channel thermal shock can be reduced, the local temperature peak value can be reduced, the two metal layers are utilized to assist heat dissipation, double-path heat conduction is realized, and the avalanche tolerance is improved.

The application discloses a Td-WTe2 / 1T'-MoTe2 heterojunction device for room-temperature photoelectric detection and a preparation method and application thereof. The heterojunction device is composed of Td-WTe2 and 1T'-MoTe2, and the two are connected through interlayer van der Waals force in an overlapping area. When light irradiates the overlapping area or a neighboring area thereof, a photo-thermal-electric response can be generated due to the difference in Seebeck coefficients of the two. The application provides a device scheme for realizing room-temperature photoelectric detection by utilizing the difference in thermoelectric properties of two specific materials without relying on a traditional semiconductor depletion region or an asymmetric light irradiation condition, and has the advantages of room-temperature operation, self-power supply, near-infrared response and fast response, and has important value in the field of photoelectric detection.

The application relates to the technical field of sensors, and provides a Hall sensor chip and a manufacturing method. The Hall sensor chip comprises a first type substrate, a first type well region formed in the first type substrate, a first ultrathin tunneling oxide layer and a contact electrode formed on the surface of the first type well region, and a second type heavily doped polysilicon layer formed on the surface of the first ultrathin tunneling oxide layer; the first type substrate, the first ultrathin tunneling oxide layer and the second type heavily doped polysilicon layer constitute a tunneling oxide layer passivation contact structure; the doping type of the first type well region is different from the doping type of the second type heavily doped polysilicon layer, and under the action of the first ultrathin tunneling oxide layer, the surface of the first type well region can form a depletion region. The application utilizes the tunneling oxide layer passivation contact structure to reduce the influence of surface effects on the performance of the Hall sensor and reduce noise caused by interface states.

This invention relates to a planar transport-controlled high-gain avalanche photodetector and its fabrication method, belonging to the field of optoelectronic technology. The invention involves sequentially forming a P-type epitaxial absorption layer, a P-well multiplication layer, an N+ heavily doped layer, a P+ contact region, and a P-well protective layer on a P-type substrate. Through layout design, a predetermined lateral spacing Ls is established between the inner boundary of the P-well protective layer and the outer boundary of the N+ heavily doped layer. This spacing is configured as an electric field control region. By stretching and smoothing the equipotential lines at the edge of the depletion region, a high electric field is guided from the device edge to the central multiplication region, thereby suppressing premature edge breakdown. By controlling the value of Ls between 15 μm and 30 μm, preferably 26 μm, excessive recombination noise can be avoided while maximizing gain, achieving an optimal balance between high gain and low noise. The process of this invention is fully compatible with standard CMOS and is suitable for high-sensitivity detection of weak light signals.

The application discloses a terahertz micro-spectrometer based on a metasurface, and has a working frequency of 1-5 terahertz; from bottom to top, the terahertz micro-spectrometer comprises a substrate, a depletion layer, a two-dimensional material absorption layer and a metal metasurface filter; source and drain electrodes are arranged at two ends of the metal metasurface filter; by applying different voltages to the source, the drain and the gate electrode, the Fermi level of the two-dimensional material absorption layer is controlled; only one metal metasurface filter is needed to perform spectrum coding, and spectrum data of an object can be collected; after decoding by deep learning, the transmittance under different frequencies is output. The spectrometer can reconstruct the spectrum data of the object at the frequency of 1-5 terahertz, and the spectrum resolution can reach 0.00078 terahertz.

The application relates to an SOI semiconductor structure integrated with longitudinal devices and a manufacturing method thereof, the method comprising the following steps: obtaining a wafer, the wafer comprising a substrate, a buried dielectric region on the substrate and a top semiconductor layer on the buried dielectric region; patterning the wafer to expose the substrate of a longitudinal device region; forming a first insulating isolation part on the side of the longitudinal device region; epitaxially forming a first conductive type region outside the longitudinal device region; forming a CMOS device main body in the first device region and a first well region and a first source region in the longitudinal device region through a CMOS process; the first well region is formed in the first conductive type region, and the first source region is formed in the first well region; and forming a first drain region at the bottom of the substrate. The depletion region of the second conductive type can optimize the electric field of the longitudinal device, the area of the depletion region is reduced, and the chip area is reduced.

The embodiment of the present application provides a kind of enhanced GaN power device, it includes: base, including the channel layer of forming electron gas channel and barrier layer;Source and drain, interval arrangement and electrically connected along the first direction by electron gas channel;First depletion layer, is located on the barrier layer and between source and drain, first depletion layer includes first depletion body and second depletion body, second depletion body includes depletion monomer, depletion monomer includes the first end connected with first depletion body and the second end spaced apart from drain, and depletion monomer defines the non-depletable area and depletable area arranged along the second direction by electron gas channel, the second direction intersects with the first direction;First gate, is located on first depletion body and with first depletion body ohmic contact.The embodiment of the present application can not only optimize the electric field distribution when device is in off-state drain high voltage stress to improve breakdown voltage, but also can effectively inhibit the trap effect in device to optimize the dynamic resistance degradation problem of device.

A miniature LED element (100, 200, 300, 400, 500, 620, 711) includes: a mesa (110, 310, 510) comprising a first semiconductor layer (111, 311, 511), an intermediate layer (112, 312), and a second semiconductor layer (113, 313, 513) stacked from top to bottom, wherein the mesa (110, 310, 510) is divided into two steps (110A, 110B; 310A, 310B) on the side of the intermediate layer (112, 312), the intermediate layer (112, 312) comprising: a light-emitting layer (114, 314, 514); and a third semiconductor layer (115, 315). The third semiconductor layer (115, 315, 515) is disposed on the surface of the light-emitting layer (114, 314, 514), wherein the third semiconductor layer (115, 315, 515) is exposed outside the mesa (110, 310, 510) to have an exposed surface (116, 316, 516) relative to the mesa (110, 310, 510); and a Schottky metal layer (130, 330, 520, 630) is disposed on the exposed surface (116, 316, 516), wherein the Schottky metal layer (130, 330, 520, 630) forms a depletion region (191, 391, 521) in the light-emitting layer (114, 314, 514).

The present application discloses a high-sensitivity gallium oxide ultraviolet detector, a manufacturing method therefor, and a use thereof. The high-sensitivity gallium oxide ultraviolet detector comprises an n-type gallium oxide channel layer, a p-type photoresponsive floating gate, a patterned photoresponsive floating gate dielectric layer, a first electrode, and a second electrode; the p-type photoresponsive floating gate is arranged on the n-type gallium oxide channel layer; the patterned photoresponsive floating gate dielectric layer is arranged between the p-type photoresponsive floating gate and the n-type gallium oxide channel layer and is completely covered by the p-type photoresponsive floating gate; the first electrode and the second electrode are arranged on the n-type gallium oxide channel layer, and are in ohmic contact with the n-type gallium oxide channel layer; the concentration of p-type impurities in the p-type photoresponsive floating gate is much higher than the concentration of n-type impurities in the n-type gallium oxide channel layer; the patterned photoresponsive floating gate dielectric layer has a thickness of 10 nm-30 nm and a duty cycle of 10%-90%; and under illumination, the width of a depletion region in the n-type gallium oxide channel layer varies with the duty cycle of the patterned photoresponsive floating gate dielectric layer.

A PN junction, a method for preparing a PN junction, and a modulator are disclosed. The PN junction includes a slab waveguide layer and a plurality of waveguides. The slab waveguide layer includes P-type doped regions and N-type doped regions, and a carrier-depletion region in a shape of S is formed at a boundary between the two types of regions. Each of the plurality of waveguides arranged at intervals includes a P-type doped region and an N-type doped region, and one carrier-depletion region is formed at a boundary between the two regions. Projections of the P-type doped regions, the N-type doped regions, and the carrier-depletion regions of the plurality of waveguides arranged at intervals on a surface of a slab waveguide region basically coincide with projections of corresponding regions of the slab waveguide layer on the surface of the slab waveguide region.

The semiconductor device provided by the embodiments of the present specification has a first trench penetrating a body region and a drift region, the first trench is filled with an isolation layer covering the sidewall of the first trench and a gate structure filled in the remaining first trench; based on the above structure, the flow direction of electrons in the device can be changed from horizontal to vertical during the operation of the semiconductor device, and in the case that the depletion layer provided in the drift region remains unchanged, the space in the vertical direction of the device can be fully utilized, the wafer area required by the device in the horizontal direction is reduced, the size of the device is reduced, and thus the overall cost of the device is reduced. In addition, compared with the conventional lateral channel LDMOS device, the device has better low on-resistance characteristics and can maintain higher withstand voltage performance. Further, the preparation process of the device can be realized based on the DTI process, which is compatible with the BCD process, and compared with the existing LDMOS preparation process, the gate mask plate can be saved, which is conducive to reducing the preparation cost.

This invention relates to the field of semiconductor technology, specifically to a fast soft recovery diode and its manufacturing method. The diode includes an N+ substrate region, an N buffer region, an N- drift region, a P- anode region, and a P+ anode contact region. The N- drift region has a stepped concentration layer, which includes at least two layers, N1 and N2, arranged from bottom to top. The doping concentration of the N2 layer is higher than that of the N1 layer. The surface doping concentration of the P+ anode contact region is greater than that of the P-anode region, and the surface doping concentration of the P-anode region is greater than that of the N2 layer. The N- drift region has a pre-defined depletion layer edge region, which has at least one P+ buried layer located below and / or to the side of the P+ anode region in the vertical direction. This improves the diode's fast soft recovery capability, effectively reduces device conduction losses and switching losses, and suppresses electromagnetic interference, thereby improving the overall system efficiency, power density, and reliability.

The application belongs to the technical field of power devices, and provides a softness modulation type IGBT device and a preparation method and a chip thereof. A softness modulation zone including an N-type diffusion layer and a local carrier lifetime control layer is formed between an N-type field termination layer and an N-type drift layer, the doping concentration of the N-type diffusion layer is less than the doping concentration of the N-type field termination layer, then a front IGBT structure and a front protective layer are formed on the N-type drift layer, so that when the IGBT device is at a lower working voltage, carrier current can be maintained at the end of device turn-off, and turn-off softness is maintained, turn-off time and turn-off loss are reduced, when the IGBT device is at a higher working voltage, the depletion layer of the device can be cut off in the N-type diffusion layer, so that the turn-off current of the IGBT device will not oscillate, and the problems of long current tail, large loss and high risk of overvoltage failure of the current IGBT device under voltage fluctuation are solved.

The present disclosure relates to a thin-film transistor (100, 200, 300, 400, 500, 600, 700, 800) and a display device (900) comprising this transistor, and a manufacturing method thereof. A thin-film transistor (100, 200, 300, 400, 500, 600, 700, 800) is provided, which has an active layer (130), a gate isolation layer (140) on the active layer (130), a gate electrode (150) on the gate isolation layer (140) and a first depletion layer (161) on the gate isolation layer (140), wherein the gate electrode (150) and the first depletion layer (161) are arranged such that they are spaced apart from each other, a section of the active layer (130) overlaps the gate electrode (150) to form a channel section (131) in the active layer (130), and the first depletion layer (161) overlaps another section of the active layer (130).

The application belongs to the technical field of semiconductors, and discloses a double Ga2O3 insertion layer GaN heterostructure ultraviolet phototransistor and a preparation method thereof. The double Ga2O3 insertion layer GaN heterostructure ultraviolet phototransistor structure comprises a substrate layer, a GaN buffer layer, a first i-GaN layer, a first Ga2O3 insertion layer, a second i-GaN layer, a second Ga2O3 insertion layer, a third i-GaN layer, an Al x Ga 1‑x N barrier layer, a p-type layer, a source electrode and a drain electrode arranged on both sides of the upper surface of the barrier layer. The application adopts Ga2O3 as the insertion layer of the GaN heterostructure ultraviolet phototransistor, redistributes the electron concentration of the depletion region, widens the depletion region, reduces the channel electron concentration in the dark state, thereby reducing the dark current of the device; in the light state, there is a strong built-in electric field at the Ga2O3 and GaN interface, which promotes the separation of electron-hole pairs, and the field strength of the barrier layer is larger, thereby enhancing the attraction of the channel to electrons, thereby improving the photocurrent and responsivity of the device.

The application discloses a preparation method of a low-detection-limit ammonia gas sensor, which comprises the following steps: firstly, synthesizing niobium oxide coated cerium oxide nanoparticles through a hydrothermal method; then adding the dried powder into rosin; finally, uniformly applying the rosin containing the sensing material on a ceramic tube and welding the ceramic tube to prepare a gas sensitive sensor. The gas sensitive sensor prepared by the method is composed of two kinds of semiconductor oxides, and the two kinds of oxides have a higher contact area and carrier mobility due to the fact that the niobium oxide is a composite nanoparticle material prepared on the surface of the cerium oxide through in-situ reduction, so that the gas sensitive sensing performance of the material is improved; and the electrons are redistributed to form an electron depletion layer and an electron enrichment layer, so that the material is more likely to react with oxygen to generate oxygen negative ions, thereby improving the gas sensitive performance of the material to VOCs gas.

This application belongs to the field of semiconductor technology and provides a gallium nitride vertical trench MOSFET device, fabrication method, and chip. By forming a first P-type isolation region between the gallium nitride drift layer and the gate insulating layer, and forming multiple second P-type isolation regions between the gallium nitride drift layer and the first N-type doped region, and multiple second P-type isolation regions between the gallium nitride drift layer and the second N-type doped region, the first P-type isolation region and the second P-type isolation region form a depletion region with the gallium nitride drift layer with only one photomask layer. At the same time, the electric field between the source and drain of the device is homogenized, and the electric field is avoided from concentrating on the gate insulating layer, thereby achieving the purpose of improving the breakdown voltage of the gallium nitride vertical trench MOSFET device.

The present invention discloses a high-sensitivity gallium oxide ultraviolet detector, its preparation method and application. The high-sensitivity gallium oxide ultraviolet detector includes an n-type gallium oxide channel layer, a p-type photo-floating gate, a patterned photo-floating gate dielectric layer, a first electrode and a second electrode; the p-type photo-floating gate is disposed on the n-type gallium oxide channel layer, the patterned photo-floating gate dielectric layer is disposed between the p-type photo-floating gate and the n-type gallium oxide channel layer and is completely covered by the p-type photo-floating gate, the first electrode and the second electrode are disposed on the n-type gallium oxide channel layer and form an ohmic contact with the n-type gallium oxide channel layer; wherein, the p-type impurity concentration in the p-type photo-floating gate is much greater than the n-type impurity concentration in the n-type gallium oxide channel layer, the thickness of the patterned photo-floating gate dielectric layer is 10 nm to 30 nm, the duty cycle is 10% to 90%, and the width of the depletion region of the n-type gallium oxide channel layer under illumination changes with the change of the duty cycle of the patterned photo-floating gate dielectric layer.

This invention belongs to the field of semiconductor power device technology and provides an n-channel HEMT depletion-type device with a comb-finger field plate structure to solve the problem of large parasitic capacitance introduced by the field plate structure in the prior art affecting the dynamic performance of the device. This invention employs a comb-finger field plate structure between the gate and drain of the gallium nitride HEMT device, while simultaneously etching the AlGaN barrier layer beneath the comb-finger field plate and filling it with insulating filler. During forward conduction, a two-dimensional electron gas is formed between the unetched AlGaN barrier layer and the GaN buffer layer, serving as a conductive channel. During reverse breakdown, the drift region channel forms a large-area depletion region under the modulation effect of the comb-finger field plate, improving the device's breakdown voltage performance. Furthermore, the comb-finger field plate and the channel have almost no overlap in the vertical direction, significantly reducing the parasitic capacitance introduced by the field plate, enabling the device to maintain good breakdown voltage characteristics while also possessing superior high-frequency characteristics.

This application discloses a variable capacitor and its manufacturing method, comprising: a semiconductor substrate, a first electrode structure, and a gate structure; the semiconductor substrate has an active region, and a first groove is formed on one side of the active region, with an insulating structure disposed in the first groove; at least a portion of the first electrode structure covers the insulating structure in the first groove, and at least a portion of the first electrode structure is opposite to a first sidewall of the first groove; at least a portion of the gate structure is disposed on the active region, and when a gate voltage is applied to the gate structure, a depletion region is formed in the active region, and at least a portion of the active region outside the depletion region serves as a second electrode structure, constituting a variable capacitor with the first electrode structure. In other words, this application forms a first electrode structure on the sidewall of the first groove of the semiconductor substrate, and uses at least a portion of the active region outside the formed depletion region as the second electrode structure, which can adjust the capacitance value, reduce the area occupied by the capacitor structure, effectively reduce costs, and improve the performance of subsequent products.

A micro LED display panel includes a mesa including a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked from top to bottom; a passivation layer formed on a sidewall surface of the mesa; and a Schottky metal layer disposed adjacent to the passivation layer, wherein the Schottky metal layer forms a depletion region in at least the light emitting layer.

A semiconductor device includes a first doped region of a first conductivity type and a second doped region of a second conductivity type different from the first conductivity type. A fusion bonded insulating layer is disposed between the first doped region and the second doped region, wherein the fusion bonded insulating layer forms a tuned depletion layer disposed between the first doped region and the second doped region to form a P-I-N junction.

The application discloses a horizontal structure double-heterojunction insulated gate diamond field effect transistor and a preparation method thereof. The field effect transistor comprises a substrate layer and an N-type gallium oxide layer which are stacked; the N-type gallium oxide layer is sequentially and spacedly provided with a source region, a gate region and a drain region in a horizontal direction; the N-type gallium oxide layer locally forms an N+ high-doped gallium oxide region, and a source electrode is arranged on the upper surface of the N+ high-doped gallium oxide region; the gate region of the N-type gallium oxide layer is sequentially and stackedly provided with a first P-type diamond part, a gate dielectric layer and a gate electrode; and the drain region of the N-type gallium oxide layer is sequentially and stackedly provided with a second P-type diamond part and a drain electrode. The field effect transistor has a double-heterojunction structure, the PN heterojunction of the gate electrode forms a depletion region under zero gate voltage by using a built-in electric field, realizes a normally-off characteristic and optimizes gate control efficiency; and the PN heterojunction of the drain electrode widens a depletion region under a reverse bias, modulates an electric field distribution and significantly improves a breakdown voltage.

This invention discloses a method for embedding nickel oxide (NiO) x A vertical AlN diode with a heterogeneous field-limited ring structure and its fabrication method. From bottom to top, the diode consists of a cathode metal layer (2), an n... + -AlN layer (5), n ‑ -AlN channel layer (4), and p-NiO disposed above the drift layer x Layer (3), anode metal layer (1), and passivation layer (6). This AlN diode has a vertical conductive structure, possessing a large on-state current density and excellent thermal stability. The p-NiO layer at the anode edge of the diode under reverse bias... x The AlN diode, when combined with n-AlN, can form a depletion region with adjustable width, efficiently modulating the electric field distribution in the device, suppressing the electric field accumulation effect at the anode edge, reducing the electric field peak value, and effectively reducing the reverse leakage current while increasing the reverse breakdown voltage. The AlN diode proposed in this invention possesses high voltage withstand capability, low loss, high temperature resistance, and high power characteristics.

This application provides an integrated IC single-photon avalanche diode and a photon detection system, relating to the field of semiconductor technology. The single-photon avalanche diode includes: a substrate; an epitaxial layer formed on the substrate; and a first P-type well, a first N-type well, and a second P-type well formed within the epitaxial layer; the first N-type well and the second P-type well are located on the side of the first P-type well facing away from the substrate and are in contact with the first P-type well; the second P-type well surrounds the first N-type well, and the second P-type well and the N-type well are spaced apart to form a protective ring structure; the first P-type well and the first N-type well form an avalanche PN junction; after incident photons are absorbed in the first P-type well, electron-hole pairs are generated, wherein electrons, as minority carriers, are accelerated in the depletion region of the avalanche PN junction, triggering avalanche multiplication. This application provides a technical solution that uses electrons as avalanche trigger carriers, fundamentally improving the avalanche triggering probability.

The application discloses an LDMOS with a trench gate and an LDMOS device, the LDMOS comprising a trench gate, the trench gate comprising a gate oxide region and a polysilicon region. The polysilicon region comprises an over-liner region and an under-liner region, the under-liner region extending from the upper surface of the LDMOS to the substrate of the LDMOS to form the trench gate. The gate oxide region completely isolates the polysilicon region from the substrate, and the extension depth of the under-liner region to the substrate of the LDMOS is greater than the extension depth of the source region and the drain region to the substrate of the LDMOS. Since the gate is deep into the substrate in the vertical direction, the trench gate of the LDMOS controls the potential of the drift region and the shape of the depletion layer in the off state in three dimensions, shifts the equipotential line from the surface of the device to the body, disperses the local electric field peak on the surface and optimizes the electric field distribution of the drift region, thereby inhibiting the premature breakdown of the surface and improving the withstand voltage margin.

The application provides a metal-oxide semiconductor field effect transistor and a preparation method thereof. The metal-oxide semiconductor field effect transistor comprises an active region and a terminal region. A first field limiting ring and a second field limiting ring are prepared in an epitaxial layer located in the terminal region. The doping concentration of the doping ions in the second field limiting ring is greater than the doping concentration of the doping ions in the first field limiting ring. The junction depth of the second field limiting ring is less than the junction depth of the first field limiting ring. The second field limiting ring is set as a shallow-junction high-doping-concentration field limiting ring relative to the first field limiting ring, and the corresponding field oxide layer is set, so that the fixed charges and movable charges in the terminal region field oxide layer can be effectively shielded, the terminal region depletion layer is prevented from shrinking, the reliability of the device in a high-voltage scene is improved, the device withstand voltage is improved in combination with the first field ring, and the operation performance and operation stability of the device are simultaneously improved.