602 results about "Depletion region" patented technology

The invention belongs to the technical field of power devices, and provides a silicon carbide device structure, a preparation method thereof and a chip, a P-type heavily doped region is isolated from a junction field effect transistor region at an adjacent position by a P-type well region, and an N-type heavily doped region is isolated from the junction field effect transistor region at an adjacent position by the P-type well region. The adjacent junction field effect transistor regions are isolated by the P-type well regions, so that a super-junction-like structure is formed, the junction field effect transistor regions can have donor doping with higher doping concentration, corner arrangement is avoided, a depletion region can be completely closed, the on resistance of the device is reduced, and the reliability of the device is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a high-temperature-resistant VDMOS power transistor used in an extreme environment and a preparation method, the high-temperature-resistant VDMOS power transistor used in the extreme environment comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a lower P + layer, a P well layer and an N well layer, side P + layers are formed on the two sides of the single MOS cell and located between the source electrode and the lower P + layer through ion implantation. The side P + layer and the N well layer are distributed in an axial symmetry mode, and the profile of the section formed after the side P + layer and the N well layer are combined is in a shape like a Chinese character'ao '. According to the invention, through the axisymmetric concave deep junction structure formed by the side P + layer and the N well layer, the lateral expansion capability of a depletion region is obviously enhanced, the parasitic resistance of the P well layer is reduced, the conduction path of a parasitic bipolar transistor is blocked by the structure, and the latch-up effect at high temperature is avoided.

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

The invention discloses a method for characterizing physical properties of a single-layer graphene / semiconductor heterojunction. The method comprises the following steps: providing a physical property model about a single-layer graphene-semiconductor heterojunction, wherein influence factors comprise the change of Fermi level of single-layer graphene after the heterojunction is formed and the influence of an interface state on a formation position of a contact potential difference; extracting heterojunction electrical characteristics by using a Kelvin probe force microscope; the interface layer spacing is obtained; and importing the heterojunction electrical characteristics and the interface interlayer spacing into a physical characteristic model, and analyzing to obtain physical characteristics. According to the new theoretical model and the method for realizing the nondestructive characterization of the physical characteristics of the heterojunction by using the Kelvin probe microscope based on the theoretical model, the influence of the change of the Fermi level of the single-layer graphene and the interface state on the formation position of the contact potential difference is fully considered; key interface physical properties, especially built-in potential and depletion region characteristics which are crucial to device performance, can be accurately analyzed.

Disclosed is a single photon detector comprising a semiconductor substrate and a 2D material layer provided adjacent to the semiconductor substrate, the semiconductor substrate includes a first well having a first conductivity type, a heavily doped region having a second conductivity type different from the first conductivity type, and a depletion region provided between the first well and the heavily doped region.

The invention discloses a deep trench isolation structure and a manufacturing process method thereof, an injection layer of a second conduction type is arranged on a substrate of a first conduction type, and a deep trap of the second conduction type is arranged on the injection layer; the surface layer of the deep well is provided with a shallow trench isolation structure, and the outer side of the shallow trench isolation structure is provided with a well region of a second conductive type; a deep trench is formed in the shallow trench isolation structure through etching; filling materials which are filled in sections are arranged in the deep grooves; wherein the lower part in the deep trench is filled with a silicon oxide material, and the upper part in the deep trench is filled with a polycrystalline silicon material; filling in the deep trench is divided into two sections of composite filling made of different materials, the portion located on the lower portion of the deep trench is made of silicon oxide, the portion located on the upper middle portion of the deep trench is made of polycrystalline silicon, the structure is further optimized, the bottom of DTI polycrystalline silicon is shortened to the position below an injection layer, the bottom of the DTI polycrystalline silicon can pull up a high peak electric field in a depletion region, and therefore the reliability of the deep trench is improved. And the breakdown voltage of the device is improved.

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, before the second conductive layer is formed, the ion implantation process is carried out on the substrate, so that the first ion implantation region is formed in the substrate below the deep trench, and the second ion implantation region is synchronously formed in the substrate at two sides of the deep trench, thereby saving an ion implantation process. The conduction type of the first ion implantation region (located between the control gate and the drain electrode) is opposite to that of the substrate, so that carriers can be mutually depleted, and the purpose of increasing a depletion region and the breakdown voltage is achieved; and then a second conductive layer is formed and deposited in the deep trench, and a control gate in a special shape is formed by combining a first conductive layer on the side wall of the deep trench, so that the purposes of reducing the overlapping area between the control gate and a drain electrode, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss and finally improving the switching speed are achieved.

The invention relates to the technical field of silicon carbide single crystal films, and provides a silicon carbide single crystal film stripping method and a silicon carbide single crystal film stripping device. An n-type silicon carbide substrate and a silicon carbide single crystal film on the surface of the n-type silicon carbide substrate are provided, and incident light is used for irradiating the surface of the n-type silicon carbide single crystal film; under the action of an internal electric field of a depletion region of an interface region of the n-type silicon carbide substrate and the silicon carbide single crystal thin film, photo-generated holes in the photo-generated hole-electron pair are enriched on one side, close to the silicon carbide single crystal thin film, of the depletion region and react with etching liquid; therefore, one side, close to the silicon carbide single crystal film, of the depletion region is selectively etched, and stripping of the silicon carbide single crystal film is achieved.

An optical semiconductor chip of the present disclosure includes a high frequency line between an electrode pad receiving a modulation signal and a modulation electrode on the optical waveguide having a light absorption layer. The depletion layer capacitance generated in the light absorption layer is canceled by an inductor component of the high frequency line. When a portion directly below the high frequency line is embedded with a low-dielectric-constant material or is made hollow, the parasitic capacitance is further reduced. The high frequency line may have a zigzag shape as well as a linear shape. The electrode pad on the optical semiconductor chip can be connected to other substrates including RF lines for modulation signal input by bumps or wire bonding.

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure for improving dynamic characteristics, which comprises a SiC VDMOSFET structure formed by mutually connecting a plurality of VDMOS cells in parallel, each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, an N well layer, a P well layer and a depletion layer; wherein the N well layer is isolated from the diffusion layer by the P well layer, and the N well layer is in ohmic short circuit with the metal source electrode. According to the utility model, the charge conduction performance of the depletion layer is changed by doping phosphorus elements with different concentrations in the depletion layer region, the depletion layer has a better charge attraction effect in a conduction state, and the JFET region is reduced to the third region of the depletion layer along with the increase of the grid voltage, so that the conductivity of a charge channel is multiplied, and the conductivity of the charge channel is improved. Therefore, bidirectional optimization of switching loss and switching EMI noise can be realized, and the purpose of improving the dynamic characteristics of the device is achieved.

A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses a silicon carbide semiconductor device with an N-top region, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that the semiconductor epitaxial layer comprises an N substrate layer and an N drift layer, a P + well layer, an N well layer and a P well layer are formed in the N drift layer through ion implantation; a first N-type doped region is formed in the N drift layer and located under the grid electrode through ion implantation, and a P-type doped region is formed in the first N-type doped region through ion implantation. A PN junction formed by P-type doping can generate a large depletion layer, the depletion layer mainly expands to a JFET region with low doping concentration, short-circuit current flows through a position closer to the center of the JFET region, the density of the short-circuit current can be effectively reduced by adding the first N-type doping region and the P-type doping region, and the short-circuit tolerance time of the device is prolonged.

The invention relates to the technical field of transistor structures, and provides a region activation mixed gate structure, a high electron mobility transistor and a manufacturing method, and the structure comprises a substrate structure, and a source electrode and a drain electrode which are disposed on the substrate structure. The gate depletion layer is arranged on the substrate structure and between the source electrode and the drain electrode; an activation enhancement region is formed between the activation enhancement layer and the gate depletion layer; the gate lead-out layer is arranged on the activation enhancement area and the area, not covered by the activation enhancement layer, of the gate consumption layer, and the area, making contact with the gate consumption layer, of the gate lead-out layer forms a low-leakage area. An activation enhancement region with high grid leakage is formed through an activation enhancement layer, a path for rapidly releasing trapped charges in a grid consumption layer is provided, and by adjusting the proportion of the activation enhancement region to a low leakage region, the grid performance is guaranteed while the trapped charges are rapidly released, the influence of the trapped charges is reduced, and the threshold voltage drift is improved. The switch performance and stability are improved.

The invention discloses an ultra-short channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure capable of resisting a short channel effect and a manufacturing process thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the core design is that a side symmetric P layer forms a strong depletion region, and drain induced barrier lowering (DIBL) and threshold voltage drift are directly inhibited; the top P-layer, the combined P-layer, the rectangular P-layer, the long-strip P-layer and the like form an auxiliary depletion region to further compress channel edge electric field distortion and cooperatively strengthen suppression on a short channel effect, so that the problem of performance degradation caused by shortening of the channel length in an ultra-short channel structure is solved, and the device can still keep stable electrical characteristics under the condition of small size.

The invention discloses a high-gain NPN-type heterojunction photoelectric detector and a preparation method thereof, and relates to the field of photoelectric detectors, and the NPN-type heterojunction photoelectric detector comprises a first N-type semiconductor layer, a P-type semiconductor layer and a second N-type semiconductor layer which are sequentially arranged between a positive electrode and a negative electrode. The first N-type semiconductor layer and the second N-type semiconductor layer are made of the same material, and the doping concentration of the P-type semiconductor layer is larger than that of the first N-type semiconductor layer. According to the photoelectric detector, the photo-generated current of the photoelectric detector is remarkably improved by applying the bias voltage to the photoelectric detector, high responsivity is achieved, and decoupling of the restriction relation between the responsivity and the response time is achieved. By designing the NPN-type heterostructure detector, the potential barrier at the bottom and the depletion region of the middle layer can effectively reduce dark current, and high specific detection rate is realized.

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

The embodiment of the invention provides an enhanced GaN power device, and the device comprises a substrate which comprises a channel layer and a barrier layer which form an electron gas channel; the source electrode and the drain electrode are arranged at an interval along the first direction and are electrically connected through the electron gas channel; the first depletion layer is arranged on the barrier layer and located between the source electrode and the drain electrode, the first depletion layer comprises a first depletion body and a second depletion body, the second depletion body comprises a depletion monomer, and the depletion monomer comprises a first end connected with the first depletion body and a second end spaced from the drain electrode; a non-depletable region and a depletable region which are arranged along a second direction are defined by the depletion monomer in the electron gas channel, and the second direction is intersected with the first direction; and the first grid electrode is arranged on the first depletion body and is in ohmic contact with the first depletion body. According to the embodiment of the invention, the electric field distribution of the device in the off-state drain electrode high-pressure stress can be optimized so as to improve the breakdown voltage, and the trap effect in the device can be effectively inhibited so as to optimize the dynamic resistance degradation problem of the device.

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a gate structure and a buried layer structure, the substrate has a first conduction type, the epitaxial layer has the first conduction type and is located on the surface of the substrate, the epitaxial layer comprises a first surface, and the first surface is provided with a gate trench; the gate structure is located in the gate trench; the buried layer structure comprises a first buried layer and a second buried layer, the second buried layer has a first conductive type, the first buried layer has a second conductive type, the ion concentration of the second buried layer is greater than that of the epitaxial layer, and the second buried layer is configured to reduce the width of a depletion region between the second buried layer and the first buried layer. According to the technical scheme of the embodiment of the invention, the gate oxide layer can be protected from being broken down easily, the reliability of the device is improved, and the on-state current of the device is ensured.

The invention discloses a semi-SGT MOSFET device. A first epitaxial layer and a second epitaxial layer are formed on a semiconductor substrate. The terminal structure in the terminal area comprises more than two first annular terminal grooves surrounding the periphery of the active area. And a terminal source conductive material layer is formed in each first annular terminal groove. The outermost primitive cell groove and each first annular terminal groove longitudinally penetrate through the second epitaxial layer; a first injection region is formed in the first epitaxial layer at the bottom of the outermost primitive cell groove and the bottom of each first annular terminal groove, and a first injection region is not formed in the first epitaxial layer at the inner side of the outermost primitive cell groove. A first width is formed between the inner side face of the first annular terminal groove on the innermost side and the outer side face of the first annular terminal groove on the outermost side. The first width ensures that the size of a depletion region of the terminal region meets the voltage-withstanding requirement of the semi-SGT MOSFET device. The size of the depletion region of the terminal region can be expanded, so that the breakdown voltage of the device can be improved.

A method of forming a graphene device includes: providing a glass substrate with a blocking layer disposed thereon to form a stack; providing a first electrode and a second electrode; increasing the temperature of the stack to at least 100° C.; applying an external electric field (VP) to the first electrode such that at least one metal ion of the glass substrate migrates toward the first electrode to create a depletion region in the glass substrate adjacent the second electrode; decreasing the temperature of the stack to room temperature while applying the external electric field to the first electrode; and after reaching room temperature, setting the external electric field to zero to create a frozen voltage region adjacent the second electrode.

Disclosed are a neuron and a neuromorphic system including the same. More particularly, a neuron according to an embodiment of the present invention includes a completely depleted Silicon-On-Insulator (SOI) device whose a depletion region is controlled according to an inputted electrical signal to perform integration and leakage.

The invention relates to a field effect transistor and a preparation method thereof, and the field effect transistor comprises an insulating substrate, a two-dimensional material Bi2O2Se channel layer which grows on the insulating substrate in situ, a first electrode and a second electrode which are arranged on the two-dimensional material Bi2O2Se channel layer, a two-dimensional material MoO3 layer which is arranged on the two-dimensional material Bi2O2Se channel layer, and a third electrode which is arranged on the two-dimensional material MoO3 layer, the two-dimensional material MoO3 layer completely covers the two-dimensional material Bi2O2Se channel layer; the width of a depletion region of the Bi2O2Se channel layer is controlled through voltage applied to the MoO3 layer, so that the switching function of the transistor is achieved, a good sub-threshold characteristic is obtained, meanwhile, due to the high carrier mobility characteristic of the two-dimensional Bi2O2Se material, a remarkable electrical response can be obtained only by applying small source and drain voltage, and the performance of the transistor is improved. And excellent sub-threshold characteristics and conduction current performance are presented.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The utility model belongs to the field of semiconductor power device manufacturing, and particularly relates to a GaN-based HEMT device with an inclined field plate structure, which comprises a substrate layer, a buffer layer connected above the substrate layer, an AlGaN barrier layer connected above the buffer layer, a GaN cap layer connected above the AlGaN barrier layer, and a GaN layer connected above the GaN cap layer. The left side and the right side of the GaN cap layer are oppositely connected with a source electrode and a drain electrode, the top of the GaN cap layer is connected with SiN passivation, the top of the GaN cap layer is connected with a grid electrode, and Schottky contact is formed between the grid electrode and the GaN cap layer; a field plate is introduced into the grid electrode. By introducing the field plate structure, electric field lines at the edge of the grid electrode are dispersed, and the electric field intensity at the edge of the grid electrode is effectively reduced, so that the electric field distribution in a depletion layer is more uniform, the possibility that electrons tunnel to a surface trap is reduced, the formation of a virtual grid effect is further hindered, and the performance of the device is improved. And the current collapse phenomenon of the device is effectively reduced.

The invention discloses a defect detection method and a defect detection device based on a semiconductor structure, and the method comprises the steps: applying a voltage to the semiconductor structure to form a stable depletion layer, recording an initial capacitance value, applying a pulse voltage to the semiconductor structure, and closing the pulse voltage, acquiring multiple groups of capacitance parameters of the capacitor of the semiconductor structure under the multiple groups of time parameters; obtaining a characteristic value and a characteristic temperature through the function relation model, the time parameter and the capacitance parameter; a curve of the characteristic value and the characteristic temperature reciprocal is established, and the capture cross section and the defect energy level of the defect are obtained through curve linear fitting; each group of time parameters comprises a first moment and a second moment, and the difference between the second moment and the first moment of each group of time parameters is an arithmetic progression. According to the method and the device, the uniformly distributed characteristic values are obtained through the multiple groups of time parameters with the arithmetic progression relation, so that a more reliable result can be linearly fitted.

The invention discloses an oxide semiconductor plane p / n superstructure and a preparation method thereof. According to the method, a latticed mask is formed on the surface of an oxide thin film based on a photoetching process, O2 atmosphere annealing (100-300 DEG C, 15-40 min) is combined, the local oxygen vacancy concentration of a mask covering area and an exposed area is precisely regulated and controlled, and precise in-situ conversion of a p type (oxygen-rich area) and an n type (oxygen-poor area) in a homogeneous material is achieved. The planar p / n superstructure breaks through the strict limitation of a traditional vertical multi-junction structure on material doping and interface quality, the width of a depletion region is expanded to the micron order through the p / n homojunction arrays alternately distributed in the plane, and the bulk recombination effect of photon-generated carriers is remarkably inhibited. According to the method, an innovative technical route of photoetching-assisted in-situ construction of the planar multi-junction photoelectrode is created, the method has the advantages of interface atomic-scale lattice matching, simple process, high compatibility, accurate and controllable space charge distribution and the like, and a technical foundation is laid for non-assisted solar water decomposition, research and development of self-driven optoelectronic devices and the like.

The utility model provides a silicon carbide transistor device and a power supply circuit. The silicon carbide transistor device comprises a shielding groove and a well region which are located in an epitaxial layer of a substrate and are isolated from each other; the source injection region and the well region extraction region are located in the well region; the first part of the grid is located above the epitaxial layer, and the second part of the grid is located in the shielding groove; the gate oxide layer is positioned between the first part of the gate and the epitaxial layer; the interlayer dielectric layer covers the surface of the first part of the gate; the second oxide layer is positioned between the second part of the grid electrode and the shielding groove; the thick oxide layer with the thickness larger than that of the gate oxide layer is arranged at the bottom of the shielding groove, and the depth of the shielding groove is set to be smaller than or equal to that of the well region, so that a depletion region can be formed at the bottom of the shielding groove more quickly along with increase of drain voltage in a device turn-off state; and the breakdown voltage of the device and the reliability of the gate oxide layer in a turn-off state can be further improved.

The invention belongs to the field of semiconductors, and discloses a novel ferroelectric memcapacitor based on an MFIS structure and a preparation method thereof, a substrate of the novel ferroelectric memcapacitor comprises a first doped region and a second doped region, and the doping type of the first doped region is p-type; the insulating layer, the ferroelectric layer and the top electrode layer are arranged on the substrate from bottom to top and cover the first doped region of the substrate; an uncovered area on the surface of the substrate is a second doped area, and the doping type of the second doped area is n type; the bottom electrode layer is located in the second doped region of the substrate and is far away from the first doped region; the channel is located in the second doped region of the substrate and is close to the first doped region; the invention also provides a corresponding preparation method, according to the ferroelectric memcapacitor prepared by using the method, because the semiconductor layer has a PN junction depletion region, the ferroelectric film can be fully overturned by using a band-to-band tunneling mechanism without large voltage, and meanwhile, the capacitance of the depletion region of the PN junction on one side of the semiconductor is adjusted, so that a relatively high capacitance-to-switch ratio is obtained while low power consumption is ensured.

The invention discloses an enhanced HEMT (High Electron Mobility Transistor) device and a preparation method thereof, and belongs to the technical field of reliability reinforcement of nitride power semiconductor devices. In the structure of the enhanced HEMT device provided by the invention, the p-type GaN cap layer has a memory effect, Mg can be gathered near metal contact, and the influence can be effectively relieved by adding the InGaN layer and the UID-GaN, so that the reliability of the grid electrode is improved. The UID-GaN layer and the InGaN layer are non-deliberately doped, so that a p + n junction structure is simply formed, a depletion region near the grid electrode and metal is enlarged, higher voltage can be borne, the electric leakage of the grid electrode is reduced, and the reliability of the grid electrode is improved. Besides, the forbidden band width of InGaN is lower than that of GaN, so that an energy level recess can be formed on an energy band, tunneling of electrons and holes is more difficult to occur, gate electric leakage is reduced, and gate reliability is improved.

The invention discloses a particle deposition prevention shielding piece for coating equipment, which is arranged in a coating cavity and comprises an annular upper plate and an annular lower plate, and a labyrinth type airflow channel is formed between the upper plate and the lower plate through baffles which are staggered up and down and arranged at intervals; a gap of 0-2mm exists between the outer edge of the shielding piece and the inner wall of the film coating cavity, the cavity wall of the film coating cavity is grounded, and the gap is constructed into an electron depletion region mainly comprising positive charges; according to the utility model, particles entering by mistake are intercepted through the labyrinth type channel, particles escaping along the gap are blocked through the electron depletion region, the pollution frequency of the lower cavity can be greatly reduced, and thus the downtime and the maintenance cost of equipment are reduced; the labyrinth type airflow channel and the electron depletion area are both designed in a non-blocking mode, the labyrinth type airflow channel does not hinder normal conveying of reaction gas, the electron depletion area does not affect lifting of the wafer and the shielding piece, the anti-pollution function is achieved, meanwhile, the technological rhythm of existing coating equipment is completely adapted, and the main body structure of the equipment does not need to be changed.