34 results about "Shallow junction" patented technology

The invention discloses a preparation method of a solar cell, and the method comprises the following steps: placing an N-type silicon wafer in a furnace tube of a diffusion furnace, and introducing nitrogen and oxygen into the furnace tube to form a first oxide layer on the surface of the silicon wafer; boron trichloride, oxygen and nitrogen are introduced into the furnace tube, so that a boron diffusion layer is formed on the surface, away from the silicon wafer, of the first oxide layer; introducing nitrogen into the furnace tube, and controlling the temperature of the furnace tube to be a first temperature so as to carry out oxygen-free propulsion of the boron element; introducing nitrogen and oxygen into the furnace tube, and controlling the temperature of the furnace tube to rise from the first temperature to a second temperature so as to carry out aerobic propulsion of the boron element; dry oxygen and wet oxygen are alternately introduced into the furnace tube for multiple times to form a second oxide layer; the temperature in the furnace tube is reduced, and dry oxygen continues to be introduced into the furnace tube; and nitrogen is introduced into the furnace tube, the temperature in the furnace tube is reduced, and boron diffusion of the silicon wafer is completed. According to the preparation method of the solar cell, the silicon wafer can have low surface concentration shallow junctions and uniform sheet resistance.

The invention discloses a preparation method of a back contact solar cell and the back contact solar cell. The preparation method comprises the steps that a shallow junction diffusion layer containing first doping atoms is formed in a first functional area of a first main surface of a silicon substrate, and the first main surface of the silicon substrate comprises the first functional area, a second functional area and an isolation area located between the first functional area and the second functional area; pushing the first doped atoms of the shallow junction diffusion layer to form a deep junction diffusion layer, forming a silicon dioxide source absorption layer on the outer side of the shallow junction diffusion layer, the second functional area and the isolation area, performing oxidation source absorption processing based on the silicon dioxide source absorption layer, and forming a second doped silica glass layer in the first functional area; cleaning the second doped silica glass layer and the residual silicon dioxide source absorption layer by using an acid solution, completely removing the silicon dioxide source absorption layer, and partially removing the second doped silica glass layer; forming a carrier collection layer containing second doping atoms in the second functional area; and removing the residual second doped silica glass layer. The preparation method can reduce damage to the silicon substrate.

The application relates to a laser annealing device for improving a CMOS wafer shallow junction process, which comprises a laser, a beam pointing adjustment system, a beam expander, a power adjustment system, a knife edge, a third beam combiner, a beam quality analyzer, an integrating mirror, a heating disc, a motion platform, a computer, a three-color temperature thermal emission detector and a laser range finder. The power adjustment system is composed of a lambda / 2 glass and a polarizer arranged on an optical path. The laser emits light with fixed power, the power adjustment system simultaneously controls the output power and the polarization, and avoids problems such as beam quality deterioration and power stability reduction caused by laser power change; the beam quality analyzer, the three-color temperature thermal emission detector and the power adjustment system jointly form an annealing power negative feedback system, and the annealing power size and stability are controlled in real time according to the annealing area temperature feedback result.

The application relates to a preparation method of a germanium-based source-drain material and application thereof, and relates to the field of germanium-based source-drain materials. A germanium-aluminum thin film is grown on a germanium-based substrate through co-deposition of germanium and aluminum. When the substrate temperature is 215-383 DEG C, X-ray diffraction (XRD) tests show that the germanium-aluminum thin film is a single crystal structure, the crystal quality is good, and there is no segregation of aluminum on the surface. Hall test shows that the germanium-aluminum thin film is self-doped with p type, and the activated hole concentration is as high as 8*10 20 According to the characterization results of a time-of-flight secondary ion mass spectrometer (TOF-SIMS), the diffusion length of aluminum atoms on an undoped germanium-based substrate is less than 4 nm / decade, and the germanium-based source-drain material can be applied to the preparation of p-type in-situ doping and p+ / n shallow junction of an advanced node process of a germanium-based logic circuit.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

The invention provides a Hall device and a manufacturing method thereof, and the manufacturing method comprises the steps: firstly, defining a region of a functional layer region of the Hall device on the surface of a high-resistance substrate through a photoetching technology, then carrying out the N-type and P-type ion implantation of the high-resistance substrate at the same time, and carrying out the high-temperature long-time thermal process, a uniform N-type doped device main function layer region and a P-type doped auxiliary function region located at the bottom of the device main function layer region are formed in a high-resistance substrate, and finally a well region and a first heavily doped region located in the well region are formed respectively. According to the invention, no extra photomask needs to be added, the photomask is injected by using the traditional Hall device function layer, N-type and P-type foreign ions are injected at the same time, the junction depth of the Hall device function layer is ensured to be less than or equal to 1.5 microns by adjusting the injection energy and dosage of the two foreign ions, the N-type foreign ions are adjusted to be injected with low doping concentration, the carrier mobility is improved, and the performance of the Hall device is improved. The sensitivity of the Hall device is improved, and the manufacturing difficulty of the shallow junction Hall device is reduced.

The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device based on a SiC material and a manufacturing process of the semiconductor device. The device comprises an N + type SiC substrate, an N-type composite buffer layer which is arranged on the substrate and has a concentration gradient, an N-type drift region which is arranged on the buffer layer, and an active region which is composed of a first conduction type region and a second conduction type ion implantation region. The innovation lies in that a composite buffer layer structure is adopted to effectively suppress dynamic avalanche and optimize the reverse recovery characteristic, and meanwhile, a composite structure of a junction termination extension region and a field limiting ring with shallower junction depth is integrated in a terminal region, so that the process complexity is simplified on the premise of ensuring high breakdown voltage. According to the manufacturing process, impurity activation of the active region and the terminal region is synchronously completed through two times of ion implantation and one time of high-temperature annealing, and the manufacturing process is completely compatible with an existing SiC plane process platform. The device realizes excellent compromise between reverse recovery charge and forward voltage drop, and has the characteristics of superspeed, soft recovery, low loss and high reliability.

The invention discloses a method for manufacturing a shallow junction in a photovoltaic battery piece process, which relates to the technical field of battery manufacturing and comprises the following steps of: performing pretreatment operation on a silicon wafer; performing primary pre-oxidation treatment on the silicon wafer to form an oxide layer on the surface of the silicon wafer; carrying out first-time source passing treatment on the silicon wafer to form an initial PN junction on the surface of the silicon wafer; performing secondary pre-oxidation treatment on the silicon wafer to deepen an oxide layer; second time of source passing processing is carried out on the silicon wafer, and PN junctions are deepened; performing third time of source passing treatment on the silicon wafer, and forming a shallow junction on the surface of the silicon wafer; performing high-temperature oxidation treatment on the silicon wafer; oxygen introduction is stopped, and heat preservation is conducted for 5-6 min at the temperature of 845-850 DEG C; performing post-source processing on the silicon wafer; and carrying out post-oxidation treatment on the silicon wafer. By controlling various parameters in the diffusion process, high-quality manufacturing of shallow junctions is achieved, doping uniformity is improved, and the photoelectric conversion efficiency of the cell is improved.

High quantum efficiency (QE) and highly stable (back-side illuminated (BSI) image sensors are provided. The BSI image sensors include a first substrate and a high doped, ultra-shallow junction (USJ). The first substrate includes a first side and a second side. The first side includes a plurality of image sensor pixels. The second side includes an at least partially exposed epitaxial layer includes a silicon lattice. The USJ is formed in the epitaxial layer. The USJ is formed by applying a dopant to the epitaxial layer utilizing atomic layer deposition (ALD) or monolayer doping (MLD) and laser annealing the epitaxial layer for drive-in diffusion of the dopant into the epitaxial layer and activation of the dopant in the silicon lattice of the epitaxial layer, thereby forming the USJ.

The invention discloses a preparation method and application of a germanium-based source-drain material, and relates to the field of germanium-based source-drain materials, a germanium-aluminum film grows on a germanium-based substrate through co-deposition of germanium and aluminum, and when the temperature of the substrate is 215-383 DEG C, X-ray diffraction (XRD) tests show that the germanium-aluminum film is of a single-crystal structure, the crystal quality is good, and the surface is free of aluminum segregation. A Hall test shows that the germanium-aluminum film has p-type doping, and the activated hole concentration is as high as 8 * 10 < 20 > # imgabs0 #. According to the characterization result of a time-of-flight-secondary ion mass spectrometer (TOF-SIMS), the diffusion length of aluminum atoms in the undoped germanium-based substrate is smaller than 4 nm / decade, and the method can be applied to p-type in-situ doping and p + / n shallow junction preparation of a germanium-based logic circuit advanced node technology.

This application relates to a solar cell and its fabrication method, a tandem solar cell, and a photovoltaic module. The fabrication method of the solar cell includes: providing a cell body and a conductive material; printing the conductive material onto the cell body; sintering and laser processing the cell body to form electrodes; wherein the conductive material includes silver powder, glass powder, and additives, and the additives include bismuth oxide or antimony oxide. The technical solution of this application has at least the following advantages: precise interface control: through a unique glass system design, "gentle yet effective" etching of the silicon nitride film is achieved. This ensures reliable ohmic contact formation while effectively protecting the underlying shallow junction n+ emitter, significantly reducing the parallel resistance (Rsh) and leakage current of the TOPCon cell, and improving the open-circuit voltage (Voc) and short-circuit current (Isc).

The invention discloses a high-sheet-resistance wet oxygen diffusion method for obtaining low-concentration BSG, and belongs to the technical field of solar cell preparation. A multi-step source introduction method is adopted, the source introduction time is shortened, the source introduction flow is increased, rapid heating promotion is achieved, and a wet oxygen oxidation method and a low-temperature deposition method are innovatively adopted; wherein the low-temperature deposition method can slow the reaction decomposition of an impurity source and reduce the concentration of the impurity source deposited on the surface of a silicon wafer, so that the content of impurities diffused into a silicon substrate is reduced, the effect of deep and shallow junctions is finally realized, and the method is an effective method for preparing low-concentration shallow junctions and obtaining high sheet resistance; according to the invention, high sheet resistance with excellent uniformity is realized while the BSG with low impurity concentration is obtained, the process time is shortened, the subsequent LECO process is ensured to be more ideally realized, and finally, the battery conversion efficiency is improved to the maximum extent and the process time is shortened to the maximum extent.

The invention relates to a preparation method of a power device, the power device, a semiconductor device and electronic equipment. The method comprises the following steps: providing a substrate; forming a front layer structure on the substrate; a first groove, a second groove and a third groove are formed in the front-layer structure, the second groove is located in the middle of the front-layer structure, the first groove and the third groove are located on the two opposite sides of the front-layer structure respectively, and the first groove, the second groove and the third groove are all exposed out of the top face of the substrate; forming a protective layer covering the top surface on the front layer structure; forming a patterned first photoresist layer on the protective layer, wherein the patterned first photoresist layer exposes the second groove covered by the protective layer; and performing ion implantation on the patterned first photoresist layer as a mask to form a body region of a first ion type. At least the source of stress can be reduced, the trouble of alignment deviation of polycrystalline silicon is avoided, and shallow junction ion implantation of a body region can be completely attached to the edge of a polycrystalline silicon gate.

The present application provides a preparation method and application of a crystalline silicon solar cell having a shallow junction diffusion emitter. The preparation method comprises a diffusion process and a chain oxidation process, the diffusion process comprises low temperature diffusion and high temperature propulsion, and the chain oxidation process comprises high-temperature chain oxidation. According to the present application, firstly, a low-doped diffusion shallow junction having a depth of 0.15 um is prepared by means of optimization of the diffusion process, and doping with a certain dose concentration is formed on the surface of a diffusion layer by using photon thermal activation radiation energy of high-temperature chain oxidation, so as to solve the mismatch problem of alloy ohmic contact subsequently formed with silver paste, and finally, the photoelectric conversion efficiency is improved to a high degree.

The invention provides a PN shallow junction composite terminal of a silicon carbide VDMOS and a preparation method, and the method comprises the steps: carrying out the epitaxial growth on a silicon carbide substrate, and forming a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, a first P + doped region, a P + well region, a cut-off ring contact region, a second P + doped region and an N-doped region are formed, and the PN shallow junction comprises the second P + doped region and the N-doped region; forming a barrier layer again, etching and depositing to form an insulating medium region; re-forming a barrier layer, etching and depositing to form an insulating layer; forming a barrier layer again, etching and depositing to form a capacitor metal layer; a barrier layer is formed again, etching and deposition are carried out, and a high-resistivity conductor layer is formed; the method comprises the following steps: re-forming a barrier layer, etching, depositing, forming a source metal layer and a cut-off ring metal layer, removing the barrier layer, transversely expanding an electric field at a main junction of the device to the cut-off ring metal direction, reducing the intensity of the electric field, and improving the reliability of the device.

The present invention provides a method for high-concentration boron diffusion of a box-type boron microcrystalline glass source, comprising: S1) performing high-temperature pretreatment on the boron microcrystalline glass to obtain the pretreated boron microcrystalline glass; S2) stacking the pretreated boron microcrystalline glass and the silicon wafer to be diffusion-treated, and heating for diffusion treatment to obtain the treated silicon wafer; the front surface of the silicon wafer to be diffusion-treated is in contact with the pretreated boron microcrystalline glass; S3) removing the borosilicate glass on the surface of the treated silicon wafer to obtain the silicon wafer subjected to boron diffusion treatment. Compared with the prior art, the present invention directly contacts the PWB source with the Si wafer, can achieve a high surface concentration while forming a shallow junction; secondly, the present invention can also make the upper and lower surfaces of the PWB source contact the doping surfaces of two layers of several Si wafers respectively, improving the diffusion efficiency; furthermore, the method provided by the present invention only uses one-step diffusion, without the need to take out the Si wafer for treatment in the middle, the process is simple and easy to operate, and unnecessary pollution is avoided.

The utility model provides a kind of PN shallow junction composite terminal of silicon carbide VDMOS, comprising: drift layer connects silicon carbide substrate;P+ well region, first P+ doped region, at least three PN shallow junction and cutoff ring contact area are equipped on drift layer;Insulating medium area is equipped in first P+ doped region;Insulating layer is connected insulating medium area, first P+ doped region, PN shallow junction respectively, and at least three grooves are equipped on insulating layer;Capacitor metal layer is located in groove, and capacitor metal layer is located directly above PN shallow junction;Source metal layer is connected P+ well region and first P+ doped region respectively;Cutoff ring metal layer is connected to cutoff ring contact area;High resistivity conductor layer is connected insulating layer, capacitor metal layer, source metal layer and cutoff ring metal layer respectively, and the electric field of device main junction place is expanded transversely to the direction of cutoff ring metal, reduces electric field intensity, improves device reliability.

The present disclosure provides a semiconductor structure and a method for manufacturing the same, and a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of how to realize an ultra-shallow junction. A semiconductor structure includes a substrate, the substrate including a top and a bottom opposite in a direction perpendicular to the substrate. At least one ion implantation region is included in the substrate, the ion implantation region being provided with an indium ion layer and a target ion layer. The indium ion layer is configured to inhibit diffusion of the target ion toward the bottom. The target ion layer is disposed on a side of the indium ion layer away from the bottom, and the target ion layer is configured to form a target well region.

The invention provides a back contact solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of solar cells. A first electrode region and a second electrode region are arranged on the back surface of the silicon substrate, and the first electrode region and the second electrode region are arranged in an interdigital staggered manner; wherein the first electrode region comprises a first selective emitter region and a first non-selective emitter region; wherein the second electrode region includes a second selective emitter region and a second non-selective emitter region. According to the back contact solar cell, deep junction and heavy doping are formed in the metal contact area, and good ohmic contact between a metal electrode and poly-Si is guaranteed; a non-metal contact region forms a shallow junction, light doping is achieved, parasitic absorption is reduced, and lattice distortion is weakened.

The invention discloses a novel diffusion process for gradient deposition and diffusion of high sheet resistance, and relates to the field of boron diffusion of solar cells, and the novel diffusion process comprises the following steps: in a tubular diffusion furnace, BCl3 enters from the furnace during ventilation, boron trichloride is decomposed at a high temperature and reacts with Si to generate elemental boron, and the elemental boron is diffused into a silicon substrate to form a PN junction; diffusion is divided into three steps: pre-diffusion, diffusion and redistribution, limited surface source diffusion is adopted, impurities introduced by pre-diffusion and diffusion are used as diffusion sources, and diffusion is carried out at a relatively high concentration so as to control the surface concentration and the diffusion depth. According to the novel gradient deposition diffusion high sheet resistance diffusion process, the high surface concentration and shallow junction depth design is adopted, the shallow junction depth design can effectively reduce the impurity recombination center of the surface, the survival rate of surface minority carriers is improved, meanwhile, the response of short waves is increased, Isc and Uoc are effectively increased based on the design, and therefore the performance of the diffusion process is improved. And the purpose of improving efficiency is achieved.

The present invention discloses a low residual voltage ESD device and a method for manufacturing the same. The method comprises: providing a P-type substrate, exposing an N-type implantation region and a P-type implantation region through a mask layer; simultaneously implanting inert ions into the N-type implantation region and the P-type implantation region to form an amorphous structure layer; implanting phosphorus ions into the N-type implantation region to form an N-type trigger region on the surface of the amorphous structure layer in the N-type implantation region, and implanting boron ions into the P-type implantation region to form a P-type anode region on the surface of the amorphous structure layer in the P-type implantation region; performing multiple annealing treatments on the P-type substrate and forming a passivation layer on the surface of the P-type substrate; etching the passivation layer to form contact holes to expose the surfaces of the N-type implantation region and the P-type implantation region, and growing an electrode layer in the contact holes to obtain a low residual voltage ESD device. The present invention forms an ultra-shallow junction through the amorphous structure layer and low-energy ion implantation, which can significantly reduce the on-resistance of the ESD device and reduce the voltage clamping residual voltage.

The invention belongs to the technical field of semiconductor photoelectric detectors, and discloses a one-time diffusion preparation method of a planar InGaAs / InP avalanche photodiode convex junction, which comprises the following steps of: forming an InGaAs / InP avalanche epitaxial material, and sequentially performing surface passivation, diffusion hole photoetching, diffusion hole mask etching and diffusion doping processes on the surface of the epitaxial material to complete the preparation of the convex junction. A deep junction diffusion region of a diffusion photoetching plate used for diffusion hole photoetching is a circular or square main junction exposure region, a shallow junction diffusion region is a narrow-band annular exposure region surrounding the deep junction diffusion region, and the narrow-band annular exposure region is separated from the main junction exposure region through a narrow-band ring. According to the method, the steps of photoetching overlay and secondary diffusion (including corresponding cleaning, etching and other processes) are omitted, the technological process is greatly simplified, and the requirement for photoetching precision is lowered.

The application provides an ultra-shallow junction deep low-energy electron detector, which comprises a silicon substrate containing opposite first and second surfaces; an ultra-shallow junction deep P-type doped layer formed on the first surface of the silicon substrate by forming a boron single layer on the surface of the silicon substrate and then performing thermal diffusion, the thickness of the P-type doped layer being 3-10 nm; an N-type doped layer formed on the second surface of the silicon substrate; a guard ring structure extending from the P-type doped layer towards the silicon substrate; a barrier layer formed on the P-type doped layer, a window being formed in the barrier layer, and a detection area of the electron detector being defined through the window; and a grid electrode formed on the P-type doped layer in the detection area. The application can effectively solve the problem of detecting low-energy electrons by the electron detector and effectively improve the detection efficiency of low-energy electrons.

The application discloses a kind of super surface hetero integrated silicon-based EUV detector design and preparation method thereof, the detector is based on super surface light field regulation and control ability and graphene / silicon hetero integrated " ultra shallow junction " characteristics, silicon nano column is lithographically etched on SOI, single-layer graphene is transferred to the top of silicon nano column by using " full dry transfer technology " to realize hetero integration, obtain Schottky barrier structure unit, overcome the key challenge of silicon-based EUV detector development (i.e., how to realize the efficient detection of extremely low transmission depth EUV band, and at the same time complete the effective extraction of light field (wave front) information). The application develops an integrated solution of EUV wave front information and direct " photoelectric " detection function, obtains a device prototype close to the theoretical performance limit, lays a foundation for developing a new type of EUV wave front detection system, and has important significance for developing new EUV detection system key components.

The present invention provides an N-type lateral double-diffused MOS field-effect transistor and its fabrication method. By setting a second heavily doped region and a third heavily doped region within the substrate, located in the second well region and connected to the cathode, a bidirectional N-P-N-P-N structure is formed. This achieves bidirectional ESD protection through a simple structure without the need for additional ESD protection devices. Thus, it balances ESD protection effectiveness with improved integration density. Furthermore, by setting an N-type first well region and a first heavily doped region, with the first heavily doped region located within the first well region and extending into the second well region, a shallow junction of N-type doped / P-type well is formed, significantly reducing the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor.

The invention relates to a low-junction capacitance symmetric transient voltage suppressor diode and a preparation method thereof. The preparation method comprises the steps of silicon wafer cleaning, N-type doping, oxidation, photoetching, oxide layer removal, slotting corrosion, passivation, surface corrosion, electrode manufacturing, metal stripping and cutting. Wherein in the N-type doping step, POCl3 is used as a gas-phase phosphorus source, double-sided synchronous diffusion is carried out on a silicon wafer, and a shallow junction N-type region with the junction depth of 1.5-3.0 microns is formed; in the oxidation step, the silicon wafer with the shallow junction N-type region is subjected to high-temperature oxidation in an oxygen-containing atmosphere, phosphorus atoms are driven to be redistributed from the surface to the inside, a doping section with the phosphorus concentration gradually changing from the surface of the silicon wafer to the inside is formed, and a surface oxidation layer is synchronously grown. According to the preparation method disclosed by the invention, the junction capacitance is reduced, and the symmetry, the response speed and the pulse endurance capability of the bidirectional transient voltage suppression diode are improved by improving the doping uniformity.

The present invention provides a PN shallow junction composite terminal and a preparation method thereof for a silicon carbide VDMOS. The method includes: epitaxially growing on a silicon carbide substrate to form a drift layer; forming a blocking layer above the drift layer, etching, and ion implanting to form a first P+ doped region, a P+ well region, a cut-off ring contact region, a second P+ doped region, and an N-doped region. The PN shallow junction includes the second P+ doped region and the N-doped region; reforming the blocking layer, etching, and depositing to form an insulating dielectric region; reforming the blocking layer, etching, and depositing to form an insulating layer; reforming the blocking layer, etching, and depositing to form a capacitive metal layer; reforming the blocking layer, etching, and depositing to form a high-resistivity conductor layer; reforming the blocking layer, etching, and depositing to form a source metal layer and a cut-off ring metal layer, removing the blocking layer, and laterally expanding the electric field at the main junction of the device towards the cut-off ring metal direction to reduce the electric field intensity and improve the device reliability.

The embodiment of the invention relates to the photovoltaic field, and discloses a preparation method of a battery piece and a photovoltaic module, and the method comprises the steps: providing a substrate, placing the substrate in a diffusion furnace tube, raising the temperature in the diffusion furnace tube from a preheated first temperature to a second temperature, carrying out pre-oxidation treatment on the surface of the substrate at the second temperature; keeping the temperature in the diffusion furnace tube at the second temperature, and introducing a doping source into the diffusion furnace tube for multiple times so as to perform diffusion deposition for multiple times; raising the temperature in the diffusion furnace tube to a third temperature, and performing high-temperature propulsion for multiple times at the third temperature; reducing the temperature in the diffusion furnace tube to the second temperature, and performing low-temperature propulsion at the second temperature; and reducing the temperature in the diffusion furnace tube to a fourth temperature so as to form a semiconductor doping layer on the surface of the substrate. According to the scheme, an ideal diffusion model of a low-surface-concentration shallow junction can be obtained, and the performance of the solar cell is improved.

The invention provides a semiconductor process method and a semiconductor device, and the method comprises the steps: a first barrier layer and a second barrier layer sequentially cover the surface of a semiconductor structure, and the first barrier layer is thinner than the second barrier layer; forming a second barrier layer on the side wall to obtain a first barrier layer on the side wall of the gate structure and the bottom of the second barrier layer; removing the second barrier layer; lDD ion implantation is carried out to form stepped shallow doping distribution; and the drain barrier layer forms a source-drain heavily doped region for mask ion implantation. According to the invention, the barrier layer is arranged for multiple times and then is locally removed to obtain the stepped barrier layer, and LDD ion implantation forms shallow doping distribution of concentration gradient change to optimize a slowly-changing junction gradient, disperse an electric field and inhibit hot carrier injection; meanwhile, the shallow doping distribution with the depth gradient change enables the deep junction to suppress the leakage current, the shallow junction to suppress the short-channel effect, and the hot carrier injection and the short-channel effect are doubly suppressed; the barrier layer material is arranged to control step distribution; and finally, setting the thickness of the barrier layer to optimize the hot carrier injection and short channel effect suppression effect.

The invention relates to the technical field of solar cells, particularly provides a boron-doped emitter, a TOPcon cell and a preparation method, and aims to solve the problem that in the prior art, a boron-doped p + emitter formed through one-time deposition cannot give consideration to the surface recombination rate and the contact performance at the same time. In order to achieve the purpose, at least two borosilicate glass layers are deposited on the front face of a silicon substrate, a silicon dioxide layer is deposited between every two adjacent borosilicate glass layers, and the molar ratio of boron to oxygen in each borosilicate glass layer is gradually increased layer by layer in the direction gradually away from the silicon substrate. According to the invention, the silicon dioxide layer is arranged, and the B / O ratio of the outer borosilicate glass layer is greater than that of the inner borosilicate glass layer, so that the surface recombination rate and the contact performance can be considered, a high surface shallow junction is formed, and the open-circuit voltage and the fill factor are greatly improved.