17 results about "Shallow junction" patented technology

The application relates to a laser annealing device for improving a CMOS wafer shallow junction process, which comprises a laser, a beam pointing adjustment system, a beam expander, a power adjustment system, a knife edge, a third beam combiner, a beam quality analyzer, an integrating mirror, a heating disc, a motion platform, a computer, a three-color temperature thermal emission detector and a laser range finder. The power adjustment system is composed of a lambda / 2 glass and a polarizer arranged on an optical path. The laser emits light with fixed power, the power adjustment system simultaneously controls the output power and the polarization, and avoids problems such as beam quality deterioration and power stability reduction caused by laser power change; the beam quality analyzer, the three-color temperature thermal emission detector and the power adjustment system jointly form an annealing power negative feedback system, and the annealing power size and stability are controlled in real time according to the annealing area temperature feedback result.

According to the silicon-based PIN photodiode, the manufacturing method and the electronic device provided by the invention, the FZ single crystal is adopted as the substrate, and the doped region is formed in an ion implantation and annealing mode, so that the junction depth and the concentration can be effectively controlled. And thinning the silicon wafer by adopting a Taiko back thinning process. The photosensitive area adopts a shallow junction and deep junction combined structure, the shallow junction can increase the blue light absorption rate, and the deep junction forms ohmic contact. The anti-reflection layer adopts a silicon dioxide and silicon nitride double-layer structure, so that the surface stress of silicon / silicon nitride can be effectively relieved, and the reliability is improved. The cut-off region N + and the back N + can reduce dark current, and back metallization can form a back cathode.

The invention discloses a method for manufacturing a shallow junction in a photovoltaic battery piece process, which relates to the technical field of battery manufacturing and comprises the following steps of: performing pretreatment operation on a silicon wafer; performing primary pre-oxidation treatment on the silicon wafer to form an oxide layer on the surface of the silicon wafer; carrying out first-time source passing treatment on the silicon wafer to form an initial PN junction on the surface of the silicon wafer; performing secondary pre-oxidation treatment on the silicon wafer to deepen an oxide layer; second time of source passing processing is carried out on the silicon wafer, and PN junctions are deepened; performing third time of source passing treatment on the silicon wafer, and forming a shallow junction on the surface of the silicon wafer; performing high-temperature oxidation treatment on the silicon wafer; oxygen introduction is stopped, and heat preservation is conducted for 5-6 min at the temperature of 845-850 DEG C; performing post-source processing on the silicon wafer; and carrying out post-oxidation treatment on the silicon wafer. By controlling various parameters in the diffusion process, high-quality manufacturing of shallow junctions is achieved, doping uniformity is improved, and the photoelectric conversion efficiency of the cell is improved.

High quantum efficiency (QE) and highly stable (back-side illuminated (BSI) image sensors are provided. The BSI image sensors include a first substrate and a high doped, ultra-shallow junction (USJ). The first substrate includes a first side and a second side. The first side includes a plurality of image sensor pixels. The second side includes an at least partially exposed epitaxial layer includes a silicon lattice. The USJ is formed in the epitaxial layer. The USJ is formed by applying a dopant to the epitaxial layer utilizing atomic layer deposition (ALD) or monolayer doping (MLD) and laser annealing the epitaxial layer for drive-in diffusion of the dopant into the epitaxial layer and activation of the dopant in the silicon lattice of the epitaxial layer, thereby forming the USJ.

This application relates to a solar cell and its fabrication method, a tandem solar cell, and a photovoltaic module. The fabrication method of the solar cell includes: providing a cell body and a conductive material; printing the conductive material onto the cell body; sintering and laser processing the cell body to form electrodes; wherein the conductive material includes silver powder, glass powder, and additives, and the additives include bismuth oxide or antimony oxide. The technical solution of this application has at least the following advantages: precise interface control: through a unique glass system design, "gentle yet effective" etching of the silicon nitride film is achieved. This ensures reliable ohmic contact formation while effectively protecting the underlying shallow junction n+ emitter, significantly reducing the parallel resistance (Rsh) and leakage current of the TOPCon cell, and improving the open-circuit voltage (Voc) and short-circuit current (Isc).

The present application provides a preparation method and application of a crystalline silicon solar cell having a shallow junction diffusion emitter. The preparation method comprises a diffusion process and a chain oxidation process, the diffusion process comprises low temperature diffusion and high temperature propulsion, and the chain oxidation process comprises high-temperature chain oxidation. According to the present application, firstly, a low-doped diffusion shallow junction having a depth of 0.15 um is prepared by means of optimization of the diffusion process, and doping with a certain dose concentration is formed on the surface of a diffusion layer by using photon thermal activation radiation energy of high-temperature chain oxidation, so as to solve the mismatch problem of alloy ohmic contact subsequently formed with silver paste, and finally, the photoelectric conversion efficiency is improved to a high degree.

The utility model provides a kind of PN shallow junction composite terminal of silicon carbide VDMOS, comprising: drift layer connects silicon carbide substrate;P+ well region, first P+ doped region, at least three PN shallow junction and cutoff ring contact area are equipped on drift layer;Insulating medium area is equipped in first P+ doped region;Insulating layer is connected insulating medium area, first P+ doped region, PN shallow junction respectively, and at least three grooves are equipped on insulating layer;Capacitor metal layer is located in groove, and capacitor metal layer is located directly above PN shallow junction;Source metal layer is connected P+ well region and first P+ doped region respectively;Cutoff ring metal layer is connected to cutoff ring contact area;High resistivity conductor layer is connected insulating layer, capacitor metal layer, source metal layer and cutoff ring metal layer respectively, and the electric field of device main junction place is expanded transversely to the direction of cutoff ring metal, reduces electric field intensity, improves device reliability.

The present disclosure provides a semiconductor structure and a method for manufacturing the same, and a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of how to realize an ultra-shallow junction. A semiconductor structure includes a substrate, the substrate including a top and a bottom opposite in a direction perpendicular to the substrate. At least one ion implantation region is included in the substrate, the ion implantation region being provided with an indium ion layer and a target ion layer. The indium ion layer is configured to inhibit diffusion of the target ion toward the bottom. The target ion layer is disposed on a side of the indium ion layer away from the bottom, and the target ion layer is configured to form a target well region.

The invention provides a back contact solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of solar cells. A first electrode region and a second electrode region are arranged on the back surface of the silicon substrate, and the first electrode region and the second electrode region are arranged in an interdigital staggered manner; wherein the first electrode region comprises a first selective emitter region and a first non-selective emitter region; wherein the second electrode region includes a second selective emitter region and a second non-selective emitter region. According to the back contact solar cell, deep junction and heavy doping are formed in the metal contact area, and good ohmic contact between a metal electrode and poly-Si is guaranteed; a non-metal contact region forms a shallow junction, light doping is achieved, parasitic absorption is reduced, and lattice distortion is weakened.

The application provides an ultra-shallow junction deep low-energy electron detector, which comprises a silicon substrate containing opposite first and second surfaces; an ultra-shallow junction deep P-type doped layer formed on the first surface of the silicon substrate by forming a boron single layer on the surface of the silicon substrate and then performing thermal diffusion, the thickness of the P-type doped layer being 3-10 nm; an N-type doped layer formed on the second surface of the silicon substrate; a guard ring structure extending from the P-type doped layer towards the silicon substrate; a barrier layer formed on the P-type doped layer, a window being formed in the barrier layer, and a detection area of the electron detector being defined through the window; and a grid electrode formed on the P-type doped layer in the detection area. The application can effectively solve the problem of detecting low-energy electrons by the electron detector and effectively improve the detection efficiency of low-energy electrons.

The application discloses a kind of super surface hetero integrated silicon-based EUV detector design and preparation method thereof, the detector is based on super surface light field regulation and control ability and graphene / silicon hetero integrated " ultra shallow junction " characteristics, silicon nano column is lithographically etched on SOI, single-layer graphene is transferred to the top of silicon nano column by using " full dry transfer technology " to realize hetero integration, obtain Schottky barrier structure unit, overcome the key challenge of silicon-based EUV detector development (i.e., how to realize the efficient detection of extremely low transmission depth EUV band, and at the same time complete the effective extraction of light field (wave front) information). The application develops an integrated solution of EUV wave front information and direct " photoelectric " detection function, obtains a device prototype close to the theoretical performance limit, lays a foundation for developing a new type of EUV wave front detection system, and has important significance for developing new EUV detection system key components.

The present invention provides an N-type lateral double-diffused MOS field-effect transistor and its fabrication method. By setting a second heavily doped region and a third heavily doped region within the substrate, located in the second well region and connected to the cathode, a bidirectional N-P-N-P-N structure is formed. This achieves bidirectional ESD protection through a simple structure without the need for additional ESD protection devices. Thus, it balances ESD protection effectiveness with improved integration density. Furthermore, by setting an N-type first well region and a first heavily doped region, with the first heavily doped region located within the first well region and extending into the second well region, a shallow junction of N-type doped / P-type well is formed, significantly reducing the trigger voltage of the N-type lateral double-diffused MOS field-effect transistor.

The invention relates to a low-junction capacitance symmetric transient voltage suppressor diode and a preparation method thereof. The preparation method comprises the steps of silicon wafer cleaning, N-type doping, oxidation, photoetching, oxide layer removal, slotting corrosion, passivation, surface corrosion, electrode manufacturing, metal stripping and cutting. Wherein in the N-type doping step, POCl3 is used as a gas-phase phosphorus source, double-sided synchronous diffusion is carried out on a silicon wafer, and a shallow junction N-type region with the junction depth of 1.5-3.0 microns is formed; in the oxidation step, the silicon wafer with the shallow junction N-type region is subjected to high-temperature oxidation in an oxygen-containing atmosphere, phosphorus atoms are driven to be redistributed from the surface to the inside, a doping section with the phosphorus concentration gradually changing from the surface of the silicon wafer to the inside is formed, and a surface oxidation layer is synchronously grown. According to the preparation method disclosed by the invention, the junction capacitance is reduced, and the symmetry, the response speed and the pulse endurance capability of the bidirectional transient voltage suppression diode are improved by improving the doping uniformity.

The embodiment of the invention relates to the photovoltaic field, and discloses a preparation method of a battery piece and a photovoltaic module, and the method comprises the steps: providing a substrate, placing the substrate in a diffusion furnace tube, raising the temperature in the diffusion furnace tube from a preheated first temperature to a second temperature, carrying out pre-oxidation treatment on the surface of the substrate at the second temperature; keeping the temperature in the diffusion furnace tube at the second temperature, and introducing a doping source into the diffusion furnace tube for multiple times so as to perform diffusion deposition for multiple times; raising the temperature in the diffusion furnace tube to a third temperature, and performing high-temperature propulsion for multiple times at the third temperature; reducing the temperature in the diffusion furnace tube to the second temperature, and performing low-temperature propulsion at the second temperature; and reducing the temperature in the diffusion furnace tube to a fourth temperature so as to form a semiconductor doping layer on the surface of the substrate. According to the scheme, an ideal diffusion model of a low-surface-concentration shallow junction can be obtained, and the performance of the solar cell is improved.

The invention provides a semiconductor process method and a semiconductor device, and the method comprises the steps: a first barrier layer and a second barrier layer sequentially cover the surface of a semiconductor structure, and the first barrier layer is thinner than the second barrier layer; forming a second barrier layer on the side wall to obtain a first barrier layer on the side wall of the gate structure and the bottom of the second barrier layer; removing the second barrier layer; lDD ion implantation is carried out to form stepped shallow doping distribution; and the drain barrier layer forms a source-drain heavily doped region for mask ion implantation. According to the invention, the barrier layer is arranged for multiple times and then is locally removed to obtain the stepped barrier layer, and LDD ion implantation forms shallow doping distribution of concentration gradient change to optimize a slowly-changing junction gradient, disperse an electric field and inhibit hot carrier injection; meanwhile, the shallow doping distribution with the depth gradient change enables the deep junction to suppress the leakage current, the shallow junction to suppress the short-channel effect, and the hot carrier injection and the short-channel effect are doubly suppressed; the barrier layer material is arranged to control step distribution; and finally, setting the thickness of the barrier layer to optimize the hot carrier injection and short channel effect suppression effect.

The invention relates to the technical field of solar cells, particularly provides a boron-doped emitter, a TOPcon cell and a preparation method, and aims to solve the problem that in the prior art, a boron-doped p + emitter formed through one-time deposition cannot give consideration to the surface recombination rate and the contact performance at the same time. In order to achieve the purpose, at least two borosilicate glass layers are deposited on the front face of a silicon substrate, a silicon dioxide layer is deposited between every two adjacent borosilicate glass layers, and the molar ratio of boron to oxygen in each borosilicate glass layer is gradually increased layer by layer in the direction gradually away from the silicon substrate. According to the invention, the silicon dioxide layer is arranged, and the B / O ratio of the outer borosilicate glass layer is greater than that of the inner borosilicate glass layer, so that the surface recombination rate and the contact performance can be considered, a high surface shallow junction is formed, and the open-circuit voltage and the fill factor are greatly improved.

The invention discloses an ultra-shallow junction preparation method based on plasma doping and a semiconductor device. Ultra-shallow junction preparation is realized through a process system of surface pretreatment, low-energy plasma accurate doping, controllable rapid thermal annealing and performance characterization. Substrate impurities and an oxide layer are thoroughly removed through surface pretreatment, the injection depth is accurately controlled through low-energy plasma doping, doping element activation and diffusion suppression are both considered through rapid thermal annealing, and the quality is guaranteed in cooperation with targeted performance characterization. According to the method, the damage to the substrate is effectively reduced, the doping uniformity and the activation rate are improved, the process adaptation range is widened, the prepared semiconductor device is low in leakage current and stable in performance, and the method is suitable for batch production of high-precision miniature semiconductor devices.