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Method for manufacturing shallow junction complementary bipolar transistor

A technology of bipolar transistors and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of low withstand voltage of transistors, difficult to meet the high-precision and dynamic adjustment requirements of high-speed analog integrated circuits, and achieve the characteristics of Increase frequency, reduce leakage current, and achieve the effect of physical isolation

Inactive Publication Date: 2010-03-17
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The advantage of these processes is that the characteristic frequency is high, but when applied to high-precision analog integrated circuits, the withstand voltage of its transistors is low (BV CEO <3.0V, it is difficult to meet the high-precision and dynamic adjustment requirements of higher-voltage high-speed analog integrated circuits

Method used

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  • Method for manufacturing shallow junction complementary bipolar transistor
  • Method for manufacturing shallow junction complementary bipolar transistor
  • Method for manufacturing shallow junction complementary bipolar transistor

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Embodiment Construction

[0045] Specific embodiments of the present invention are not limited to the following description. The present invention will be further described now in conjunction with accompanying drawing.

[0046] The method of the present invention firstly utilizes silicon / silicon bonding, CMP thinning and polishing technology to obtain the required SOI material sheet, and then forms on the SOI material sheet by implanting the buried layer, decompression ultra-thin epitaxy, deep groove etching, and polysilicon backfilling. The shallow junction complementary bipolar transistor is manufactured by combining the technology of deep trench dielectric isolation and shallow isolation wall, combined with the vertical PNP of the shallow junction polysilicon emitter and the complementary bipolar process compatible with the vertical NPN.

[0047] 1. The steps of forming SOI material sheet by silicon / silicon bonding, thinning and polishing method are:

[0048] 1# liquid (NH 4 OH:H 2 o 2 :H 2 O=1...

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Abstract

The invention discloses a method for manufacturing a shallow junction complementary bipolar transistor. The main technological steps of the method are as follows: 1) forming an SOI material chip by the methods of silicon / silicon bonding, thinning and polishing; and 2) manufacturing the shallow junction complementary bipolar transistor by using the methods of deep-trench etching, deep trench isolation with polysilicon backfilling and a shallow isolation wall and combining with a longitudinal NPN pipe with a shallow junction polysilicon emitter and the complementary bipolar technology which is compatible with the longitudinal PNP pipe. The method improves the pressure resistance (BVCEO is greater than 5.0V) and the Early voltage of the complementary bipolar transistor and simultaneously takes into consideration of the characteristic frequency. The method greatly reduces the drain current of an isolation junction, and the drain current of the shallow junction complementary bipolar transistor is smaller than 10<minus 12>A. The method can be widely applied in the field of manufacture of high-speed complementary bipolar technologies.

Description

technical field [0001] The invention relates to a manufacturing method of a shallow-junction complementary bipolar transistor, which is directly applied to the manufacturing field of high-speed complementary bipolar transistors. Background technique [0002] Complementary bipolar technology (CB) has a history of more than 30 years. In the early days, PNP transistors and NPN transistors were mainly used to form a complementary structure. Around 1986, junction isolation CB technology was used. The main advantage of the CB process is that it can obtain high-frequency vertical NPN and PNP transistors with extremely small parasitic capacitance at the same time. This complementary bipolar transistor has a high characteristic frequency f under a certain current. T , so that the integrated operational amplifier can have better frequency characteristics and bandwidth characteristics under a small quiescent current. However, the complementary bipolar process is difficult to manufactu...

Claims

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Application Information

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IPC IPC(8): H01L21/84H01L21/331
Inventor 李荣强崔伟张正元
Owner NO 24 RES INST OF CETC
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