27 results about "Junction isolation" patented technology

The invention provides a semiconductor device with a PN junction and a preparation method thereof, and belongs to the technical field of semiconductor devices. The semiconductor device comprises a silicon substrate, the surface of one side of the silicon substrate in the thickness direction is provided with an emitter region covering an emitter and an isolation region formed by removing the emitter, a PN junction is formed between the emitter and the silicon substrate, the isolation region is arranged at the edge of the silicon substrate, and at least one side wall of the silicon substrate in the length direction is provided with a cutting surface. An isolation region is arranged at least close to the edge of the cutting surface in the silicon substrate, the surface height of the isolation region is lower than that of the emitter region, the isolation region and the emitter region are connected through a buffer region of a slope structure, and passivation layers cover the surfaces of the emitter, the isolation region and the buffer region. According to the invention, the structure of the isolation region is optimized, a transmission channel of carriers from the emitter region to the cutting surface is effectively cut off, and uniform coverage of the passivation layer is ensured, so that the performance of the device is optimized.

An object is to provide a technique that eliminates the need for an external circuit for enhancing the breakdown voltage. A switching element drive circuit includes a primary circuit and a secondary circuit, and an insulating element isolating the primary circuit and the secondary circuit from each other in terms of a direct current. The secondary circuit includes a semiconductor substrate, a detector provided on a portion of the semiconductor substrate, including a pn junction isolation portion, and configured to detect a voltage of a high voltage terminal, and a controller provided on a remaining portion of the semiconductor substrate and configured to control a control voltage of a semiconductor switching element based on a second signal and a detection result of the detector.

The invention provides a manufacturing method of a crimping type high-power high-voltage diode chip, and relates to the technical field of power semiconductor device manufacturing, and the method comprises the steps: forming an annular groove in the surface of a semiconductor wafer through laser grooving, and forming a circular PN junction isolation wall of a single chip in the groove in combination with a closed tube gallium-aluminum diffusion technology; carrying out boron-phosphorus double-substance diffusion in a unit cell region enclosed by the isolation wall to form a PN junction doping structure; a photoetching mask is adopted to limit an area, and a double-angle mesa structure is formed through chemical corrosion of an HF / HNO3 mixed solution; sequentially depositing a semi-insulating polycrystalline silicon layer and a double-layer glass passivation layer; performing laser cutting along the separating wall to separate the single chip; and sintering an anode molybdenum sheet on the anode surface of the chip, performing vacuum evaporation on a cathode aluminum film on the cathode surface of the chip, and alloying to form an electrode. According to the invention, the consistency and stability of chip manufacturing can be improved through the wafer-level mesa modeling and the inorganic passivation process.

The utility model provides a photoelectric converter, a sensing device and electronic equipment, and belongs to the technical field of semiconductors. The photoelectric converter includes a substrate; the plurality of photoelectric conversion units are formed in the substrate, each photoelectric conversion unit comprises a first semiconductor region and a second semiconductor region, and a PN junction is formed on a contact interface between the first semiconductor region and the second semiconductor region; each isolation structure is arranged between every two adjacent photoelectric conversion units, each isolation structure comprises a deep trench isolation structure, and each deep trench isolation structure comprises a first trench extending into the substrate from the surface of the substrate, and an insulating material and a semiconductor material which are filled in the first trench. According to the invention, crosstalk between adjacent photoelectric conversion units can be reduced.

The present disclosure generally relates to semi-floating junction isolation. In an example, a semiconductor device includes an epitaxial layer, a buried layer, a deep well, a drift well, a contact well, and a contact region. The buried layer, deep well, drift well, contact well, and contact region each have a conductivity type opposite from a conductivity type of the epitaxial layer. The buried layer is spaced apart from a top surface of the epitaxial layer. The deep well extends in the epitaxial layer and touches the buried layer. The deep well laterally encircles an active area over the buried layer. The drift well extends in the epitaxial layer to a depth and extends laterally from the deep well towards the active area. The contact well extends in the epitaxial layer to a greater depth and touching the drift well. The contact region extends in the contact well.

An edge-isolated sliced cell and a manufacturing method therefor. The sliced cell comprises a silicon wafer (1); the front surface of the silicon wafer (1) is provided with a cell working area covering a boron emitter (2) and a pn junction isolation area (3) formed by removing all or part of the boron emitter (2); a front electrode (5) is arranged in the cell working area; the side surface of the silicon wafer (1) is provided with a laser slicing area (12) of which surface damage is removed; the pn junction isolation area (3) is located between the front electrode (5) and the laser slicing area (12); the pn junction isolation area (3) can cut off a transmission channel of minority carriers from the cell working area to the laser slicing area (12); and passivation layers are arranged on surfaces of the pn junction isolation area (3) and the laser slicing area (12). By forming a pn junction-free isolation structure between a laser slicing area (12) and a front electrode (5), and the laser slicing area (12) is subjected to passivation treatment, so that the technical effect of improving the efficiency of the sliced cell is achieved.

The invention discloses a method for improving voltage resistance of a transverse transistor device by adopting irradiation. The method comprises the following steps: providing a silicon wafer as a substrate; forming a buried layer and a base deep well region on the substrate; pN junction isolation structures are formed on the two sides of the buried layer respectively, and a base deep junction well region connected with one end of the buried layer is formed; isolation grooves are formed between the emitter region and the collector regions on the two sides; filling an isolation medium in the isolation groove, and forming a thick field oxygen isolation structure on the base deep well region; completing the manufacturing of a base electrode, an emitter electrode and a collector electrode; a surface of the lateral transistor device is irradiated. According to the invention, a longitudinal base region current channel is formed through the isolation groove, electric leakage between an emitter and a collector of the device is greatly reduced, surface inversion of the device is reduced through irradiation of the surface of the transverse transistor device, CE voltage resistance of the device is further improved while CE spacing of the device is reduced, and the device is suitable for large-scale production. Therefore, the integration level of the transverse transistor high-power device can be improved.

Apparatuses that include a junction-isolated semiconductor strain gauge and methods for manufacturing a junction-isolated semiconductor strain gauge are disclosed. In a particular embodiment, an apparatus comprises a silicon chip that includes a silicon substrate and a semiconductor strain gauge. In this embodiment, the semiconductor strain gauge includes a plurality of resistors formed by locally doping the silicon substrate and biasing the silicon substrate such that the resistors of the plurality of resistors are junction-isolated. The silicon chip also includes a field shield layer to isolate an output signal of the semiconductor strain gauge from external electrical fields.

Disclosed are an interposer and a chip package structure. The interposer may include: at least one signal transmission vias; at least one insulator isolation rings, one of said insulator isolation rings encircling one of said signal transmission vias; and at least one reverse-biased PN junction isolation rings, one of said reverse-biased PN junction isolation rings surrounding at least one of said insulator isolation rings, and the reverse-biased PN junction isolation ring including a semiconductor ring of a first conductivity type and a semiconductor ring of a second conductivity type from inside to outside, the semiconductor ring of the second conductivity type is connected to a bias potential.

The invention discloses a medium-voltage flame-retardant B1-level fire-resistant power cable, and relates to the technical field of cables, a plurality of transmission wire cores are arranged on the inner side of a silicone rubber outer protective tube at equal intervals, a plurality of embedded insulating sheets are clamped on the outer sides of the transmission wire cores at equal intervals, and pressing mica tapes are wound at the outer side ends of the embedded insulating sheets; the outer side end of the pressing and pasting mica tape is bonded with an inner limiting semi-conductive sheet, the side end of the inner limiting semi-conductive sheet is provided with a card inserting convex fixing plate, the side end of the card inserting convex fixing plate is sleeved with a pressing and punching concave combination block, and an arc pasting pressing and connecting sleeve is installed between the card inserting convex fixing plate and the pressing and punching concave combination block. In order to solve the problems that a flame-retardant layer of the cable is thin and the cable cannot actively inhibit the combustion environment, through multi-section sintering isolation and active inhibition processing, the control processing of the cable on the environment is improved, so that the fire-resistant and flame-retardant effects of the cable are improved and the fire-resistant time of the cable is prolonged under the environments of long-time burning and short-time high temperature.

The present invention discloses a low dark current image sensor pixel structure, which includes a photodiode, a transfer transistor, a floating diffusion node, a reset transistor, a source follower transistor, a row selection transistor, a power supply, and a pixel output disposed in a semiconductor substrate; a reverse PN junction isolation 301 is adopted between adjacent photodiodes, and a trapezoidal shallow trench isolation 205 is added between the photodiodes, so that stress is concentrated in the obtuse angle structure formed at the four corners of the photodiode. By optimizing the pixel layout design, and in the pixel process, a low-stress silicon nitride film is used to replace the high-stress silicon nitride film and the thickness of the silicon nitride film is reduced to reduce the stress on the photodiode. The dislocation defects caused by high stress in the active region of the photodiode are reduced, thereby reducing the dark current generated by the pixel and improving the performance of the image sensor.

The present disclosure relates generally to semi-floating junction isolation. In an example, a semiconductor device includes an epitaxial layer (106), a buried layer (108), a deep well (112), a drift well (122, 224), a contact well (120, 222), and a contact region (126). The buried layer (108), the deep well (112), the drift wells (122, 224), the contact wells (120, 222), and the contact region (126) each have a conductivity type opposite to a conductivity type of the epitaxial layer (106). The buried layer (108) is spaced apart from a top surface of the epitaxial layer (106). The deep well (112) extends in the epitaxial layer (106) and touches the buried layer (108). And the deep well (112) transversely surrounds the active region above the buried layer (108). The drift well (122, 224) extends to a depth in the epitaxial layer (106) and extends laterally from the deep well (112) toward the active region. The contact well (120, 222) extends to a greater depth in the epitaxial layer (106) and touches the drift well (122, 224). The contact region (126) extends in the contact well (120, 222).

The application discloses a high-speed HBT device with an in-situ heavily doped epitaxial emitter and a manufacturing method thereof, and the device manufacturing method comprises the following steps: providing a first SEG self-alignment front structure; forming an HBT base region and an E-B junction isolation medium on the first SEG self-alignment front structure; depositing a heavily doped emitter thin film in-situ; performing physical etching on the emitter thin film; performing a rapid thermal annealing process; and performing a metallization process to obtain the HBT device. In the application, the process scheme of As heavy doping in-situ deposition and then re-etching is adopted, the As doping concentration in the epitaxial growth process and the capacity demand are effectively considered, the difficult problem of eliminating the As emitter hole at the single crystal-polycrystal interface is successfully solved, and therefore, the As heavily doped HBT device emitter thin film material with a smooth surface and high doping concentration can be obtained.

The invention provides an ultrahigh-voltage isolating ring structure and a manufacturing method thereof. The structure is composed of a plurality of high-voltage laterally diffused metal oxide semiconductors. In order to solve the problem of punch-through breakdown caused by junction isolation on a high-resistivity substrate in the prior art, a deep trench isolation structure is arranged between the high-voltage laterally diffused metal oxide semiconductors or between the high-voltage laterally diffused metal oxide semiconductors and a device of a high-voltage circuit. The deep trench isolation structure is filled with a dielectric material, a leakage path in the substrate is cut off in a physical isolation mode, the punch-through breakdown problem is fundamentally solved, the isolation voltage endurance capability and the device reliability in a high-voltage circuit are remarkably improved, the device area can be optimized, and the deep trench isolation structure is suitable for a high-voltage integrated circuit of 1,000 V or above.

The present invention provides a deep trench uniform field isolation device for a high-voltage integrated circuit and a manufacturing method thereof. A longitudinal floating field plate is formed by carving a groove between an LDMOS region and a high-voltage circuit and then filling it with a dielectric and polysilicon. The longitudinal floating field plate is evenly distributed on a third dielectric oxide layer to achieve isolation between the LDMOS region and the high-voltage circuit region, saving area compared to traditional PN junction isolation. Furthermore, the longitudinal floating field plate uses a first metal strip to correlate the potential of the high-voltage junction terminal with the potential of the LDMOS, achieving uniform potential distribution, achieving stronger voltage coupling, and improving withstand voltage.

The application provides a manufacturing method of a crimping type high-power high-voltage diode chip, and relates to the technical field of power semiconductor device manufacturing technology, which forms a ring-shaped groove on the surface of a semiconductor wafer through laser grooving, and forms a single chip circular PN junction isolation wall in the groove by combining a closed tube gallium aluminum diffusion process; boron and phosphorus double quality diffusion is carried out in the single cell area surrounded by the isolation wall to form a PN junction doping structure; a double-angle mesa structure is formed by chemical corrosion of an HF / HNO3 mixed solution through a photolithography mask limited area; a semi-insulating polysilicon layer and a double-layer glass passivation layer are sequentially deposited; a single chip is separated by laser cutting along the isolation wall; an anode molybdenum sheet is sintered on the anode surface of the chip, and an anode aluminum film is vacuum evaporated on the cathode surface of the chip and alloyed to form an electrode. The application can improve the consistency and stability of chip manufacturing through wafer-level mesa modeling and inorganic passivation process.

The present disclosure relates to a p-type bulk silicon memory device, and more particularly, to a technology that implements stable and reliable memory operation by utilizing positive feedback and negative feedback mechanisms based on a triple-well structure and a p-n junction isolation layer, and provides low power consumption and high integration density without a capacitor. In particular, the present disclosure meets the requirements of next-generation memory devices and provides solutions suitable for various electronic devices through miniaturization and high integration.

The application discloses a high-temperature pressure sensing chip based on a single crystal silicon wafer and a three-dimensional integration method, and a manufacturing process of the chip comprises a force sensing resistor manufacturing step, an insulation isolation step, a high-temperature-resistant electrode and interconnection manufacturing step, a pressure-sensitive diaphragm etching step and a bonding step. The application uses a method of etching an insulation isolation groove around the force sensing resistor, filling and covering an insulation layer and precisely etching a lower layer bulk silicon of the force sensing resistor, avoids the problem of failure of a traditional single crystal silicon pn junction isolation high-temperature leakage current, does not depend on expensive materials such as SOI wafers and silicon carbide wafers, uses a general single crystal silicon wafer to realize mutual insulation isolation between Wheatstone bridge force sensing resistors, and meets high-temperature working requirements. The proposed air-tight leadless bonding method based on a through silicon via further improves the reliability of the pressure sensing chip. Meanwhile, the manufacturing method is fully compatible with a silicon-based CMOS process, and on-chip system integration can be realized.

The present disclosure relates to semiconductor structures and, more particularly, to a single-photon avalanche diode with isolated junctions and methods of manufacture. The structure includes a first p-n junction in a semiconductor material; and a second p-n junction in a second semiconductor material isolated from the first p-n junction by a buried insulator layer.

A semiconductor device includes a high voltage region formed on a semiconductor substrate; a junction isolation region surrounding the high voltage region; a Schottky diode configured to supply a forward current to the high voltage region; a silicon controlled rectifier (SCR) region formed between the Schottky diode and the high voltage region; a drain region, a gate region and a source region formed in the SCR region; a P-type isolation region formed between the Schottky diode and the source region; a first SCR including a first N+ region and a first P+ region in contact with each other and formed in the drain region; a second SCR comprising a second N+ region and a second P+ region in contact with each other and formed in the gate region; and a third SCR comprising a third N+ region and a third P+ region in contact with each other and formed in the P-type isolation region.

A semiconductor device includes a junction isolation region, a Schottky diode including an n-type buried layer (NBL), an anode electrode, and a cathode electrode formed on the NBL, and a guard ring surrounding the Schottky diode. A source electrode of the junction isolation region is electrically connected to the cathode electrode of the Schottky diode.

This invention provides an edge-isolated sliced ​​solar cell and photovoltaic module, comprising a silicon wafer. The front side of the silicon wafer has a cell working area covering a boron emitter and a pn junction isolation area formed by removing the boron emitter. A front electrode is disposed within the cell working area. At least one side of the silicon wafer along its length has a sliced ​​area. The pn junction isolation area is located between the front electrode and the sliced ​​area. The surface of the pn junction isolation area is covered with a first passivation layer, and the surface of the sliced ​​area is covered with a second passivation layer. This invention forms a pn junction-free isolation structure between the sliced ​​area and the electrode, cutting off the transport path of minority carriers from the cell working area to the sliced ​​area. This effectively suppresses the influence of carrier recombination dark current in the sliced ​​area on the cell working area. Combined with the first passivation layer of the pn junction isolation area and the second passivation layer of the sliced ​​area, recombination and leakage at the cell cutting edge can be essentially eliminated, thereby improving the efficiency of the sliced ​​solar cell.

A SiC trench MOS device structure with built-in polysilicon heterojunction diode relates to the field of power semiconductor, comprising source metal, drain metal, substrate, N-drift region, P-shielding region, isolation oxide layer, gate oxide layer, polysilicon source, polysilicon gate, current spreading layer, P-base region, N-source region, P-plus region. One end of the substrate is in contact with the drain metal, and the other end is in contact with the drift layer; the current spreading layer is arranged on the N-drift region; the P-base region is arranged on the current spreading layer; the N-source region and the P-plus region are arranged side by side on the P-base region; a plurality of trenches are formed in the base region and extend vertically into the drift layer; the left side of the trench is filled with polysilicon gate, and the right side is filled with polysilicon source; the left side, the right side and the bottom of the polysilicon gate are in contact with the gate oxide layer; the left side of the polysilicon source is in contact with the gate oxide layer; the polysilicon source is in contact with the N-drift region to form a heterojunction. The isolation oxide layer is in contact with the source metal, the trench and the N-source region; the trench is in contact with the N-source region. The application improves the switching speed and improves the reverse recovery charge.

The utility model discloses a ka-band low-loss high-power microstrip double-junction isolator which is sequentially provided with a base (1), a microwave ferrite substrate (2), a thin-film resistance layer (3), a microstrip circuit (4) and a permanent magnet (5) from bottom to top. The microstrip circuit (4) comprises a pair of main body discs (41), each main body disc (41) is connected with a pair of branch leads (42) and a central lead (43), and the two main body discs (41) are connected through the branch leads; a notch (41a) is formed in the outer edge of the main body disc (41); a pin of the central lead (43) is connected to the thin-film resistor layer (3) and comprises a straight section (43a), a 1 / 4 arc-shaped section (43b), a horizontal extension section (43c) and an arc-shaped bent section (43d); and the permanent magnet (5) is connected to the main body disc (41). The utility model has the advantages that the isolation performance is effectively improved, the miniaturization is maintained, and meanwhile, the high-power processing capability and the low-loss function are realized.

The invention provides a photoelectric converter, a sensing device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The photoelectric converter includes a substrate; the plurality of photoelectric conversion units are formed in the substrate, each photoelectric conversion unit comprises a first semiconductor region and a second semiconductor region, and a PN junction is formed on a contact interface between the first semiconductor region and the second semiconductor region; each isolation structure is arranged between every two adjacent photoelectric conversion units, each isolation structure comprises a deep trench isolation structure, and each deep trench isolation structure comprises a first trench extending into the substrate from the surface of the substrate, and an insulating material and a semiconductor material which are filled in the first trench. According to the invention, crosstalk between adjacent photoelectric conversion units can be reduced.

The invention relates to the technical field of photoelectric couplers, in particular to a silicon-based monolithic integrated photoelectric coupler based on silicon dioxide isolation. According to the invention, the SiO2 layer is prepared right above the silicon substrate, the luminescent device and the photosensitive device are embedded in the SiO2 layer, and a medium isolation belt is formed between the luminescent device and the photosensitive device through SiO2, so that a transverse on-chip optocoupler structure is realized; on one hand, the maximum voltage limitation of STI or PN junction isolation on the silicon substrate is avoided; on the other hand, the light emitting device and the light sensing triode are horizontally arranged on the two sides of the isolation strip, the light transmission path is plane propagation through the transverse SiO2 isolation strip, compared with a vertical structure, the middle SiO2 isolation strip can be made to be wider in transverse propagation distance and is not limited, therefore, the isolation voltage can be made to be very high, and light loss caused by longitudinal transmission is further avoided. According to the invention, high electrical isolation between the light-emitting device and the light-sensing device is realized by innovating the device structure, and light loss is considered at the same time.

The present invention provides a preparation method for improving the junction isolation characteristics of an N-type piezoresistive sensor, characterized by comprising the following steps: S1: performing photolithography, high-dose phosphorus implantation, and debonding on a P-type silicon wafer to form a heavily doped region; S2: performing photolithography, phosphorus implantation according to design requirements, and debonding to form a varistor; S3: performing photolithography, boron implantation, and debonding to form a P-type isolation ring structure 6; S4: performing annealing and oxidation to form an insulating layer; S5: performing photolithography, etching, and debonding to form contact holes in the insulating layer; and S6: performing sputtering, photolithography, etching, and debonding to form metal leads. The present invention has simple steps and is easy to implement. The isolation ring effectively blocks the electron migration channel between the N-type piezoresistive sensor and other functional ports, reducing leakage current and improving product performance and reliability.