14 results about "Junction isolation" patented technology

The present disclosure generally relates to semi-floating junction isolation. In an example, a semiconductor device includes an epitaxial layer, a buried layer, a deep well, a drift well, a contact well, and a contact region. The buried layer, deep well, drift well, contact well, and contact region each have a conductivity type opposite from a conductivity type of the epitaxial layer. The buried layer is spaced apart from a top surface of the epitaxial layer. The deep well extends in the epitaxial layer and touches the buried layer. The deep well laterally encircles an active area over the buried layer. The drift well extends in the epitaxial layer to a depth and extends laterally from the deep well towards the active area. The contact well extends in the epitaxial layer to a greater depth and touching the drift well. The contact region extends in the contact well.

An edge-isolated sliced cell and a manufacturing method therefor. The sliced cell comprises a silicon wafer (1); the front surface of the silicon wafer (1) is provided with a cell working area covering a boron emitter (2) and a pn junction isolation area (3) formed by removing all or part of the boron emitter (2); a front electrode (5) is arranged in the cell working area; the side surface of the silicon wafer (1) is provided with a laser slicing area (12) of which surface damage is removed; the pn junction isolation area (3) is located between the front electrode (5) and the laser slicing area (12); the pn junction isolation area (3) can cut off a transmission channel of minority carriers from the cell working area to the laser slicing area (12); and passivation layers are arranged on surfaces of the pn junction isolation area (3) and the laser slicing area (12). By forming a pn junction-free isolation structure between a laser slicing area (12) and a front electrode (5), and the laser slicing area (12) is subjected to passivation treatment, so that the technical effect of improving the efficiency of the sliced cell is achieved.

Apparatuses that include a junction-isolated semiconductor strain gauge and methods for manufacturing a junction-isolated semiconductor strain gauge are disclosed. In a particular embodiment, an apparatus comprises a silicon chip that includes a silicon substrate and a semiconductor strain gauge. In this embodiment, the semiconductor strain gauge includes a plurality of resistors formed by locally doping the silicon substrate and biasing the silicon substrate such that the resistors of the plurality of resistors are junction-isolated. The silicon chip also includes a field shield layer to isolate an output signal of the semiconductor strain gauge from external electrical fields.

The invention discloses a medium-voltage flame-retardant B1-level fire-resistant power cable, and relates to the technical field of cables, a plurality of transmission wire cores are arranged on the inner side of a silicone rubber outer protective tube at equal intervals, a plurality of embedded insulating sheets are clamped on the outer sides of the transmission wire cores at equal intervals, and pressing mica tapes are wound at the outer side ends of the embedded insulating sheets; the outer side end of the pressing and pasting mica tape is bonded with an inner limiting semi-conductive sheet, the side end of the inner limiting semi-conductive sheet is provided with a card inserting convex fixing plate, the side end of the card inserting convex fixing plate is sleeved with a pressing and punching concave combination block, and an arc pasting pressing and connecting sleeve is installed between the card inserting convex fixing plate and the pressing and punching concave combination block. In order to solve the problems that a flame-retardant layer of the cable is thin and the cable cannot actively inhibit the combustion environment, through multi-section sintering isolation and active inhibition processing, the control processing of the cable on the environment is improved, so that the fire-resistant and flame-retardant effects of the cable are improved and the fire-resistant time of the cable is prolonged under the environments of long-time burning and short-time high temperature.

The present disclosure relates generally to semi-floating junction isolation. In an example, a semiconductor device includes an epitaxial layer (106), a buried layer (108), a deep well (112), a drift well (122, 224), a contact well (120, 222), and a contact region (126). The buried layer (108), the deep well (112), the drift wells (122, 224), the contact wells (120, 222), and the contact region (126) each have a conductivity type opposite to a conductivity type of the epitaxial layer (106). The buried layer (108) is spaced apart from a top surface of the epitaxial layer (106). The deep well (112) extends in the epitaxial layer (106) and touches the buried layer (108). And the deep well (112) transversely surrounds the active region above the buried layer (108). The drift well (122, 224) extends to a depth in the epitaxial layer (106) and extends laterally from the deep well (112) toward the active region. The contact well (120, 222) extends to a greater depth in the epitaxial layer (106) and touches the drift well (122, 224). The contact region (126) extends in the contact well (120, 222).

The application discloses a high-speed HBT device with an in-situ heavily doped epitaxial emitter and a manufacturing method thereof, and the device manufacturing method comprises the following steps: providing a first SEG self-alignment front structure; forming an HBT base region and an E-B junction isolation medium on the first SEG self-alignment front structure; depositing a heavily doped emitter thin film in-situ; performing physical etching on the emitter thin film; performing a rapid thermal annealing process; and performing a metallization process to obtain the HBT device. In the application, the process scheme of As heavy doping in-situ deposition and then re-etching is adopted, the As doping concentration in the epitaxial growth process and the capacity demand are effectively considered, the difficult problem of eliminating the As emitter hole at the single crystal-polycrystal interface is successfully solved, and therefore, the As heavily doped HBT device emitter thin film material with a smooth surface and high doping concentration can be obtained.

The invention provides an ultrahigh-voltage isolating ring structure and a manufacturing method thereof. The structure is composed of a plurality of high-voltage laterally diffused metal oxide semiconductors. In order to solve the problem of punch-through breakdown caused by junction isolation on a high-resistivity substrate in the prior art, a deep trench isolation structure is arranged between the high-voltage laterally diffused metal oxide semiconductors or between the high-voltage laterally diffused metal oxide semiconductors and a device of a high-voltage circuit. The deep trench isolation structure is filled with a dielectric material, a leakage path in the substrate is cut off in a physical isolation mode, the punch-through breakdown problem is fundamentally solved, the isolation voltage endurance capability and the device reliability in a high-voltage circuit are remarkably improved, the device area can be optimized, and the deep trench isolation structure is suitable for a high-voltage integrated circuit of 1,000 V or above.

The application provides a manufacturing method of a crimping type high-power high-voltage diode chip, and relates to the technical field of power semiconductor device manufacturing technology, which forms a ring-shaped groove on the surface of a semiconductor wafer through laser grooving, and forms a single chip circular PN junction isolation wall in the groove by combining a closed tube gallium aluminum diffusion process; boron and phosphorus double quality diffusion is carried out in the single cell area surrounded by the isolation wall to form a PN junction doping structure; a double-angle mesa structure is formed by chemical corrosion of an HF / HNO3 mixed solution through a photolithography mask limited area; a semi-insulating polysilicon layer and a double-layer glass passivation layer are sequentially deposited; a single chip is separated by laser cutting along the isolation wall; an anode molybdenum sheet is sintered on the anode surface of the chip, and an anode aluminum film is vacuum evaporated on the cathode surface of the chip and alloyed to form an electrode. The application can improve the consistency and stability of chip manufacturing through wafer-level mesa modeling and inorganic passivation process.

The present disclosure relates to a p-type bulk silicon memory device, and more particularly, to a technology that implements stable and reliable memory operation by utilizing positive feedback and negative feedback mechanisms based on a triple-well structure and a p-n junction isolation layer, and provides low power consumption and high integration density without a capacitor. In particular, the present disclosure meets the requirements of next-generation memory devices and provides solutions suitable for various electronic devices through miniaturization and high integration.

The application discloses a high-temperature pressure sensing chip based on a single crystal silicon wafer and a three-dimensional integration method, and a manufacturing process of the chip comprises a force sensing resistor manufacturing step, an insulation isolation step, a high-temperature-resistant electrode and interconnection manufacturing step, a pressure-sensitive diaphragm etching step and a bonding step. The application uses a method of etching an insulation isolation groove around the force sensing resistor, filling and covering an insulation layer and precisely etching a lower layer bulk silicon of the force sensing resistor, avoids the problem of failure of a traditional single crystal silicon pn junction isolation high-temperature leakage current, does not depend on expensive materials such as SOI wafers and silicon carbide wafers, uses a general single crystal silicon wafer to realize mutual insulation isolation between Wheatstone bridge force sensing resistors, and meets high-temperature working requirements. The proposed air-tight leadless bonding method based on a through silicon via further improves the reliability of the pressure sensing chip. Meanwhile, the manufacturing method is fully compatible with a silicon-based CMOS process, and on-chip system integration can be realized.

The present disclosure relates to semiconductor structures and, more particularly, to a single-photon avalanche diode with isolated junctions and methods of manufacture. The structure includes a first p-n junction in a semiconductor material; and a second p-n junction in a second semiconductor material isolated from the first p-n junction by a buried insulator layer.

A semiconductor device includes a high voltage region formed on a semiconductor substrate; a junction isolation region surrounding the high voltage region; a Schottky diode configured to supply a forward current to the high voltage region; a silicon controlled rectifier (SCR) region formed between the Schottky diode and the high voltage region; a drain region, a gate region and a source region formed in the SCR region; a P-type isolation region formed between the Schottky diode and the source region; a first SCR including a first N+ region and a first P+ region in contact with each other and formed in the drain region; a second SCR comprising a second N+ region and a second P+ region in contact with each other and formed in the gate region; and a third SCR comprising a third N+ region and a third P+ region in contact with each other and formed in the P-type isolation region.

This invention provides an edge-isolated sliced ​​solar cell and photovoltaic module, comprising a silicon wafer. The front side of the silicon wafer has a cell working area covering a boron emitter and a pn junction isolation area formed by removing the boron emitter. A front electrode is disposed within the cell working area. At least one side of the silicon wafer along its length has a sliced ​​area. The pn junction isolation area is located between the front electrode and the sliced ​​area. The surface of the pn junction isolation area is covered with a first passivation layer, and the surface of the sliced ​​area is covered with a second passivation layer. This invention forms a pn junction-free isolation structure between the sliced ​​area and the electrode, cutting off the transport path of minority carriers from the cell working area to the sliced ​​area. This effectively suppresses the influence of carrier recombination dark current in the sliced ​​area on the cell working area. Combined with the first passivation layer of the pn junction isolation area and the second passivation layer of the sliced ​​area, recombination and leakage at the cell cutting edge can be essentially eliminated, thereby improving the efficiency of the sliced ​​solar cell.

A SiC trench MOS device structure with built-in polysilicon heterojunction diode relates to the field of power semiconductor, comprising source metal, drain metal, substrate, N-drift region, P-shielding region, isolation oxide layer, gate oxide layer, polysilicon source, polysilicon gate, current spreading layer, P-base region, N-source region, P-plus region. One end of the substrate is in contact with the drain metal, and the other end is in contact with the drift layer; the current spreading layer is arranged on the N-drift region; the P-base region is arranged on the current spreading layer; the N-source region and the P-plus region are arranged side by side on the P-base region; a plurality of trenches are formed in the base region and extend vertically into the drift layer; the left side of the trench is filled with polysilicon gate, and the right side is filled with polysilicon source; the left side, the right side and the bottom of the polysilicon gate are in contact with the gate oxide layer; the left side of the polysilicon source is in contact with the gate oxide layer; the polysilicon source is in contact with the N-drift region to form a heterojunction. The isolation oxide layer is in contact with the source metal, the trench and the N-source region; the trench is in contact with the N-source region. The application improves the switching speed and improves the reverse recovery charge.