The present invention discloses a junction terminal of a power
transistor, comprising a
dielectric layer, a plurality of field limiting ring groups, and a plurality of field plates corresponding to the field limiting ring groups; the
projected area of the field plates on the
dielectric layer is larger than the
projected area of the field limiting ring groups on the
dielectric layer; wherein the field limiting ring groups comprise a main field limiting ring and a plurality of
auxiliary field limiting rings; the main field limiting ring is connected to the corresponding field plate through a
contact hole of the
dielectric layer, and the
auxiliary field limiting ring is isolated from the corresponding field plate through the
dielectric layer. In this way, a field plate, a main field limiting ring, and a plurality of
auxiliary field limiting rings form a
composite structure, and under the constraint of the same blocking
voltage, the number of field plates is smaller, the number of gaps between the field plates is also smaller, and the terminal
exposure area is reduced accordingly. In the subsequent
chip process, packaging process, and external environment, the charge entering the
dielectric layer through these gaps is reduced as much as possible, so as to avoid the destruction of the
electric field distribution of the junction terminal due to excessive accumulation of charge, and prevent the
voltage resistance of the power
transistor from being reduced.