92results about "Pulse technique" patented technology

The invention provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, and relates to the technical field of circuits, the frequency divider comprises a master latch and a slave latch; each of the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross coupling pair and a load resistor pair; the current source is connected with the first current branch and the second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, the first current branch is provided with a first switching tube, and the second current branch is provided with a second switching tube and an adjustable resistor unit which are connected in series. Thus, the adjustable resistor unit is configured on the second current branch, association between the resistance value of the adjustable resistor unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustability, and frequency requirements of different scenes are met by adjusting the resistance value of the adjustable resistor unit and adjusting the self-resonant frequency of the frequency divider.

The invention discloses a detection equipment data synchronization method and device based on optical pulse coding counting. The method comprises the following steps: collecting a pulse signal output by a pulse encoder; the pulse encoder is mounted on the detection vehicle; according to a preset frequency division coefficient, performing frequency division on the pulse signal to generate frequency division pulse signals corresponding to the number of frequency division pulses; the preset frequency division coefficient is determined according to the sampling interval requirement of each detection device; the detection equipment is mounted on the detection vehicle; the number of the frequency division pulses corresponds to the number of the detection devices; the frequency division pulse signals corresponding to the frequency division pulse number are input into an optical switch for photoelectric signal conversion, and optical signals corresponding to the detection equipment are generated; according to the optical signal, detection data synchronization is carried out on the detection equipment corresponding to the optical signal, the accuracy of data synchronization of the detection equipment can be improved, and resource waste is avoided.

The application discloses an ultra-wideband reconfigurable injection locking multi-mode single-ended input / output frequency divider circuit, comprising an input unit, a frequency division circuit connected with the input unit, and an output unit connected with the frequency division circuit, wherein the frequency division circuit comprises an injection locking two-frequency division circuit and an injection locking three-frequency division circuit; the input unit utilizes a balun structure circuit, so that the injection locking two-frequency division circuit and the injection locking three-frequency division circuit are the same single-ended input; and the output unit utilizes a Multi-tank resonant network structure to realize single-ended output of two / three frequency division modes. The application can realize better efficacy, ultra-wideband performance, lower cost and easy integration in the design of a wideband millimeter wave phase-locked loop chip.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

The invention relates to a frequency division clock circuit detection method and device, computer equipment, a medium and a product. The method comprises the following steps: acquiring a detection target set of a frequency division clock circuit to be detected; the detection target set comprises each detection target; determining a detection template corresponding to each detection target in each candidate detection template; extracting a clock information set corresponding to the to-be-detected frequency division clock from the to-be-detected function module, and updating each detection template according to the clock information set to obtain detection data; detecting the to-be-detected frequency division clock according to the detection data to obtain a detection result of the to-be-detected frequency division clock; the detection result is used for positioning an abnormal reason of the to-be-detected functional module. By adopting the method, the problem positioning accuracy can be improved.

This invention provides a pulse voltage regulation circuit, comprising: a pulse control module and a reference voltage regulation module; the pulse control module is used to generate a set of M switching control signals according to the number of continuously input pulse signals; the reference voltage regulation module is connected to the output terminal of the pulse control module and is used to select a resistor voltage division ratio according to the M switching control signals, and to divide the bandgap voltage according to the selected resistor voltage division ratio to generate a reference voltage output; wherein, M = 2 N N is an integer greater than or equal to 1. The pulse voltage regulation circuit provided by this invention solves the problem of existing voltage regulation schemes adjusting the output voltage by changing the resistance value of external resistors.

The embodiment of the invention provides a wide dynamic range ion pulse threshold adaptive counting method and circuit, and the method comprises the steps: a first end of an electron multiplier is connected with an ion signal, a second end is connected with an input end of an amplification circuit, an output end is connected with a first end of a baseline extraction module, and a second end is connected with a first end of a baseline smoothing module; the second end is connected with the input end of the comparison circuit and the output end is connected with the counting circuit; the electron multiplier is used for converting the ion signal into a current pulse; the amplifying circuit is used for converting the current pulse into a voltage pulse; the baseline extraction module is used for extracting a voltage pulse baseline to obtain a baseline signal; the baseline smoothing module is used for smoothing the baseline signal to obtain a smoothed signal; the comparison circuit is used for dynamically determining a self-adaptive threshold value based on the smooth signal, comparing the voltage pulse with the self-adaptive threshold value and outputting a comparison signal; and the counting circuit is used for pulse counting to obtain the number of target pulses. Therefore, the counting accuracy and the counting upper limit are improved.

There is described a computer-implemented method of operating a counter, the method comprising: i) performing a counting operation, wherein the counting operation is done in a bit-wise manner, in particular using Gray code; ii) splitting the counting operation using a wear levelling; and iii) performing an error correction scheme with respect to the counting operation using a majority voting.

The application relates to a time-domain temperature sensor based on MOSFET temperature sensing, and belongs to the temperature sensor field. The temperature sensor comprises a temperature sensing unit and a frequency digital converter connected in sequence. The frequency digital converter comprises a voltage-controlled oscillator and a counter. The temperature sensor senses the external temperature through the temperature sensing unit, converts a physical signal into an analog signal, converts the analog signal into a frequency signal through the voltage-controlled oscillator, inputs the frequency signal into the counter, and reads out a digital code value representing temperature information from the counter. Compared with a traditional temperature sensor, the temperature sensor has the advantages of low power consumption, small area, simple structure and the like.

An electronic system including: a first electronic device including a sender that is configured to transmit data; and a second electronic device including a receiver that is configured to receive the data, wherein the sender is configured to: transmit a clock signal, an enable signal, and a heartbeat signal to the receiver; update a sending count value in response to the clock signal and the enable signal; and generate the heartbeat signal when the sending count value is a first value, and wherein the receiver is configured to: update a receiving count value in response to the clock signal and the enable signal; and generate an error signal when the receiving count value does not have the first value upon receipt of the heartbeat signal.

Overvoltage and overcurrent protection switch. This description relates to an overvoltage and overcurrent protection switch (210) comprising: - a first NMOS transistor (T211) adapted to receive a first voltage across its conduction terminals; - a second NMOS transistor (T212) comprising a source terminal connected to a source terminal of said first transistor (T211), and adapted to receive a second voltage across its conduction terminals that is lower than the first voltage; and - a third NMOS transistor (T213) comprising a source terminal connected to a source terminal of said first transistor (T211), and adapted to receive said second voltage across its conduction terminals. Figure for the abbreviation: Fig. 2

The application belongs to the signal reading part in the circuit system, and relates to a digital signal driving circuit and a driving method with multi-channel input and single-channel output. The driving circuit comprises an enabling pulse generating circuit, a time sequence generating circuit and m signal transmission circuits. The enabling pulse generating circuit has one clock signal input end, one enabling pulse signal input end and n column-level circuit output switch control signal output ends. The time sequence generating circuit has k column-level circuit output switch control signal input ends and k signal transmission control time sequence output ends. Each signal transmission circuit has n column-level circuit signal input ends, n column-level circuit output switch control signal input ends, k signal transmission control time sequence input ends and one single-tap data output end. In one signal transmission circuit, n columns of signals are divided into k sections for driving respectively, and each section has j columns of reading circuits, so that multi-channel input and single-channel output of single-tap signal transmission from the column-level circuit are realized.

The invention relates to a charging device (1) comprising at least one grid connection (2) for an alternating voltage (3), a power factor correction circuit (5) for each grid connection (2), n DC / DC converters (6) connected in parallel, wherein n > 2, and a control device (7), wherein the control device (7) is configured to operate the DC / DC converters (6), wherein the control device (7) is further configured to distribute power non-uniformly to the DC / DC converters (6) depending on the power requirements and parameters of the switching elements (S) of the DC / DC converters (6).

A computer-implemented method of operating a counter is described, the method comprising: i) performing a counting operation, where the counting operation is performed in a bitwise manner, in particular using Gray codes; ii) segmenting the counting operation using wear leveling; and iii) performing an error correction scheme for the count operation using majority voting.

A button mechanism is provided, including a button element, a magnet connected to the button, a hollow tube, a first coil, and a second coil. The first and second coils are disposed on the tube. When the first coil generates a first magnetic field, the magnet is magnetically attracted by the first coil, and the button element is positioned in the first position. When the second coil generates a second magnetic field, the magnet is attracted by the second coil, and the button element is positioned in the second position.

There is described a computer-implemented method of operating a counter, where the method includes performing a counting operation in a bit-wise manner, such as by using Gray code; splitting the counting operation using wear levelling; and performing an error correction scheme with respect to the counting operation using majority voting.

The problem is to reduce the chances of causing a voltage drop in a bootstrap circuit. A control unit (60) has a first control mode, a second control mode, and a third control mode. In the first control mode, the control unit (60) controls a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) so that the first, second, third, and fourth switching elements (Q1, Q2, Q3, Q4) are ON, ON, OFF, and OFF, respectively. In the second control mode, the control unit (60) controls the first, second, third, and fourth switching elements (Q1-Q4) so that the first, second, third, and fourth switching elements (Q1-Q4) are OFF, ON, ON, and OFF, respectively. In the third control mode, the control unit (60) controls the first, second, third, and fourth switching elements (Q1-Q4) so that the first, second, third, and fourth switching elements (Q1-Q4) are OFF, ON, OFF, and ON, respectively When the polarity of a current flowing through an output terminal (41) is positive, the control unit (60) makes a transition to the first control mode via the second control mode immediately after having gone through the third control mode.

A half-bridge includes: a high-side (HS) transistor; a low-side (LS) transistor connected in series with the high-side transistor at the output node of the half-bridge; and a third-quadrant state (TQS) detector connected in parallel with the HS transistor or the LS transistor and connected in series with the LS transistor and / or the HS transistor, respectively, the TQS detector generating a signal in response to the direction of the voltage drop across the transistor connected in parallel with the TQS detector.

This invention discloses an excitation circuit and method for a fluxgate magnetic probe. The excitation circuit includes a crystal oscillator, a frequency divider, a D flip-flop, a first current amplifier, a second current amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor, a transistor, and an excitation coil. The crystal oscillator generates a high-frequency periodic signal, which is input to the input terminal of the frequency divider. The frequency divider divides the signal to obtain a square wave signal of the desired frequency. The square wave signal is input to the input terminal of the first current amplifier and the data input terminal of the D flip-flop. The data output terminal of the D flip-flop is connected to the input terminal of the second current amplifier. The first current amplifier is sequentially connected to the first resistor, the first capacitor, the excitation coil, the second capacitor, and the second resistor. The other end of the second resistor is connected to the output terminal of the second current amplifier. The base of the transistor is connected to the output terminal of the first current amplifier, and the collector of the transistor is connected to the clock control terminal of the D flip-flop.

The invention relates to a circuit arrangement (100) for measuring the current at a power transistor (10) of a drive inverter for an electrically powered vehicle, comprising a measuring transistor (20) configured to reflect a current (32) flowing through the power transistor (10), and an operational amplifier (40) configured such that an output voltage (48) at its output (46) is proportional to the current (32) flowing through the power transistor (10). The measuring transistor (20) and the operational amplifier (40) are integrated into the drive inverter. The invention further relates to a drive inverter and an electrically operated vehicle with a drive inverter.

The invention relates to an enable signal generation circuit and a semiconductor device including the same. An enable signal generation circuit includes a signal generation circuit, a counting circuit, and an activation interval adjustment circuit. The signal generation circuit synchronizes the command with the clock signal to activate the enable signal, and deactivates the enable signal in response to the deactivation control signal. The count circuit counts the clock signal when the enable signal is activated to generate a plurality of count result signals. When a command is input, the activation interval adjustment circuit generates the deactivation control signal at a first timing based on transition timings of the plurality of counting result signals.

Disclosed is a power supply semiconductor integrated circuit including: a power supply input terminal; a power supply output terminal; a ground terminal; a first external terminal to which a second terminal of a first capacitor is connected; a second external terminal to which a second terminal of a second capacitor is connected; a first detector which detects a voltage of the first external terminal; a second detector which detects a voltage of the second external terminal; a first switch between the first external terminal and the ground terminal; and a second switch between the second external terminal and the ground terminal. The first switch disconnects the second terminal of the first capacitor from ground potential upon receiving a signal from the first detector, and the second switch disconnects the second terminal of the second capacitor from ground potential upon receiving a signal from the second detector.

A device for driving a haptic actuator includes a driver circuit, a boost converter, a power device and a discharge circuit. In operation, an input signal may be converted into a PWM signal in the driver circuit. The PWM signal may drive the power device and the boost converter may generate an increasing amplitude at a high-voltage output. The discharge circuit may discharge the voltage on the high-voltage output and may decrease the amplitude at the high-voltage output.

A control input device and system are disclosed. The control input device has a mounting base to a capacitive touch screen; an actuator supported by and electrically insulated from the base with an electrically conducting surface and further including: an electrode that is touching, or adjacent to, the capacitive touch screen when the base is mounted, an electrical circuit between the electrode and the electrically conducting surface, the electrically conducting surface having a surface area that is selected such that the electrically conducting surface provides capacitive coupling to, or approaching, infinity whereby capacitive coupling between the electrode and the capacitive touch screen is detectable by the capacitive touch screen's controller, wherein, in use, the electrode is configured to undergo a change corresponding to a state of the actuator and the controller of the touch screen can determine the state of the actuator from the change to the electrode.

In a power converter system, converter legs are connected in parallel between a common direct current (DC) system and a common alternating current (AC) system or between two common DC systems to provide respective leg currents. A gate driver circuitry is included to provide dedicated gate voltages to gates of controllable semiconductor switching devices of parallel-connected converter legs. A control arrangement is configured to balance a current sharing between the parallel-connected converter legs by means of having an individual autonomous leg-specific gate voltage adjustment for the semiconductor power switching devices of each of parallel connected converter legs based on the leg current or leg-current-related information of the respective converter leg.

An enable signal generation circuit includes a signal generation circuit, a counting circuit, and an activation interval adjustment circuit. The signal generation circuit synchronizes a command to a clock signal to activate an enable signal, and deactivates the enable signal in response to a deactivation control signal. The counting circuit counts the clock signal to generate a plurality of count result signals when the enable signal is activated. The activation interval adjustment circuit generates the deactivation control signal at a first timing based on transition timings of the plurality of count result signals when the command is input.

An electronic system includes: a first electronic device including a transmitter configured to transmit data; and a second electronic device including a receiver configured to receive data, in which the transmitter is configured to: transmit a clock signal, an enable signal, and a heartbeat signal to the receiver; updating a transmit count value in response to a clock signal and the enable signal; and generating a heartbeat signal when the transmit count value is a first value, and wherein the receiver is configured to: update the receive count value in response to the clock signal and the enable signal; and generating an error signal when the reception count value is not the first value when the heartbeat signal is received.

A control input device for a capacitive touchscreen, a system, and a capacitive touchscreen including the control input device are disclosed, the control input device comprising a base for mounting the device at a predetermined location on the capacitive touchscreen, an actuator, the actuator supported by and electrically insulated from the base, the actuator having a conductive surface and further including an electrode that touches or is adjacent to the capacitive touchscreen when the base is in place, and an electrical circuit between the electrode and the conductive surface, the conductive surface having a surface area selected such that the conductive surface provides a capacitive coupling at or approaching infinity, whereby the capacitive coupling between the electrode and the capacitive touchscreen is detectable by a controller of the capacitive touchscreen, and in use the electrode is configured to undergo a change corresponding to a state of the actuator, and the controller of the touchscreen can determine the state of the actuator from the change in the electrode.

A monitoring circuit includes first and second oscillators, first and second frequency dividers, first and second counters, a determination portion, and an identification portion. The first and second frequency dividers respectively divide frequencies of first and second clock signals outputted from the first and second oscillators, respectively. The first and second counters respectively count the numbers of clocks of the second and first clock signals at first and second numbers of periods of first and second frequency-divided signals outputted from the first and second frequency dividers, respectively. The determination portion determines, based on results of counting by the first and second counters, whether or not an abnormality has occurred in either of the first and second clock signals. The identification portion identifies, at the occurrence of an abnormality in either of the first and second clock signals, which of the first and second clock signals is in an abnormal state.