160results about "Pulse technique" patented technology

An inductor-inductor-capacitor (LLC) converter may include a control system that holds a duty cycle of control signals at a desired ratio, such as 50%. The control system may include a counter that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch. An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits to add delay and / or inversion to generate multiple control signals from the output of the latch. Furthermore, the counter may be configured to switch from counting up to counting down in response to a comparator output.

Disclosed is an input-sensing part including sensing electrodes, sensing lines connected to the sensing electrodes, MUX circuits connected to the sensing lines, sensing pads connected to the MUX circuits, the sensing pads being fewer in number than the sensing lines, and a shielding electrode above the MUX circuits to cover the MUX circuits.

The invention provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, and relates to the technical field of circuits, the frequency divider comprises a master latch and a slave latch; each of the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross coupling pair and a load resistor pair; the current source is connected with the first current branch and the second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, the first current branch is provided with a first switching tube, and the second current branch is provided with a second switching tube and an adjustable resistor unit which are connected in series. Thus, the adjustable resistor unit is configured on the second current branch, association between the resistance value of the adjustable resistor unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustability, and frequency requirements of different scenes are met by adjusting the resistance value of the adjustable resistor unit and adjusting the self-resonant frequency of the frequency divider.

The invention discloses a detection equipment data synchronization method and device based on optical pulse coding counting. The method comprises the following steps: collecting a pulse signal output by a pulse encoder; the pulse encoder is mounted on the detection vehicle; according to a preset frequency division coefficient, performing frequency division on the pulse signal to generate frequency division pulse signals corresponding to the number of frequency division pulses; the preset frequency division coefficient is determined according to the sampling interval requirement of each detection device; the detection equipment is mounted on the detection vehicle; the number of the frequency division pulses corresponds to the number of the detection devices; the frequency division pulse signals corresponding to the frequency division pulse number are input into an optical switch for photoelectric signal conversion, and optical signals corresponding to the detection equipment are generated; according to the optical signal, detection data synchronization is carried out on the detection equipment corresponding to the optical signal, the accuracy of data synchronization of the detection equipment can be improved, and resource waste is avoided.

The application discloses an ultra-wideband reconfigurable injection locking multi-mode single-ended input / output frequency divider circuit, comprising an input unit, a frequency division circuit connected with the input unit, and an output unit connected with the frequency division circuit, wherein the frequency division circuit comprises an injection locking two-frequency division circuit and an injection locking three-frequency division circuit; the input unit utilizes a balun structure circuit, so that the injection locking two-frequency division circuit and the injection locking three-frequency division circuit are the same single-ended input; and the output unit utilizes a Multi-tank resonant network structure to realize single-ended output of two / three frequency division modes. The application can realize better efficacy, ultra-wideband performance, lower cost and easy integration in the design of a wideband millimeter wave phase-locked loop chip.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

The invention relates to a frequency division clock circuit detection method and device, computer equipment, a medium and a product. The method comprises the following steps: acquiring a detection target set of a frequency division clock circuit to be detected; the detection target set comprises each detection target; determining a detection template corresponding to each detection target in each candidate detection template; extracting a clock information set corresponding to the to-be-detected frequency division clock from the to-be-detected function module, and updating each detection template according to the clock information set to obtain detection data; detecting the to-be-detected frequency division clock according to the detection data to obtain a detection result of the to-be-detected frequency division clock; the detection result is used for positioning an abnormal reason of the to-be-detected functional module. By adopting the method, the problem positioning accuracy can be improved.

This invention provides a pulse voltage regulation circuit, comprising: a pulse control module and a reference voltage regulation module; the pulse control module is used to generate a set of M switching control signals according to the number of continuously input pulse signals; the reference voltage regulation module is connected to the output terminal of the pulse control module and is used to select a resistor voltage division ratio according to the M switching control signals, and to divide the bandgap voltage according to the selected resistor voltage division ratio to generate a reference voltage output; wherein, M = 2 N N is an integer greater than or equal to 1. The pulse voltage regulation circuit provided by this invention solves the problem of existing voltage regulation schemes adjusting the output voltage by changing the resistance value of external resistors.

In described examples, a circuit (100) includes a charge pump (110) to generate an output reference voltage. A first bootstrap refresh circuit (120) receives the reference voltage from the charge pump (110) and is coupled between first and second bootstrap nodes (124, 126) of a DC / DC converter. The first bootstrap refresh circuit (120) supplies first charge current that is sourced from the first bootstrap node (124) to the second bootstrap node (126) based on a control signal (130) indicating a first operating mode of the DC / DC converter. A second bootstrap refresh circuit (140) receives the reference voltage from the charge pump (110) and is coupled between the first and second bootstrap nodes (124, 126) of the DC / DC converter. The second bootstrap refresh circuit (140) supplies second charge current from the second bootstrap node (126) to the first bootstrap node (124) based on the control signal (130) indicating a second operating mode of the DC / DC converter.

Disclosed is an input-sensing part including sensing electrodes, sensing lines connected to the sensing electrodes, MUX circuits connected to the sensing lines, sensing pads connected to the MUX circuits, the sensing pads being fewer in number than the sensing lines, and a shielding electrode above the MUX circuits to cover the MUX circuits.

The present description relates to an electronic device (100), comprising: - a first electronic circuit (104) configured to generate a first clock signal (CK) and a second signal (READY) indicating a stability state of the frequency of the first signal, the second signal having a first value during a first period and a second value after the first period; and - a second electronic circuit (106) configured to generate an output clock signal (CK_SOC) having a frequency equal to the frequency of the first signal (CK) divided by a first factor (k) when the second signal (READY) is at the first value and having the frequency of the first signal (CK), or a frequency equal to the frequency of the first signal (CK) divided by a second factor (N) lower than the first factor, following a change of the second signal (READY) towards the second value.

The invention relates to a high-side switching circuit. A circuit includes an input terminal (VBB), an output terminal (VOUT), a first transistor (102), a second transistor (106), a charge pump circuit (118), a resistor (104), and a current source (112). The input terminal (VBB) is configured to provide an input voltage. The output terminal (VOUT) is configured to provide an output voltage. The first transistor (102) has a first terminal coupled to the input terminal (VBB), a second terminal coupled to the output terminal (VOUT), and a control terminal. The charge pump circuit (118) has an output coupled to the control terminal. The resistor (104) has a first terminal coupled to the control terminal, and a second terminal. The second transistor (106) has a first terminal coupled to the second terminal of the resistor (104), a second terminal coupled to the output terminal (VOUT), and a control terminal. The current source (112) has an input coupled to the control terminal of the second transistor (106).

The invention relates to a measuring device (1) for capacitive level detection, consisting of a housing (2) that is at least partially rotationally symmetrical and a sensor tip (3) extending directly to the housing (2) in an axial direction, which comprises a measuring electrode (4) and a sheathing (5) surrounding the measuring electrode (4), wherein the sheathing (5) extends into the housing (2) and has a circumferential projection (6) that increases the diameter of the sensor tip (3), onto which the housing (2) rests axially.According to the invention, the housing (2) has an inwardly directed shoulder-like narrowing (7) on which a ring element (10) rests, and the casing (5) has a groove-like recess (8) at the level of the shoulder-like narrowing (7) into which the ring element (10) engages, wherein the ring element (10) is designed such that it develops a permanent tensile stress inwards in the direction of the groove-like recess (8), and wherein the groove-like recess (8) has a wedge shape, such that the casing (5) is pulled axially towards the housing (2) due to the inwardly acting tensile stress of the ring element (10), and thereby the housing (2) rests permanently tightly on the projection (6) of the casing (5).

The embodiment of the invention provides a wide dynamic range ion pulse threshold adaptive counting method and circuit, and the method comprises the steps: a first end of an electron multiplier is connected with an ion signal, a second end is connected with an input end of an amplification circuit, an output end is connected with a first end of a baseline extraction module, and a second end is connected with a first end of a baseline smoothing module; the second end is connected with the input end of the comparison circuit and the output end is connected with the counting circuit; the electron multiplier is used for converting the ion signal into a current pulse; the amplifying circuit is used for converting the current pulse into a voltage pulse; the baseline extraction module is used for extracting a voltage pulse baseline to obtain a baseline signal; the baseline smoothing module is used for smoothing the baseline signal to obtain a smoothed signal; the comparison circuit is used for dynamically determining a self-adaptive threshold value based on the smooth signal, comparing the voltage pulse with the self-adaptive threshold value and outputting a comparison signal; and the counting circuit is used for pulse counting to obtain the number of target pulses. Therefore, the counting accuracy and the counting upper limit are improved.

In this gate drive circuit, first and second gate drive ICs each have: an INA terminal and an INB terminal to which PWM signals are input; a gate output terminal for outputting a gate drive signal; and an OSFB terminal for outputting a feedback signal of the gate drive signal. The first and second gate drive ICs are configured so as to output the gate drive signal of an ON state when inputs to the INA terminal and the INB terminal are ON and OFF, respectively. In the first gate drive IC, the INA terminal and the INB terminal receive a first PWM signal and a second PWM signal, respectively. In the second gate drive IC, the INA terminal and the INB terminal receive the second PWM signal and the first PWM signal, respectively. A first diode has the cathode side that is connected to the INB terminal of the second gate drive IC and the anode side that is connected to the OSFB terminal of the first gate drive IC. A second diode has the cathode side that is connected to the INB terminal of the first gate drive IC and the anode side that is connected to the OSFB terminal of the second gate drive IC.

The utility model discloses a divide-by-2 frequency divider. The divide-by-2 frequency divider comprises a first trigger, a second trigger, a third trigger, a fourth trigger and an anti-phase unit, the first trigger, the second trigger, the third trigger and the fourth trigger are cascaded; the inverting unit is used for inverting a first intermediate signal output by the first trigger, a second intermediate signal output by the second trigger, a third intermediate signal output by the third trigger and a fourth intermediate signal output by the fourth trigger to generate a first result signal, a second result signal, a third result signal and a fourth result signal. According to the divide-by-2 frequency divider provided by the utility model, the first trigger, the second trigger, the third trigger and the fourth trigger are cascaded, and each trigger can support a differential mode and is driven by a differential input clock signal, so that the divide-by-2 frequency divider can output a signal with a duty ratio of 25% while realizing divide-by-2 frequency division, and a special output circuit with a duty ratio of 25% is not needed any more; and the power consumption and the chip area are reduced.

A semiconductor device capable of repeated use and suppressing damage to surrounding equipment. The semiconductor device of this embodiment includes a first circuit, a first terminal, a second terminal, a conductor connecting the first terminal and the second terminal in series, and a first switching element. The first circuit is configured to turn the first switching element off when a first condition is met. The conductor is configured to be physically disconnected when a second condition is met.

There is described a computer-implemented method of operating a counter, the method comprising: i) performing a counting operation, wherein the counting operation is done in a bit-wise manner, in particular using Gray code; ii) splitting the counting operation using a wear levelling; and iii) performing an error correction scheme with respect to the counting operation using a majority voting.

The application relates to a time-domain temperature sensor based on MOSFET temperature sensing, and belongs to the temperature sensor field. The temperature sensor comprises a temperature sensing unit and a frequency digital converter connected in sequence. The frequency digital converter comprises a voltage-controlled oscillator and a counter. The temperature sensor senses the external temperature through the temperature sensing unit, converts a physical signal into an analog signal, converts the analog signal into a frequency signal through the voltage-controlled oscillator, inputs the frequency signal into the counter, and reads out a digital code value representing temperature information from the counter. Compared with a traditional temperature sensor, the temperature sensor has the advantages of low power consumption, small area, simple structure and the like.

The utility model discloses a hybrid counter capable of shielding a clock metastable state. The hybrid counter structurally comprises an n-bit asynchronous clock counter, a metastable state shielding circuit and an m-bit synchronous clock counter. A first input clock signal passes through the n-bit asynchronous clock counter to generate an asynchronous clock signal, the asynchronous clock signal Q [n-3] and a data signal Qdata [n] pass through the metastable state shielding circuit to generate a second input clock, and the clock signal passes through the m-bit synchronous clock counter to output a count value. The shielding signal generated by the metastable state shielding circuit can shield the rising edge and the falling edge of the clock received by the synchronous clock counter during the metastable state, so that the problem of overflow counting caused by burrs generated by the metastable state is solved.

An electronic system including: a first electronic device including a sender that is configured to transmit data; and a second electronic device including a receiver that is configured to receive the data, wherein the sender is configured to: transmit a clock signal, an enable signal, and a heartbeat signal to the receiver; update a sending count value in response to the clock signal and the enable signal; and generate the heartbeat signal when the sending count value is a first value, and wherein the receiver is configured to: update a receiving count value in response to the clock signal and the enable signal; and generate an error signal when the receiving count value does not have the first value upon receipt of the heartbeat signal.

Overvoltage and overcurrent protection switch. This description relates to an overvoltage and overcurrent protection switch (210) comprising: - a first NMOS transistor (T211) adapted to receive a first voltage across its conduction terminals; - a second NMOS transistor (T212) comprising a source terminal connected to a source terminal of said first transistor (T211), and adapted to receive a second voltage across its conduction terminals that is lower than the first voltage; and - a third NMOS transistor (T213) comprising a source terminal connected to a source terminal of said first transistor (T211), and adapted to receive said second voltage across its conduction terminals. Figure for the abbreviation: Fig. 2

The invention discloses a clock frequency divider and a clock frequency division generation method, the clock frequency divider comprises a frequency division coefficient synchronization module, a frequency division counting module and a clock generation module, when a current effective frequency division coefficient is 0 or 1, an input clock signal is used as an output signal; when the current effective frequency division coefficient is a non-zero even number, taking the frequency division clock signal as an output signal; and when the current effective frequency division coefficient is a non-1 odd number, latching the frequency division clock signal at the falling edge of the input clock signal to generate a latch signal, and taking a combined signal of the frequency division clock signal and the latch signal as an output signal. The invention aims to provide a clock frequency division solution which can flexibly adjust the frequency division coefficient according to the actual application scene and has the functions of low-power-consumption control, safe clock switching and the like so as to meet the diversified clock requirements of a complex digital system.

Embodiments of the disclosure provide a short-circuit protection circuit for a SiC MOS transistor including: a state detection unit configured to generate an indication signal for indicating whether a short-circuit occurs; a driving unit connected to the SiC MOS transistor, to drive the SiC MOS transistor to be turned off in response to that the indication signal indicates that a short-circuit occurs; and a power supply voltage conversion unit, the power supply voltage conversion unit being connected to the state detection unit, to switch between a first on position and a second on position, the power supply voltage conversion unit being connected to the driving unit, to provide a first power supply voltage or a second power supply voltage to the driving unit, the driving unit being configured to provide a first driving voltage to the SiC MOS transistor and provide a second driving voltage to the SiC MOS transistor.

The application belongs to the signal reading part in the circuit system, and relates to a digital signal driving circuit and a driving method with multi-channel input and single-channel output. The driving circuit comprises an enabling pulse generating circuit, a time sequence generating circuit and m signal transmission circuits. The enabling pulse generating circuit has one clock signal input end, one enabling pulse signal input end and n column-level circuit output switch control signal output ends. The time sequence generating circuit has k column-level circuit output switch control signal input ends and k signal transmission control time sequence output ends. Each signal transmission circuit has n column-level circuit signal input ends, n column-level circuit output switch control signal input ends, k signal transmission control time sequence input ends and one single-tap data output end. In one signal transmission circuit, n columns of signals are divided into k sections for driving respectively, and each section has j columns of reading circuits, so that multi-channel input and single-channel output of single-tap signal transmission from the column-level circuit are realized.

The invention relates to a charging device (1) comprising at least one grid connection (2) for an alternating voltage (3), a power factor correction circuit (5) for each grid connection (2), n DC / DC converters (6) connected in parallel, wherein n > 2, and a control device (7), wherein the control device (7) is configured to operate the DC / DC converters (6), wherein the control device (7) is further configured to distribute power non-uniformly to the DC / DC converters (6) depending on the power requirements and parameters of the switching elements (S) of the DC / DC converters (6).

The application discloses a frequency division synchronous circuit applied to a multi-channel analog-digital converter, which is composed of three main modules of a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit. The multi-channel analog-digital converter needs a reasonably designed clock system to provide a timing basis for the cooperative work of each module, but the existing clock system has problems of large jitter, fuzzy state and low efficiency, and the multi-channel analog-digital converter based on the clock system is difficult to meet the needs of the fast developing communication and detection array system. The application is an improved clock system, which reduces the sampling clock jitter through an edge reconstruction technology, thereby improving the sampling noise and improving the conversion precision; the phase ambiguity of the frequency division is eliminated through a synchronous strategy, which is beneficial to data processing and correction, and the clock system can be reset to a specific initial state under control, which is beneficial to array application; through a bus type clock distribution strategy, the number of clock transmission lines is reduced, and the circuit operation efficiency is improved.

A computer-implemented method of operating a counter is described, the method comprising: i) performing a counting operation, where the counting operation is performed in a bitwise manner, in particular using Gray codes; ii) segmenting the counting operation using wear leveling; and iii) performing an error correction scheme for the count operation using majority voting.

The invention relates to a method and an apparatus for correct identification of overload conditions in power devices. A circuit for protecting a power supply system from an over-current condition by monitoring an input voltage and an output voltage of the power supply system, detecting the over-current condition based on the monitored input voltage and output voltage, and determining whether the over-current condition is caused by an input transient or an output short circuit. When the detected overcurrent condition is caused by the input transient, the gate of the power transistor is controlled to maintain current flow to the load. When the detected overcurrent condition is caused by the output short circuit, the power transistor is turned off to protect the power supply system.