305results about "Pulse technique" patented technology

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

A semiconductor device includes an output element, a temperature detection circuit, a current limiting circuit, and an overcurrent detection circuit. The output element is a power semiconductor element that drives a load, and is turned on by applying a predetermined turn-on voltage to a gate of the output element in a normal state. The temperature detection circuit detects the temperature of the output element as a detected temperature, during the operation of the output element. The overcurrent detection circuit detects an overcurrent state of the output element. When the overcurrent state is detected and the detected temperature exceeds a set temperature, the current limiting circuit sets a gate voltage of the output element to a set voltage lower than the predetermined turn-on voltage. In addition, the current limiting circuit increases the set voltage in stages as the temperature decreases.

An integrated circuit can include frequency monitoring circuitry. The frequency monitoring circuitry may include a voltage based frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a first set of frequencies and a coarse frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a second set of frequencies different than the first set of frequencies. The voltage based frequency monitoring circuit can be configured to generate an output voltage having a first value when the input clock frequency is greater than a reference frequency and having a second value when the input clock frequency is less than the reference frequency. The coarse frequency monitoring circuit can include a reference counter and an input clock counter that generates a count value used to compute the input clock frequency.

An illuminated keyswitch structure includes a base plate, a keycap, and a light-emitting die package. The light-emitting die package is disposed to illuminate the keycap through the base plate. The light-emitting die package comprises a warm color temperature light-emitting die and a cold color temperature light-emitting die, and the light-emitting die package extends along an arrangement direction. Each of the two light-emitting dies has a short side arranged adjacent to each other, with a long side of each of the two light-emitting dies facing a same direction and configured proximate to each other. A gap between the two adjacent short sides of the two light-emitting dies is not greater than either one of the two adjacent short sides of the two light-emitting dies.

An inductor-inductor-capacitor (LLC) converter may include a control system that holds a duty cycle of control signals at a desired ratio, such as 50%. The control system may include a counter that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch. An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits to add delay and / or inversion to generate multiple control signals from the output of the latch. Furthermore, the counter may be configured to switch from counting up to counting down in response to a comparator output.

The invention relates to an address identification system and method for a multi-card-slot system and multi-card-slot equipment, and the system comprises a signal generation module which is used for generating a fundamental wave signal according to a preset requirement of a user; the input end of the signal frequency division module is connected with the signal generation module, and the signal frequency division module is used for performing frequency division on the fundamental wave signal to obtain a plurality of frequency division signals with different frequencies and outputting the frequency division signals with different frequencies to different card slots; the input end of the signal detection module is connected with the card slot, and the signal detection module is used for receiving the frequency division signal transmitted to the card slot and identifying the physical address of the card slot according to the frequency division signal. According to the device address identification method, the fundamental wave signal with the fixed frequency is generated, and the frequency division signal is sequentially generated on each slot, so that the device on each slot can detect signals with different frequencies, and a traditional resistance voltage division method is replaced to carry out device address identification.

The invention discloses a method and device for measuring the rotating speed of a steam turbine, and the method comprises the steps: carrying out the blocking and filtering of a rotating speed signal collected in real time, generating a filtering signal, setting a threshold voltage through a hysteresis circuit, and outputting a pulse signal; the pulse signal is subjected to optocoupler isolation and signal wave shaping, and then a square wave signal is output; the frequency value of the rotating speed is calculated based on the square wave signal, the rotating speed value is obtained through further calculation, and finally the obtained rotating speed value is filtered by combining a Hampel filter and a moving average filter. Compared with a traditional rotating speed measurement mode, the frequency measurement precision is guaranteed, and meanwhile the anti-interference capacity of the measurement device is enhanced.

Disclosed is an input-sensing part including sensing electrodes, sensing lines connected to the sensing electrodes, MUX circuits connected to the sensing lines, sensing pads connected to the MUX circuits, the sensing pads being fewer in number than the sensing lines, and a shielding electrode above the MUX circuits to cover the MUX circuits.

A power consumption evaluation device and a power consumption evaluation method are provided. The power consumption evaluation device includes a power converter, a counter, and a controller. The power converter includes a power switch. The power switch performs a switching operation according to a control signal, so that the power converter supplies power to a corresponding load among at least one load. The counter counts one of a positive pulse and a negative pulse of the control signal during a measurement period to obtain a count value. The controller generates an evaluation result of the corresponding load according to the count value.

The invention discloses a coiled material defect positioning method and device, equipment and a medium. The method comprises the following steps: receiving a coiled material image of a to-be-detected coiled material shot by a line-scan digital camera and a pulse accumulation number corresponding to the coiled material image; wherein the coiled material image is obtained by triggering shooting by pulses emitted by the meter counting wheel, and the pulse accumulation number is obtained by accumulating the pulses emitted by the meter counting wheel while the linear array camera triggers shooting; determining actual position information of the coiled material image based on the pulse cumulative number; performing defect detection based on the coiled material image; and if the defect information is detected, positioning the position of the defect in the defect information based on the actual position information. Therefore, the actual position information corresponding to each part on the image can be accurately determined by associating the pulse cumulative number with the coiled material image, and when the defect is detected, the defect is accurately positioned by using the actual position information, so that the exact position of the defect on the coiled material can be quickly identified, and the accuracy of coiled material defect detection is improved.

The invention discloses an ultra-wideband reconfigurable injection-locking multi-mode single-ended input / output frequency divider circuit, which comprises an input unit, a frequency dividing circuit connected with the input unit and an output unit connected with the frequency dividing circuit, and is characterized in that the frequency dividing circuit comprises an injection-locking two-half frequency dividing circuit and an injection-locking three-half frequency dividing circuit; the input unit uses a Balun structure circuit to enable the injection locking frequency-halving circuit and the injection locking frequency-tripling circuit to be the same single-end input, and the output unit uses a Multi-tank resonance network structure to realize single-end output of two frequency-tripling and frequency-tripling modes. In the design of the broadband millimeter wave phase-locked loop chip, better efficacy and ultra-wideband performance can be realized, the cost is lower, and the integration is easy.

The invention relates to a dual-mode asynchronous binary counter circuit and a detection method, the circuit comprises a plurality of cascaded counting modules and a negation delayer, and the negation delayer delays an external control signal to generate a negation control signal; the counting module comprises a D trigger and a multiplexer, the multiplexer comprises a low-level input end and a high-level input end, a selection end is connected with an external control signal, the high-level input end is connected with a negation control signal, and an output end is connected with a clock input end of the D trigger of the counting module where the multiplexer is located; the low-level input end of the multiplexer in the first-stage counting module is connected with an external clock signal; the D input end of the D trigger is connected with the inverted output end of the D trigger and then connected to the low-level input end of the multiplexer in the next-stage counting module, the D input end of the D trigger of the last-stage counting module is connected with the inverted output end of the D trigger, and the output end of the D trigger outputs a counting result. Compared with the prior art, the method has the advantages of high dynamic performance, low power consumption, high flexibility and the like.

The embodiment of the invention discloses a signal period determination method and device, equipment, a medium and a program product. Comprising the following steps: acquiring a to-be-measured signal, a basic clock signal, a frequency increasing multiple and a split-phase number; performing frequency multiplication and phase splitting processing on the basic clock signal according to the frequency multiplication multiple and the phase splitting number to obtain a plurality of frequency multiplication phase splitting clock signals; sampling the to-be-measured signal for at least two periods through the basic clock signal and each frequency multiplication phase-splitting clock signal, and determining a counting result corresponding to each period; and determining the signal period of the to-be-detected signal according to each counting result. As the sampling times are greatly increased, the precision and accuracy of periodic measurement of the to-be-measured signal are improved, and the shooting stability of an industrial camera triggered according to the to-be-measured signal is further improved.

A control input device and system are disclosed. The control input device has a mounting base to a capacitive touch screen; an actuator supported by and electrically insulated from the base with an electrically conducting surface and further including: an electrode that is touching, or adjacent to, the capacitive touch screen when the base is mounted, an electrical circuit between the electrode and the electrically conducting surface, the electrically conducting surface having a surface area that is selected such that the electrically conducting surface provides capacitive coupling to, or approaching, infinity whereby capacitive coupling between the electrode and the capacitive touch screen is detectable by the capacitive touch screen's controller, wherein, in use, the electrode is configured to undergo a change corresponding to a state of the actuator and the controller of the touch screen can determine the state of the actuator from the change to the electrode.

The invention discloses a single-photon detector post-pulse probability suppression method and system, and the method achieves the measurement of the arrival time of a detection pulse after a previous detection pulse, abandons the detection pulses in a certain time range, reduces the post-pulse probability, does not need to close a gate signal and hardware processing, and does not affect the performance of a detector. The post-pulse probability time distribution characteristics of the single-photon detector can be identified by means of a time periodic folding measurement scheme, so that the optimal suppression time window of the post-pulse probability of the single-photon detector can be reasonably adjusted according to the relationship between post-pulse probability distribution and the saturation counting rate, and the optimal detector performance is realized. The method has the characteristic of universality, is not only applied to a sine gating detector, but also can be applied to scenes such as a rectangular gating detector and a free operation detector which need to further suppress the post-pulse, and does not affect the original detection process.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

The invention relates to a serial-to-parallel conversion circuit and MIPI C-PHY equipment, the serial-to-parallel conversion circuit comprises a first frequency division module, a second frequency division module and a serial-to-parallel conversion module, the first frequency division module is used for accessing a first clock signal, performing m-1 frequency division processing and m frequency division processing on the first clock signal and then outputting a second clock signal and a switching signal; the second frequency division module is used for accessing a first clock signal and performing n / 2 frequency division processing on the first clock signal to obtain a synchronous clock signal; wherein n + 1 is equal to 2m, and n is a positive odd number; the serial-to-parallel conversion module is connected with the first frequency division module and the second frequency division module and is used for outputting the data signal as n paths of data under the control action of the access data signal, the first clock signal, the second clock signal, the switching signal and the synchronous clock signal; the transmission rate of the data signal is twice the frequency of the first clock signal.

The invention discloses a frequency division synchronous circuit applied to a multi-channel analog-to-digital converter. The frequency division synchronous circuit is composed of three main modules including a frequency division reconstruction circuit, a synchronous signal generation circuit and a clock distribution circuit. A multi-channel analog-to-digital converter needs a reasonably designed clock system to provide a time sequence basis for cooperative work of all modules, however, an existing clock system has the problems of large jitter, fuzzy state, low efficiency and the like, and the multi-channel analog-to-digital converter based on the problems is difficult to meet the requirements of rapidly developed communication and detection array systems. According to the improved clock system, the sampling clock jitter is reduced through the edge reconstruction technology, so that the sampling noise is improved, and the conversion precision is improved; the phase ambiguity of frequency division is eliminated through a synchronization strategy, data processing and correction are facilitated, the device can be controlled to be reset to a specific initial state, and array application is facilitated; through a bus type clock distribution strategy, the number of clock transmission lines is reduced, and the circuit operation efficiency is improved.

The invention provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, and relates to the technical field of circuits, the frequency divider comprises a master latch and a slave latch; each of the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross coupling pair and a load resistor pair; the current source is connected with the first current branch and the second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, the first current branch is provided with a first switching tube, and the second current branch is provided with a second switching tube and an adjustable resistor unit which are connected in series. Thus, the adjustable resistor unit is configured on the second current branch, association between the resistance value of the adjustable resistor unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustability, and frequency requirements of different scenes are met by adjusting the resistance value of the adjustable resistor unit and adjusting the self-resonant frequency of the frequency divider.

The invention discloses a detection equipment data synchronization method and device based on optical pulse coding counting. The method comprises the following steps: collecting a pulse signal output by a pulse encoder; the pulse encoder is mounted on the detection vehicle; according to a preset frequency division coefficient, performing frequency division on the pulse signal to generate frequency division pulse signals corresponding to the number of frequency division pulses; the preset frequency division coefficient is determined according to the sampling interval requirement of each detection device; the detection equipment is mounted on the detection vehicle; the number of the frequency division pulses corresponds to the number of the detection devices; the frequency division pulse signals corresponding to the frequency division pulse number are input into an optical switch for photoelectric signal conversion, and optical signals corresponding to the detection equipment are generated; according to the optical signal, detection data synchronization is carried out on the detection equipment corresponding to the optical signal, the accuracy of data synchronization of the detection equipment can be improved, and resource waste is avoided.

The application discloses an ultra-wideband reconfigurable injection locking multi-mode single-ended input / output frequency divider circuit, comprising an input unit, a frequency division circuit connected with the input unit, and an output unit connected with the frequency division circuit, wherein the frequency division circuit comprises an injection locking two-frequency division circuit and an injection locking three-frequency division circuit; the input unit utilizes a balun structure circuit, so that the injection locking two-frequency division circuit and the injection locking three-frequency division circuit are the same single-ended input; and the output unit utilizes a Multi-tank resonant network structure to realize single-ended output of two / three frequency division modes. The application can realize better efficacy, ultra-wideband performance, lower cost and easy integration in the design of a wideband millimeter wave phase-locked loop chip.

An integrated circuit may include frequency monitoring circuitry. The frequency monitoring circuitry may include a voltage-based frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a first set of frequencies and a coarse frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a second set of frequencies different from the first set of frequencies. The voltage-based frequency monitoring circuit may be configured to generate an output voltage having a first value when the input clock frequency is greater than a reference frequency and a second value when the input clock frequency is less than the reference frequency.The coarse frequency monitoring circuitry may include a reference counter and an input clock counter that generates a count value used to calculate the input clock frequency.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

The invention relates to a frequency division clock circuit detection method and device, computer equipment, a medium and a product. The method comprises the following steps: acquiring a detection target set of a frequency division clock circuit to be detected; the detection target set comprises each detection target; determining a detection template corresponding to each detection target in each candidate detection template; extracting a clock information set corresponding to the to-be-detected frequency division clock from the to-be-detected function module, and updating each detection template according to the clock information set to obtain detection data; detecting the to-be-detected frequency division clock according to the detection data to obtain a detection result of the to-be-detected frequency division clock; the detection result is used for positioning an abnormal reason of the to-be-detected functional module. By adopting the method, the problem positioning accuracy can be improved.

This invention provides a pulse voltage regulation circuit, comprising: a pulse control module and a reference voltage regulation module; the pulse control module is used to generate a set of M switching control signals according to the number of continuously input pulse signals; the reference voltage regulation module is connected to the output terminal of the pulse control module and is used to select a resistor voltage division ratio according to the M switching control signals, and to divide the bandgap voltage according to the selected resistor voltage division ratio to generate a reference voltage output; wherein, M = 2 N N is an integer greater than or equal to 1. The pulse voltage regulation circuit provided by this invention solves the problem of existing voltage regulation schemes adjusting the output voltage by changing the resistance value of external resistors.

In described examples, a circuit (100) includes a charge pump (110) to generate an output reference voltage. A first bootstrap refresh circuit (120) receives the reference voltage from the charge pump (110) and is coupled between first and second bootstrap nodes (124, 126) of a DC / DC converter. The first bootstrap refresh circuit (120) supplies first charge current that is sourced from the first bootstrap node (124) to the second bootstrap node (126) based on a control signal (130) indicating a first operating mode of the DC / DC converter. A second bootstrap refresh circuit (140) receives the reference voltage from the charge pump (110) and is coupled between the first and second bootstrap nodes (124, 126) of the DC / DC converter. The second bootstrap refresh circuit (140) supplies second charge current from the second bootstrap node (126) to the first bootstrap node (124) based on the control signal (130) indicating a second operating mode of the DC / DC converter.

Disclosed is an input-sensing part including sensing electrodes, sensing lines connected to the sensing electrodes, MUX circuits connected to the sensing lines, sensing pads connected to the MUX circuits, the sensing pads being fewer in number than the sensing lines, and a shielding electrode above the MUX circuits to cover the MUX circuits.

An integrated circuit comprises a charge pump connected to a power source terminal and to a ground terminal, the charge pump having a charge pump output terminal; and a switch matrix having a plurality of switch matrix inputs and a plurality of switch matrix outputs, wherein pairs of the plurality of switch matrix outputs are connected to respective ones of a respective plurality of output terminals, and wherein the charge pump output terminal is connected to a first subset comprising at least three of the plurality of switch matrix inputs.

The present description relates to an electronic device (100), comprising: - a first electronic circuit (104) configured to generate a first clock signal (CK) and a second signal (READY) indicating a stability state of the frequency of the first signal, the second signal having a first value during a first period and a second value after the first period; and - a second electronic circuit (106) configured to generate an output clock signal (CK_SOC) having a frequency equal to the frequency of the first signal (CK) divided by a first factor (k) when the second signal (READY) is at the first value and having the frequency of the first signal (CK), or a frequency equal to the frequency of the first signal (CK) divided by a second factor (N) lower than the first factor, following a change of the second signal (READY) towards the second value.