218results about "Pulse technique" patented technology

A circuit is provided. The circuit can include sensing circuits configured to sense differences between first and second currents on selected bit lines of an array of memory cells and produce outputs for the bit lines as a function of the difference, and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal, wherein each sensing circuit, of the sensing circuits, includes (i) a local detector circuit configured to detect a voltage (Vc) generated according to the difference and (ii) a reference voltage selector configured to receive reference voltages from a source and to select a single reference voltage (Vref), and wherein each sensing circuit produces an output according to (i) a difference between Vc and Vref and (ii) a stored count value received from the counter.

An inductor-inductor-capacitor (LLC) converter may include a control system that holds a duty cycle of control signals at a desired ratio, such as 50%. The control system may include a counter that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch. An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits to add delay and / or inversion to generate multiple control signals from the output of the latch. Furthermore, the counter may be configured to switch from counting up to counting down in response to a comparator output.

Disclosed is an input-sensing part including sensing electrodes, sensing lines connected to the sensing electrodes, MUX circuits connected to the sensing lines, sensing pads connected to the MUX circuits, the sensing pads being fewer in number than the sensing lines, and a shielding electrode above the MUX circuits to cover the MUX circuits.

A control input device and system are disclosed. The control input device has a mounting base to a capacitive touch screen; an actuator supported by and electrically insulated from the base with an electrically conducting surface and further including: an electrode that is touching, or adjacent to, the capacitive touch screen when the base is mounted, an electrical circuit between the electrode and the electrically conducting surface, the electrically conducting surface having a surface area that is selected such that the electrically conducting surface provides capacitive coupling to, or approaching, infinity whereby capacitive coupling between the electrode and the capacitive touch screen is detectable by the capacitive touch screen's controller, wherein, in use, the electrode is configured to undergo a change corresponding to a state of the actuator and the controller of the touch screen can determine the state of the actuator from the change to the electrode.

The invention discloses a single-photon detector post-pulse probability suppression method and system, and the method achieves the measurement of the arrival time of a detection pulse after a previous detection pulse, abandons the detection pulses in a certain time range, reduces the post-pulse probability, does not need to close a gate signal and hardware processing, and does not affect the performance of a detector. The post-pulse probability time distribution characteristics of the single-photon detector can be identified by means of a time periodic folding measurement scheme, so that the optimal suppression time window of the post-pulse probability of the single-photon detector can be reasonably adjusted according to the relationship between post-pulse probability distribution and the saturation counting rate, and the optimal detector performance is realized. The method has the characteristic of universality, is not only applied to a sine gating detector, but also can be applied to scenes such as a rectangular gating detector and a free operation detector which need to further suppress the post-pulse, and does not affect the original detection process.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

The invention relates to a serial-to-parallel conversion circuit and MIPI C-PHY equipment, the serial-to-parallel conversion circuit comprises a first frequency division module, a second frequency division module and a serial-to-parallel conversion module, the first frequency division module is used for accessing a first clock signal, performing m-1 frequency division processing and m frequency division processing on the first clock signal and then outputting a second clock signal and a switching signal; the second frequency division module is used for accessing a first clock signal and performing n / 2 frequency division processing on the first clock signal to obtain a synchronous clock signal; wherein n + 1 is equal to 2m, and n is a positive odd number; the serial-to-parallel conversion module is connected with the first frequency division module and the second frequency division module and is used for outputting the data signal as n paths of data under the control action of the access data signal, the first clock signal, the second clock signal, the switching signal and the synchronous clock signal; the transmission rate of the data signal is twice the frequency of the first clock signal.

The invention provides a static frequency divider with adjustable self-resonant frequency and a clock circuit, and relates to the technical field of circuits, the frequency divider comprises a master latch and a slave latch; each of the master latch and the slave latch comprises a current source, an adjustable resistor unit, a differential amplification pair, a cross coupling pair and a load resistor pair; the current source is connected with the first current branch and the second current branch, the first current branch is connected with the load resistor pair through the differential amplification pair, the second current branch is connected with the load resistor pair through the cross coupling pair, the first current branch is provided with a first switching tube, and the second current branch is provided with a second switching tube and an adjustable resistor unit which are connected in series. Thus, the adjustable resistor unit is configured on the second current branch, association between the resistance value of the adjustable resistor unit and the frequency of the frequency divider is established, a hardware basis is provided for frequency adjustability, and frequency requirements of different scenes are met by adjusting the resistance value of the adjustable resistor unit and adjusting the self-resonant frequency of the frequency divider.

The invention discloses a detection equipment data synchronization method and device based on optical pulse coding counting. The method comprises the following steps: collecting a pulse signal output by a pulse encoder; the pulse encoder is mounted on the detection vehicle; according to a preset frequency division coefficient, performing frequency division on the pulse signal to generate frequency division pulse signals corresponding to the number of frequency division pulses; the preset frequency division coefficient is determined according to the sampling interval requirement of each detection device; the detection equipment is mounted on the detection vehicle; the number of the frequency division pulses corresponds to the number of the detection devices; the frequency division pulse signals corresponding to the frequency division pulse number are input into an optical switch for photoelectric signal conversion, and optical signals corresponding to the detection equipment are generated; according to the optical signal, detection data synchronization is carried out on the detection equipment corresponding to the optical signal, the accuracy of data synchronization of the detection equipment can be improved, and resource waste is avoided.

The application discloses an ultra-wideband reconfigurable injection locking multi-mode single-ended input / output frequency divider circuit, comprising an input unit, a frequency division circuit connected with the input unit, and an output unit connected with the frequency division circuit, wherein the frequency division circuit comprises an injection locking two-frequency division circuit and an injection locking three-frequency division circuit; the input unit utilizes a balun structure circuit, so that the injection locking two-frequency division circuit and the injection locking three-frequency division circuit are the same single-ended input; and the output unit utilizes a Multi-tank resonant network structure to realize single-ended output of two / three frequency division modes. The application can realize better efficacy, ultra-wideband performance, lower cost and easy integration in the design of a wideband millimeter wave phase-locked loop chip.

An integrated circuit may include frequency monitoring circuitry. The frequency monitoring circuitry may include a voltage-based frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a first set of frequencies and a coarse frequency monitoring circuit for monitoring an input clock signal having an input clock frequency within a second set of frequencies different from the first set of frequencies. The voltage-based frequency monitoring circuit may be configured to generate an output voltage having a first value when the input clock frequency is greater than a reference frequency and a second value when the input clock frequency is less than the reference frequency.The coarse frequency monitoring circuitry may include a reference counter and an input clock counter that generates a count value used to calculate the input clock frequency.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

The invention relates to a frequency division clock circuit detection method and device, computer equipment, a medium and a product. The method comprises the following steps: acquiring a detection target set of a frequency division clock circuit to be detected; the detection target set comprises each detection target; determining a detection template corresponding to each detection target in each candidate detection template; extracting a clock information set corresponding to the to-be-detected frequency division clock from the to-be-detected function module, and updating each detection template according to the clock information set to obtain detection data; detecting the to-be-detected frequency division clock according to the detection data to obtain a detection result of the to-be-detected frequency division clock; the detection result is used for positioning an abnormal reason of the to-be-detected functional module. By adopting the method, the problem positioning accuracy can be improved.

This invention provides a pulse voltage regulation circuit, comprising: a pulse control module and a reference voltage regulation module; the pulse control module is used to generate a set of M switching control signals according to the number of continuously input pulse signals; the reference voltage regulation module is connected to the output terminal of the pulse control module and is used to select a resistor voltage division ratio according to the M switching control signals, and to divide the bandgap voltage according to the selected resistor voltage division ratio to generate a reference voltage output; wherein, M = 2 N N is an integer greater than or equal to 1. The pulse voltage regulation circuit provided by this invention solves the problem of existing voltage regulation schemes adjusting the output voltage by changing the resistance value of external resistors.

In described examples, a circuit (100) includes a charge pump (110) to generate an output reference voltage. A first bootstrap refresh circuit (120) receives the reference voltage from the charge pump (110) and is coupled between first and second bootstrap nodes (124, 126) of a DC / DC converter. The first bootstrap refresh circuit (120) supplies first charge current that is sourced from the first bootstrap node (124) to the second bootstrap node (126) based on a control signal (130) indicating a first operating mode of the DC / DC converter. A second bootstrap refresh circuit (140) receives the reference voltage from the charge pump (110) and is coupled between the first and second bootstrap nodes (124, 126) of the DC / DC converter. The second bootstrap refresh circuit (140) supplies second charge current from the second bootstrap node (126) to the first bootstrap node (124) based on the control signal (130) indicating a second operating mode of the DC / DC converter.

Disclosed is an input-sensing part including sensing electrodes, sensing lines connected to the sensing electrodes, MUX circuits connected to the sensing lines, sensing pads connected to the MUX circuits, the sensing pads being fewer in number than the sensing lines, and a shielding electrode above the MUX circuits to cover the MUX circuits.

The present description relates to an electronic device (100), comprising: - a first electronic circuit (104) configured to generate a first clock signal (CK) and a second signal (READY) indicating a stability state of the frequency of the first signal, the second signal having a first value during a first period and a second value after the first period; and - a second electronic circuit (106) configured to generate an output clock signal (CK_SOC) having a frequency equal to the frequency of the first signal (CK) divided by a first factor (k) when the second signal (READY) is at the first value and having the frequency of the first signal (CK), or a frequency equal to the frequency of the first signal (CK) divided by a second factor (N) lower than the first factor, following a change of the second signal (READY) towards the second value.

The invention relates to a high-side switching circuit. A circuit includes an input terminal (VBB), an output terminal (VOUT), a first transistor (102), a second transistor (106), a charge pump circuit (118), a resistor (104), and a current source (112). The input terminal (VBB) is configured to provide an input voltage. The output terminal (VOUT) is configured to provide an output voltage. The first transistor (102) has a first terminal coupled to the input terminal (VBB), a second terminal coupled to the output terminal (VOUT), and a control terminal. The charge pump circuit (118) has an output coupled to the control terminal. The resistor (104) has a first terminal coupled to the control terminal, and a second terminal. The second transistor (106) has a first terminal coupled to the second terminal of the resistor (104), a second terminal coupled to the output terminal (VOUT), and a control terminal. The current source (112) has an input coupled to the control terminal of the second transistor (106).

Various embodiments disclosed herein relate to a system and method whereby a haptic feedback mechanism may be integrated into a rotatable gear module such that rotating the module may generate pure mechanical haptic feedback. The gear module may be integrated into a wearable device, such as headphones, such that a set of magnets incorporated within may be aligned and misaligned with a plurality of teeth when the gear module rotates. In response to the rotation, each alignment and misalignment of the set of magnets with the plurality of teeth may generate pure haptic feedback. In embodiments, the gear module may be rotated to increment or decrement a unit of measurement associated with the headphones. Each unit of increment or decrement of change may produce haptic feedback based on the alignment and misalignment of the set of magnets.

A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.

The invention relates to a measuring device (1) for capacitive level detection, consisting of a housing (2) that is at least partially rotationally symmetrical and a sensor tip (3) extending directly to the housing (2) in an axial direction, which comprises a measuring electrode (4) and a sheathing (5) surrounding the measuring electrode (4), wherein the sheathing (5) extends into the housing (2) and has a circumferential projection (6) that increases the diameter of the sensor tip (3), onto which the housing (2) rests axially.According to the invention, the housing (2) has an inwardly directed shoulder-like narrowing (7) on which a ring element (10) rests, and the casing (5) has a groove-like recess (8) at the level of the shoulder-like narrowing (7) into which the ring element (10) engages, wherein the ring element (10) is designed such that it develops a permanent tensile stress inwards in the direction of the groove-like recess (8), and wherein the groove-like recess (8) has a wedge shape, such that the casing (5) is pulled axially towards the housing (2) due to the inwardly acting tensile stress of the ring element (10), and thereby the housing (2) rests permanently tightly on the projection (6) of the casing (5).

The embodiment of the invention provides a wide dynamic range ion pulse threshold adaptive counting method and circuit, and the method comprises the steps: a first end of an electron multiplier is connected with an ion signal, a second end is connected with an input end of an amplification circuit, an output end is connected with a first end of a baseline extraction module, and a second end is connected with a first end of a baseline smoothing module; the second end is connected with the input end of the comparison circuit and the output end is connected with the counting circuit; the electron multiplier is used for converting the ion signal into a current pulse; the amplifying circuit is used for converting the current pulse into a voltage pulse; the baseline extraction module is used for extracting a voltage pulse baseline to obtain a baseline signal; the baseline smoothing module is used for smoothing the baseline signal to obtain a smoothed signal; the comparison circuit is used for dynamically determining a self-adaptive threshold value based on the smooth signal, comparing the voltage pulse with the self-adaptive threshold value and outputting a comparison signal; and the counting circuit is used for pulse counting to obtain the number of target pulses. Therefore, the counting accuracy and the counting upper limit are improved.

In this gate drive circuit, first and second gate drive ICs each have: an INA terminal and an INB terminal to which PWM signals are input; a gate output terminal for outputting a gate drive signal; and an OSFB terminal for outputting a feedback signal of the gate drive signal. The first and second gate drive ICs are configured so as to output the gate drive signal of an ON state when inputs to the INA terminal and the INB terminal are ON and OFF, respectively. In the first gate drive IC, the INA terminal and the INB terminal receive a first PWM signal and a second PWM signal, respectively. In the second gate drive IC, the INA terminal and the INB terminal receive the second PWM signal and the first PWM signal, respectively. A first diode has the cathode side that is connected to the INB terminal of the second gate drive IC and the anode side that is connected to the OSFB terminal of the first gate drive IC. A second diode has the cathode side that is connected to the INB terminal of the first gate drive IC and the anode side that is connected to the OSFB terminal of the second gate drive IC.

The utility model discloses a divide-by-2 frequency divider. The divide-by-2 frequency divider comprises a first trigger, a second trigger, a third trigger, a fourth trigger and an anti-phase unit, the first trigger, the second trigger, the third trigger and the fourth trigger are cascaded; the inverting unit is used for inverting a first intermediate signal output by the first trigger, a second intermediate signal output by the second trigger, a third intermediate signal output by the third trigger and a fourth intermediate signal output by the fourth trigger to generate a first result signal, a second result signal, a third result signal and a fourth result signal. According to the divide-by-2 frequency divider provided by the utility model, the first trigger, the second trigger, the third trigger and the fourth trigger are cascaded, and each trigger can support a differential mode and is driven by a differential input clock signal, so that the divide-by-2 frequency divider can output a signal with a duty ratio of 25% while realizing divide-by-2 frequency division, and a special output circuit with a duty ratio of 25% is not needed any more; and the power consumption and the chip area are reduced.

A semiconductor device capable of repeated use and suppressing damage to surrounding equipment. The semiconductor device of this embodiment includes a first circuit, a first terminal, a second terminal, a conductor connecting the first terminal and the second terminal in series, and a first switching element. The first circuit is configured to turn the first switching element off when a first condition is met. The conductor is configured to be physically disconnected when a second condition is met.

The invention discloses a high-temperature gas cooled reactor ball passing pulse counter system and method, and relates to the technical field of monitoring and control of a high-temperature gas cooled reactor, and the high-temperature gas cooled reactor ball passing pulse counter system comprises a pulse time sequence control module, an FPGA data acquisition and processing module and a power management and monitoring module; the system generates a time sequence signal through the pulse time sequence control module to realize rapid and accurate counting and interval recording, so that the counting precision is improved; the FPGA module provides low-power-consumption and efficient signal acquisition and AD conversion, can stably communicate with an external sensor, and ensures the real-time performance and accuracy of data acquisition. And the power management module adopts an isolated power supply design, so that real-time monitoring of multiple paths of power supplies is realized, and the stability and the safety of the system are enhanced.

There is described a computer-implemented method of operating a counter, the method comprising: i) performing a counting operation, wherein the counting operation is done in a bit-wise manner, in particular using Gray code; ii) splitting the counting operation using a wear levelling; and iii) performing an error correction scheme with respect to the counting operation using a majority voting.

The application relates to a time-domain temperature sensor based on MOSFET temperature sensing, and belongs to the temperature sensor field. The temperature sensor comprises a temperature sensing unit and a frequency digital converter connected in sequence. The frequency digital converter comprises a voltage-controlled oscillator and a counter. The temperature sensor senses the external temperature through the temperature sensing unit, converts a physical signal into an analog signal, converts the analog signal into a frequency signal through the voltage-controlled oscillator, inputs the frequency signal into the counter, and reads out a digital code value representing temperature information from the counter. Compared with a traditional temperature sensor, the temperature sensor has the advantages of low power consumption, small area, simple structure and the like.

The utility model discloses a hybrid counter capable of shielding a clock metastable state. The hybrid counter structurally comprises an n-bit asynchronous clock counter, a metastable state shielding circuit and an m-bit synchronous clock counter. A first input clock signal passes through the n-bit asynchronous clock counter to generate an asynchronous clock signal, the asynchronous clock signal Q [n-3] and a data signal Qdata [n] pass through the metastable state shielding circuit to generate a second input clock, and the clock signal passes through the m-bit synchronous clock counter to output a count value. The shielding signal generated by the metastable state shielding circuit can shield the rising edge and the falling edge of the clock received by the synchronous clock counter during the metastable state, so that the problem of overflow counting caused by burrs generated by the metastable state is solved.

A control interface (10) for controlling a system, comprising a module comprising: a carrier (32) having a top surface and an opposite bottom surface; an elongate window formed in, or adjacent, the carrier; an elongate array of light sources (36) on the bottom surface of the carrier; a reflector arrangement (40) for reflecting light from the array of light sources towards the window (38) to escape from the top surface, such that a light path is formed between each light source and the window (38), with a portion of the light paths being parallel to the carrier (32), wherein the light sources are adapted to be turned on in response to a control signal; wherein the module further comprises: a user interface surface (20), comprising a track area (22) for receiving touch input from a user, wherein the window is formed beneath the track area; and a touch sensor circuit (34) beneath the track area (22), wherein the touch sensitive circuit (34) comprises a touch sensor region on the top surface of the carrier (32); and a controller (70) adapted to control the light sources in dependence on a detected location of a touch input.