1247 results about "Charge pump" patented technology

The invention belongs to the field of driving circuits of gallium nitride (GaN) power devices in motor driving or power electronic conversion, and discloses a design method of a three-level active driving circuit for restraining bridge arm crosstalk of a GaN device, and the method comprises the steps that a circuit is connected in a bridge type topological structure, and the bridge type topological structure comprises an upper bridge arm and a lower bridge arm which are the same in structure; the upper bridge arm and the lower bridge arm are both divided into two parts, namely a traditional driving circuit and an auxiliary circuit, and the auxiliary circuit is divided into a negative voltage self-recovery circuit and a crosstalk suppression circuit. According to the invention, a negative voltage self-recovery circuit and a crosstalk suppression circuit are formed by using the output and reverse conduction characteristics of the charge pump and the auxiliary GaN device. The advantages of the two methods are combined, the defects of a traditional method are effectively overcome, the turn-off speed is increased, the turn-off loss is reduced, and the positive and negative crosstalk is reduced while the turn-on speed is hardly influenced and the reverse turn-on loss is not additionally increased. The overall design is flexible, efficient and reliable.

Disclosed in the present invention is a high-dynamic capacitive digital microphone system based on electrostatic force feedback. The system comprises an MEMS microphone and an interface circuit chip thereof, wherein the interface circuit chip comprises a charge pump, an analog front end, an analog-to-digital conversion circuit, an amplitude detection module, an amplitude adjustment control module and a pulse density modulation module. In the present invention, the characteristic of the sensitivity being able to be adjusted by means of changing a bias voltage by a capacitive sensor is used, and a charge pump with an adjustable output voltage is used to provide electrostatic force feedback, thereby further expanding the adjustable range of a front-end gain, and also reducing requirements for the noise performance of a readout circuit. Therefore, the system in the present application has the characteristics of high dynamic range and high-precision quantization.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.

The present disclosure provides a multi-stage charge pump, a current limiting circuit, a driver circuit, a charge pump, a chip, and an electronic device. A control circuit controls a first charge pump circuit to boost an input voltage of a multi-stage charge pump, and controls, based on a second-phase clock signal, a second charge pump circuit to be charged using an output voltage of the first charge pump circuit, such that the second charge pump circuit boosts an output voltage of the first charge pump circuit, and hence a high-side switch driver circuit satisfies a drive requirement of a high-side switch. This ensures normal operation of the charge pump is ensured while reducing the cost and circuit area. In this way, the reliability and safety of the charge pump are improved.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention provides an automatic frequency locking circuit based on a time-to-voltage converter and a phase-locked loop, and relates to the technical field of phase-locked loops, a first frequency-halving unit and a second frequency-halving unit respectively carry out frequency-halving processing on a reference signal and a frequency division signal of a current comparison period to obtain a first square wave signal and a second square wave signal; the first square wave signal and the second square wave signal are transmitted to the time-to-voltage converter; the time voltage converter comprises a phase generation unit, a first charge pump and a second charge pump, the phase generation unit generates an enable signal according to the first square wave signal and the second square wave signal, and the first charge pump and the second charge pump respond to control of the enable signal and collect single pulse signals from the first square wave signal and the second square wave signal respectively so as to supply power to the input end of the comparator; the comparator compares power supply voltages of the two input ends to achieve frequency comparison of the reference signal and the frequency division signal. And selection in a plurality of phase signals is not needed, and required digital circuit modules are reduced, so that the delay of the reference signal and the frequency division signal in the conversion process is reduced.

The invention provides a power management and power consumption control device and method of a continuous blood glucose detection circuit. Relates to the technical field of continuous blood glucose detection, solves the problems of power consumption control and switching in the prior art, and is characterized in that a power input end of a charge pump is connected with an anode of an external power supply; the control input end of the charge pump is connected with a mode control signal end; the power output end of the charge pump is connected with the first control end of the power switch device; the switching signal control end of the charge pump is connected with the second control end of the power switching device through the delayer; the output end of the power switch device is connected with the working voltage input end, and the working voltage output end is connected with the grounding capacitor; the power output end of the charge pump is connected with the input end of the power-on reset module, the power switch switching signal end of the power-on reset module is connected with the power switch switching signal end of the charge pump, and different working modes can be achieved, so that power consumption control is achieved.

Systems and devices for power multiplexing are described. A device can include a first power input circuit including a first power driver having a first gate that is configured to receive power from a first power input channel and output power to a power output channel. The device includes a second power input circuit including a second power driver having a second gate that is configured to receive power from a second power input channel and output power to the power output channel. The device includes a charge pump connected to the power output channel that generates an output having a voltage greater than a voltage on the power output channel. The device includes a switching circuit connected to the output of the charge pump that is configured to selectively control the first and second power input circuits to output power to the power output channel.

The utility model relates to the technical field of gas cylinder airtightness testing, and particularly provides a gas cylinder airtightness testing device, which comprises a base, a gas cylinder conveying belt is arranged on the base, the gas cylinder conveying belt comprises a first conveying belt and a second conveying belt, a water tank is arranged between the first conveying belt and the second conveying belt, and a gas cylinder taking and placing mechanism is arranged above a gas cylinder conveying mechanism; an inflation and deflation mechanism and a plurality of rotating shafts are arranged in the pool, the inflation and deflation mechanism comprises a lifting mechanism, a fixed table and inflation connectors, the fixed table is arranged on one axial side of the rotating shafts in a liftable mode through the lifting mechanism, a plurality of fixed plates are arranged on the fixed table, and each fixed plate is rotationally connected with one inflation connector; and the inflating joint is respectively connected with the pressure release valve and the inflating pump. According to the utility model, the automation degree of the gas cylinder airtightness test can be improved, the manpower is saved, the gas cylinder can be overturned by the rotating shaft in the water tank, the position of a leakage point can be observed more easily by overturning the gas cylinder, and the efficiency and effect of the gas cylinder airtightness test are improved.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

The invention belongs to the technical field of power management, and particularly relates to a double-phase DC-DC topological structure with a current multiplier. The invention is characterized in that a current multiplier and a switched capacitor SC buck are embedded on the basis of the traditional multiphase buck, the inductive current and the RMS current of a buck power device are greatly reduced, the current stress is transferred to a charge pump structure of a low-voltage and low-FoM-value device, and the voltage stress is retained in a high-voltage device of the buck. And high conversion efficiency is realized through a strategy that the charge pump and the buck share current and voltage stress respectively. Meanwhile, due to the fact that the switched capacitor has extremely low output impedance, and the circuit is compatible with a loop control strategy of a traditional multi-phase buck, the transient response speed is also remarkably improved. The idea of the invention can be linearly expanded from typical two-phase buck to N-phase buck, so that the topological structure of the invention has universality.

The invention belongs to the technical field of electronic circuits, and provides a negative voltage charge pump circuit, a switching power supply converter and electronic equipment. A reference voltage generation module, a comparison module, a fourth driving module, a fifth power tube, a sixth power tube and a seventh power tube are additionally arranged on an existing charge pump. The reference voltage generation module is used for generating third reference voltage, namely threshold voltage when the negative-voltage charge pump circuit enters the light load, then the comparison module is used for comparing the third reference voltage with error voltage output by the error amplifier, and whether the negative-voltage charge pump circuit enters the light-load working condition or not is judged; when the negative-voltage charge pump circuit enters a light-load working condition, the large-size power tube and the driving module thereof are closed, and only the small-size power tube works, so that other performances of the negative-voltage charge pump circuit are ensured, the working current of the negative-voltage charge pump circuit in the light-load state is greatly reduced, and the working efficiency of the negative-voltage charge pump circuit is improved. Therefore, the conversion efficiency of the charge pump circuit in light load is improved.

The invention discloses a grid voltage bootstrapped switch circuit with compensation and an ADC, and belongs to the technical field of integrated circuits. The circuit comprises a compensation charge pump circuit and a grid voltage bootstrapped switch circuit. A charge pump branch power supply end in the grid voltage bootstrap switch circuit is connected to an output compensation voltage end of the compensation charge pump circuit; when the input clock signal CLK1 is low and the input clock signal CLK2 is high in level, the power supply end of the charge pump branch is switched off, and the capacitor in the charge pump circuit is compensated for charging; when the level of the CLK1 is high and the level of the CLK2 is low, the power supply end of the charge pump branch is switched on, a bootstrap capacitor in the grid voltage bootstrap switch circuit is charged, and the Vboost provides compensation voltage. The compensation charge pump circuit provides higher power supply voltage for the grid voltage bootstrap switch, grid voltage drop of the sampling switch tube caused by parasitic capacitance at the positive end of the bootstrap capacitor can be compensated back, input parasitic capacitance is reduced, on-resistance of the sampling switch tube is reduced, and sampling linearity is improved.

A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

A level shifter or a display device comprising a level shifter includes a scan channel circuit generating a scan start signal for a plurality of subpixels according to a first input signal, a charge pump circuit generating a high-potential emission voltage using circuit power of a host system, and an emission channel circuit controlling an emission start signal according to a second input signal with a change in the circuit power reflected.

A charge pump circuit of a semiconductor memory device, which may include a first pumping stage that includes a first pumping capacitor and a second pumping capacitor, a first transfer stage that transfers a voltage of the first pumping capacitor when a clock signal is at a high level or transfers a voltage of the second pumping capacitor when a inverse clock signal is at the high level, a second pumping stage that includes a third pumping capacitor and a fourth pumping capacitor, and a second transfer stage that transfers a voltage of the third pumping capacitor when the clock signal is at the high level or transfers a voltage of the fourth pumping capacitor when the inverse clock signal is at the high level. The second transfer stage may output multiple times of the input voltage.

The invention provides a capacitor self-checking circuit, a charge pump system and a self-checking method. The capacitor self-checking circuit is characterized in that the output end of a charge pump unit is connected with an upper pole plate of a second capacitor through a current source and a first mode switching switch in sequence; the first resistor and the second mode change-over switch are connected in series between the upper pole plate and the lower pole plate of the first capacitor; the second resistor and the third mode change-over switch are connected in series between the upper pole plate of the first capacitor and the ground; the third resistor and the fourth mode change-over switch are connected in series between the upper pole plate of the second capacitor and the ground; the first comparator is connected with the upper and lower polar plates of the first capacitor and outputs a first detection result; and the second comparator is connected with the upper and lower polar plates of the second capacitor and outputs a second detection result. According to the capacitance self-checking circuit and method of the charge pump, detection items are more comprehensive, the detection time is short, the efficiency is high, the power consumption is low, and the cost is low; after the detection is completed, the system can be started immediately without an additional pre-charging link.

A charge pump includes a flying capacitor; a push-pull driver connected to a first end of the flying capacitor; a first switch provided between the first end of the flying capacitor and a first reference conductor; a second switch provided between a second end of the flying capacitor and the first reference conductor; and a third switch provided between the second end of the flying capacitor and an output terminal. The push-pull driver includes a fourth switch and a fifth switch, each of the fourth switch and the fifth switch having a first end connected to the first end of the flying capacitor. The fourth switch has a second end connected to a second reference conductor, the second reference conductor being different from the first reference conductor. The fifth switch has a second end connected to the first reference conductor.

The invention provides a charge pump circuit and a chip, in the charge pump circuit, a sampling circuit, a feedback circuit and a clock generation circuit are sequentially coupled and are coupled with a first charge pump and a second charge pump to form a loop, and in the initial stage of establishing the output of the charge pump circuit, the sampling circuit is used for carrying out primary charging on the output end of the charge pump circuit; when the input voltage rises to a corresponding value, the first charge pump and the second charge pump work at the same time, and when the voltage of the output end of the charge pump circuit reaches a target value, one of the first charge pump and the second charge pump stops working, so that the power consumption of the charge pump circuit in a steady state is effectively reduced; sectional charging and self-adaptive adjustment of a working mode are realized, and the vast majority of charging processes in an output establishment stage are completed by using an input voltage, so that the load pressure in the charge pump circuit is reduced. In addition, the sampling circuit also realizes parallel voltage sampling and ripple sampling, and the transient response capability of the charge pump circuit is enhanced.

One embodiment relates to A DC / DC converter for boosting an input voltage to a desired voltage and outputting same, comprising: a boost converter for boosting an input voltage to a first voltage; a voltage drop pump for reducing the input voltage to a second voltage; and a charge pump connected to the boost converter and the voltage drop pump, wherein the charge pump generates, as an output voltage, on the basis of the first voltage that is input from the boost converter and the second voltage that is input from the voltage drop pump, a third voltage boosted to be higher than the input voltage.

The invention relates to a circuit arrangement (12) for which an input voltage U is provided. E to a predetermined output voltage U A to increase. The circuit arrangement (12) comprises an electric charge pump, configured to alternately charge a first capacitor (16) with the input voltage U in a first operating step by means of a switching device (21) at a frequency f. E to charge and in a second step connect the first capacitor (16) to the input voltage U Eto connect in series. A microcontroller (20) is configured to control the switching device (21) and, within the first operating step, to set a capacitor charging time independent of the duration of the first operating step, wherein the capacitor charging time specifies a duty cycle T as the ratio of the capacitor charging time to one period of the frequency f, and the microcontroller (20) is configured to control the output voltage U A by varying the duty cycle T.

The invention belongs to the field of integrated circuits, and particularly relates to a charge pump circuit for a phase-locked loop, a charge pump module, the phase-locked loop and a communication chip. The charge pump circuit adopts a source switch single-end topology, and a numerical control current source DAC with an adaptive compensation circuit and two rail-to-rail operational amplifiers are applied. According to the source electrode switch single-end topology, the switch time sequence is dynamically optimized through a three-state working mode, and the charge injection effect and clock feed-through interference are remarkably reduced; the numerical control current source realizes multi-stage high-precision programmable current output according to a control code, responds to the change of output voltage in real time by utilizing a self-adaptive compensation mechanism, and maintains the stability of charging and discharging current; the rail-to-rail operational amplifier eliminates the common-mode constraint in a full-swing input range by connecting an NMOS-PMOS differential pair structure in parallel. The charge pump circuit overcomes the defects of a charge pump circuit adopted in an existing phase-locked loop in the aspects of output swing, stability and the like, static power consumption can be reduced to the microampere level, and the advantages are obvious.

In one example, a high voltage generation block comprises a temperature sensor to sense an operating temperature and output a temperature output, a trim circuit to receive a trim enable circuit and the temperature output and to generate oscillator trim bits, a charge pump oscillator to generate an oscillating signal in response to the oscillator trim bits and a feedback signal, a charge pump to receive the oscillating signal and to generate a pumped voltage, and a charge pump regulator to receive the pumped voltage and to generate the feedback signal and a high voltage output.

The invention relates to a charge pump circuit, a modulation method of the charge pump circuit and electronic equipment. The charge pump circuit comprises a charge pump module, a driving module, an obtaining module and a frequency adjusting module. The charge pump module is used for connecting a load and is configured to output a target voltage to the load in response to the adjusted target switching frequency based on the power supply voltage. And the driving module is connected with the charge pump module and is configured to respond to the adjusted target switching frequency to drive the charge pump module. The acquisition module is configured to acquire a pre-input signal corresponding to a load. And the frequency regulation module is connected with the acquisition module and the driving module, and is configured to regulate the magnitude of the target switching frequency in real time according to the pre-input signal. The switching frequency of the charge pump can be dynamically regulated and controlled, so that the output efficiency of the charge pump circuit is improved, and electromagnetic interference and switching loss are avoided.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

Circuits and methods are provided that more effectively and efficiently implement multi-level converter circuits. A system includes multi-level switching circuitry selectively couplable to one or more capacitors, multi-level control circuitry configurable to operate the multi-level switching circuitry in accordance with a selected mode of operation to convert an input voltage received at a first node to an output voltage at a second node, and an inductor switch couplable between the second node and one or more of a plurality of inductors including a first inductor and a second inductor. The first inductor has an inductance that is larger than the second inductor, and inductance control circuitry configurable to operate the inductor switch to select an inductance at the second node for the selected mode of operation by selectively coupling the second node to the first inductor, the second inductor, or a combination of the first inductor and second inductor.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.