15 results about "Capacitive divider" patented technology

A substrate processing system is disclosed and includes a sensor and at least one controller. The sensor is disposed at least partially within at least one component of a process chamber of the substrate processing system. The sensor includes a capacitive divider. The capacitive divider includes a first capacitor and a second capacitor connected in series. The first capacitor and the second capacitor include a conductive base layer and a conductive middle layer. The at least one controller is configured to: detect a first voltage of the conductive base layer and a second voltage of the conductive middle layer; based on the first voltage and the second voltage, determine a first plasma property of plasma in the process chamber; and adjust a parameter of the substrate processing system based on the first plasma property.

Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds / Vdg / Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.

A capacitive sensor having a cylindrical capacitor, for a conductor of a GIS. The capacitive sensor having at least two digital or analog temperature sensors.

The invention discloses a SiC variable-frequency power supply for a high-voltage series resonance withstand voltage test. The SiC variable-frequency power supply comprises a control module, a driving module, a three-phase rectifier bridge, a filter capacitor bank, a SiC inverter bridge and an outlet filter, the control module is used for logic control and clock control, and obtains a feedback signal of the capacitive voltage divider as a voltage reference; the driving module is used for performing voltage isolation on a power supply circuit and a driving signal and transmitting a control signal through a photoelectric isolation method, and the control signal is amplified and then drives a grid electrode of the MOSFET; the three-phase rectifier bridge is used for rectifying input three-phase alternating current into single-phase direct current, the filter capacitor bank is used for filtering the single-phase direct current, the SiC inverter bridge is used for rectifying the filtered single-phase direct current into alternating current, and the outlet filter is used for filtering the alternating current.

This invention relates to a vacuum drying oven and method for capacitor voltage dividers, comprising a drying chamber, with a gas filling chamber and a heating chamber arranged sequentially from top to bottom at the lower end of the drying chamber. The gas filling chamber is connected to a heating gas pipeline, and the heating chamber is connected to a high-temperature oil injection pipeline. Multiple vent holes at the lower end of the drying chamber communicate with the gas filling chamber. Additionally, a cavity is provided within the drying chamber wall, communicating with the gas filling chamber. An exhaust pipeline and a vacuum pipeline are provided on the drying chamber. Control valves for controlling the on / off state of the heating gas pipeline, high-temperature oil injection pipeline, exhaust pipeline, and vacuum pipeline are all provided on the pipelines. A core assembly frame is located inside the drying chamber, and the core assembly frame has multiple layers of support frames along its height. During drying, capacitor core assemblies are placed on the corresponding layers of support frames, with capacitor core assemblies on adjacent support frames placed vertically. This invention significantly improves the drying efficiency of capacitor core assemblies, and is particularly suitable for large-scale production.

A transistor memory device includes storage elements storing a capacitance including (1) a capacitance at a source of PFETs, (2) a capacitance at each storage element connected to a storage node and (3) a capacitance at a gate input of inverter transistors from the plurality of transistor storage elements. Each storage element configured to perform (i) a read data access (ii) a write data access, to increase static noise margin. The transistor memory device further includes a harvest node coupled to a ground and that is configured to store a harvested charge transferred from a selected bitline to increase an output voltage at the harvest node. The transistor memory device further includes a capacitor divider configured to maintain a voltage swing on a bitline. The transistor memory device further includes a harvest circuit configured to, in response to the read data access, decouple the harvest node and invert a voltage.

CMOS harvesting circuits are disclosed for conventional 6T SRAM bitcell arrays enabling substantial improvements to SRAM access time, pipeline performance and to SRAM active and leakage energy consumption—without scaling operating voltages while also improving Read and Write margins using assist schemes at very low area and energy overhead by reusing circuits that harvest charge.Active energy dissipation during an SRAM read access is lowered by use of novel sensing schemes that self-limit signal development on the BL without the energy overheads seen in conventional designs from sense-amp offsets, BL column leakage and uncertain read current. Improvements in access time are enabled by increasing the signal development rate on the BL—by comparing the rising electric potential of harvested charge with a decreasing BL voltage in a bitcell column using a novel and compact inverting amplifier with dynamic reset. This area and energy efficient scheme leveraging availability of harvested charge not only self-limits signal development on the BL to lower active power and improve read latency, but also eliminates most of the uncertainty of BL voltage signal from uncertain read current by using a capacitive divider. Charge harvested in each column of bitcells from a read / write access is moved to a local harvest grid with a fraction of the capacitance of the BLs accessed in the subarray, at a voltage closer to VDD and is readily tapped into during a following Write access lowering write energy consumption from the power grid by over 30%. Active or standby mode leakage is lowered by the raised voltage of the harvesting node in each column—that is discharged only before the WL selects—for all columns during a Read and for half-select columns during a Write.

A differential comparator circuit includes a voltage amplifier of negative gain receiving an analog input signal and generating an inverted analog input signal. The analog input signal and the inverted analog input signal form differential analog input signals. A comparator input circuit includes a first capacitive divider to generate a first signal as an average of the analog input signal and a first ramp signal, and a second capacitive divider to generate a second signal as an average of the inverted analog input signal and a second ramp signal, with the first and second ramp signals being differential ramp signals. The comparator is configured to compare the first and second signals to generate a signal transition having a timing based on the input signal.

An electrical sensor may include an electrode. The electrical sensor may include a first capacitive divider electrically coupled between the electrode and ground, the first capacitive divider including a first output. The electrical sensor may include a second capacitive divider electrically coupled between the first output and ground, the second capacitive divider including a second output. The electrical sensor may include a compensating circuit configured to receive, as inputs, the first output and the second output and to output a compensated voltage signal corresponding to a voltage of the electrode.

The present invention provides an electronic device comprising: a battery; a switched capacitor voltage divider (SCVD) including a plurality of switches and a flying capacitor, and configured to convert a voltage of power provided from the outside according to a designated ratio and supply the converted voltage to the battery or a system of the electronic device; a switch circuit disposed between the SCVD and a node for supplying power to the system; and a control circuit. The control circuit may be configured to identify a battery voltage output from the battery, control the plurality of switches such that the flying capacitor and the battery are connected in series in a first time interval of a switching period of the plurality of switches included in the SCVD, and control the plurality of switches such that the flying capacitor and the battery are connected in parallel in a second time interval of the switching period. On the basis of applying, to the switch circuit, a voltage obtained by adding a charging voltage of the flying capacitor and the battery voltage according to a duty ratio indicating a ratio of the first time interval to the switching period, a first voltage higher than a designated voltage may be supplied to the node through the switch circuit.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for implementing a SAR ADC circuit with improved quantization error. In some implementations, an apparatus includes an analog-to-digital converter (ADC) configured to receive a set of voltage signals and generate digital representations of signals. The ADC comprises a capacitive digital-to-analog converter (CDAC) comprising a capacitive divider circuit, the capacitive divider circuit comprising (i) a first capacitor in parallel with a second capacitor in a first branch, (ii) a plurality of capacitors in a plurality of other respective branches, and (iii) the CDAC configured to receive the set of sampled voltages and adjust each set of the sampled voltages by a first voltage or a second voltage through selection of one or more capacitors of the (i) first capacitor and the second capacitor and (ii) one or more of the plurality of capacitors.

A DC-DC converter circuit includes a high-side transistor, a low side transistor, a gate driver power supply, a converter control, and a capacitance divider network. The high-side transistor includes a high-side drain terminal, a high-side source terminal, and a high-side gate terminal. The high-side drain terminal is coupled to a positive DC supply terminal. The gate driver power supply is electrically isolated from the high-side transistor and the low-side transistor. The converter control is configured to supply high-side control commands and low-side control commands to the high-side transistor and the low-side transistor, respectively. The capacitance divider network includes a first capacitor and a second capacitor. The first capacitor is electrically connected in series, at a DC-link midpoint node, to the second capacitor. The DC-link midpoint node, the gate driver power supply, and the converter control are all electrically connected to, and share, a local electrical ground.

A line sensor is for being mounted to a power line. The line sensor includes: i) a housing for containing line sensor electronics; and ii) a voltage-sensing capacitor in connection with the housing. The line sensor is characterized by an electric circuit connected in parallel with the first capacitance for receiving a harvested voltage standing over the two capacitor plates, the electric circuit being configured for operating in an energy harvesting mode and / or a voltage-sensing mode. The line sensor is further characterized by a slot antenna integrated in the first, upper, one of the capacitor plates, wherein in the second, lower, one of the capacitor plates an opening allows radio-frequency waves generated by the slot antenna to be transmitted through the opening. Thereby a single component multi-purpose structure is formed enabling both the energy harvesting mode and the voltage sensing mode as well as wireless communication with other units.

An electrical sensor may include an electrode. The electrical sensor may include a first capacitive divider electrically coupled between the electrode and ground, the first capacitive divider including a first output. The electrical sensor may include a second capacitive divider electrically coupled between the first output and ground, the second capacitive divider including a second output. The electrical sensor may include a compensating circuit configured to receive, as inputs, the first output and the second output and to output a compensated voltage signal corresponding to a voltage of the electrode.