6274results about "Individual semiconductor device testing" patented technology

An object of the invention is to provide a probe card capable of properly performing a measurement. A probe card according to the invention includes: probes 100 shaped to allow vertical elastic deformation; a supporting substrate 200 with the probes provided on the lower surface thereof; a main substrate 300 positioned opposing the upper surface of the supporting substrate 200; an intermediate substrate 400 disposed between the supporting substrate 200 and main substrate 300; a supporting member 500 that is a column-shaped member with one end thereof attached to the center of the supporting substrate 200 and the other end thereof attached to the intermediate substrate 400 and holds the supporting substrate 200 so that the supporting substrate 200 is inclinable; and elastic members for holding the supporting substrate 200 so that the supporting substrate 200 is in a horizontal position relative to the main substrate 300, which are provided between the supporting substrate 200 and main substrate 300.

The invention discloses a wind power converter I-GBT monitoring system, particularly relates to the field of wind power converter I-GBT module monitoring, is used for solving the problem of inaccurate fault prediction and early warning in long-term operation, and is cooperatively realized through period division, parameter screening, index evaluation, dynamic adjustment and multi-stage early warning. The cycle division is used for identifying aging characteristics of the IGBT module in different life cycles and screening out monitoring parameters highly related to the state of the bonding wire. And through a multi-dimensional dynamic fusion model, the uniqueness of monitoring parameters is evaluated, and the accuracy of fault prediction is ensured. And the dynamic adjustment module dynamically optimizes the weight of the monitoring parameter according to the periodic change and the environment variable, so that the adaptability and the real-time performance of the monitoring are enhanced. The multi-stage early warning mechanism generates early warning signals of different grades according to changes of key parameters in a period, and potential faults are early warned in advance. The operation reliability of the wind power converter is improved, the sudden failure risk is reduced, and safe and stable operation of the system is guaranteed.

The invention discloses a semiconductor packaging device electromagnetic compatibility comprehensive test method and system, and belongs to the technical field of electromagnetic compatibility testing. The method comprises the following steps: collecting structure parameters, packaging topology and predefined function states of a to-be-tested packaging device, and constructing a polymorphic working model; establishing a disturbance injection control model according to each state and configuring disturbance source parameters; implementing dynamic disturbance injection and acquiring response data in a real working state of the device; performing time domain and frequency domain conjoint analysis on the response data, constructing an electromagnetic response dynamic feature sequence, inputting the electromagnetic response dynamic feature sequence into a machine learning model, extracting multi-dimensional coupling features and predicting tolerance; calculating performance indexes such as an interference tolerance score and a coupling strength index based on model output indexes, comparing the performance indexes with a standard, and evaluating a compatible risk level in a full state; the method realizes quantitative evaluation of the EMC performance of the packaging device with high reduction degree and multi-state coverage, and has the advantages of comprehensive test, accurate prediction, explainable attribution and the like.

The present invention discloses a system and method for quickly testing the anti-hydrolysis performance of LED chips, wherein the system comprises: a temperature and humidity regulator, the temperature and humidity regulator is provided with a cavity; a rotating device connected to the inner wall of the cavity, the rotating device can rotate along the inner wall of the cavity; a bracket, the bracket is a cup-shaped structure, the LED chip is mounted on the bracket and forms a conductive connection with the bracket; a test substrate, the bracket is fixed on the test substrate, and the bracket is conductively connected to the test substrate, and the test substrate is connected to the rotating device; the direction of the LED chip is adjusted by the rotating device, a reverse voltage is passed to the test substrate, and the temperature and humidity in the cavity are adjusted to perform an impact test on the LED chip. The direction of the LED chip is adjusted by the rotating device, and the hydrolysis speed of the LED chip is effectively accelerated, thereby shortening the detection time.

The invention relates to an inverter IGBT junction temperature prediction method and related equipment, and the method comprises the following steps: generating a loss characteristic spectrum through collecting IGBT electrical parameters and analyzing switching loss; calculating surface heat flux density, and constructing a heat flux distribution matrix. And performing thermal-electric coupling analysis by combining the two to obtain a junction temperature dynamic response sequence. Fourier transform is utilized to extract temperature fluctuation harmonic features, and a feature set is constructed; and extrapolating and predicting a junction temperature change trend based on the feature set, and outputting an IGBT junction temperature early warning signal through threshold judgment. The technical problem that the service life of a device is affected due to the fact that a large amount of loss is generated due to frequent switching actions in the working process of the inverter, the junction temperature of a chip rises and even temperature fluctuation occurs is solved.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

The invention relates to a probe suite multifunctional test method and system based on wafer test, and the method comprises the steps: obtaining the to-be-tested data of a wafer and the parameter information of a probe and a probe card; and through a preset intelligent algorithm, the contact state of the probe tip and the wafer is judged according to the working parameters, and the contact pressure and the probe impedance are dynamically adjusted. Meanwhile, environmental parameters including temperature, humidity and electromagnetic interference intensity in a test area are obtained, and when the environmental parameters exceed a preset range, the environment is automatically optimized. And detecting wafer characteristics based on the to-be-tested data, preprocessing the initial test data to obtain wafer test data, and performing real-time analysis and anomaly detection. And finally, according to an analysis detection result, whether the probe is adjusted or self-repaired is judged, and meanwhile, the test parameters and the working mode of the probe card are dynamically adjusted, so that high-precision and high-stability wafer test is realized, the performance of the probe and a test system is guaranteed, and the accuracy and the reliability of semiconductor test are improved.

The invention belongs to the technical field of semiconductor testing, and discloses a novel automatic detection system and method for the electrostatic protection performance of a power device. A distributed parasitic parameter network model is constructed by acquiring packaging structure parameters of a to-be-tested power device and physical layout data of a test fixture, key parasitic parameter distribution is identified in combination with a time domain reflection measurement technology, a waveform distortion coefficient is calculated, and a spatio-temporal evolution model of electrostatic pulse propagation is constructed. Based on the model, a compensatory predistortion waveform is generated to counteract the parasitic effect of a transmission path, a device port response signal is collected in real time, an energy dissipation characteristic spectrum is extracted through wavelet packet decomposition, and quantitative evaluation of the electrostatic protection performance is achieved. According to the invention, the test precision and repeatability are improved, and the method is suitable for electrostatic protection tests of various novel power devices, especially high-frequency wide-band gap devices.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving circuit and a control method thereof, the SiC MOSFET driving circuit comprises an active current source driving circuit, a SiC MOSFET, a load current detection circuit, a drain-source inter-electrode voltage overshoot detection circuit, an analog-to-digital conversion module and an FPGA (Field Programmable Gate Array) module, and a self-adaptive adjustment algorithm is built in the FPGA module. The load current detection circuit and the drain-source inter-electrode voltage overshoot detection circuit have low requirements for real-time performance, use of high-speed simulation devices is avoided, hardware design cost is reduced, a self-adaptive adjustment algorithm can adjust SiC MOSFET gate drive parameters in real time according to output of the load current detection circuit and the drain-source inter-electrode voltage overshoot detection circuit, and the self-adaptive adjustment algorithm can adjust the gate drive parameters of the SiC MOSFET in real time according to the output of the drain-source inter-electrode voltage overshoot detection circuit. Therefore, overshoot and switching loss are self-adaptively balanced, and safe operation of the SiC MOSFET is ensured. The technical problems that a SiC MOSFET driving circuit driven by an active grid is high in hardware cost and is difficult to balance voltage and current overshoot and switching loss are solved.

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

The invention discloses a scene self-adaptive aging test method and system for an extra-high voltage MOS (Metal Oxide Semiconductor), and relates to the related technical field of MOS test, and the method comprises the steps: building a device aging test platform; performing test condition analysis on the application scene information of the target extra-high voltage MOS device; performing pretest adjustment on the target extra-high voltage MOS device, and determining an aging test update parameter table; performing aging test monitoring on the target extra-high voltage MOS device; and calling an extra-high voltage MOS aging adaptive evaluator to process and evaluate the device aging scene test data stream set to obtain a device scene aging performance test result. The technical problems that in the prior art, due to the fact that an MOS aging test lacks scene adaptability, the aging process of the MOS device in the actual application environment is difficult to accurately simulate, the test pertinence is insufficient, and the result accuracy is poor are solved, and the technical effect of improving the MOS device aging test pertinence and the result accuracy is achieved.

The invention discloses an online aging state monitoring method and system for a silicon carbide MOSFET, and belongs to the technical field of semiconductor device monitoring, and the method specifically comprises the steps: collecting the working voltage, working current and junction temperature data of the silicon carbide MOSFET in real time, analyzing and processing the data through a data processing unit, and extracting the aging state characteristic parameters of the MOSFET; a dynamic aging state evaluation model fusing multi-source data and time sequence information is adopted to evaluate the aging state of the silicon carbide MOSFET, and a result is output to a display unit; according to the method, the aging state of the silicon carbide MOSFET is monitored, multi-level alarm strategies are set, different levels of alarm signals are triggered according to the aging state, meanwhile, feedback data are collected to optimize the state evaluation model, real-time and accurate monitoring of the aging state of the silicon carbide MOSFET is achieved, and the reliability and stability of a power electronic system are improved.

A chip tester, comprising: a support frame movable in the vertical direction and a movable plate movable in the horizontal direction. An upper test base is mounted on the support frame; a lower test base capable of moving to a position directly below the upper test base along with the movable plate is mounted on the movable plate; a recess is formed in a lower surface of the upper test base and / or an upper surface of the lower test base; when the chip tester is in a test state, the lower surface of the upper test base is tightly attached to the upper surface of the lower test base to form at the recess region a sealing cavity used for accommodating a chip to be tested; and a PCB and a partition plate are sequentially stacked above the upper test base. Flat attachment is ensured while realizing standard conversion after the upper test base and the lower test seat are subjected to mold closing, thereby improving the consistency of test data, and improving the safety of the chip in a high-current and high-voltage test state.

The invention proposes a semiconductor device test optimization method, and the method comprises the steps: initializing a test environment, obtaining the test data of a semiconductor, and automatically configuring the test environment; constructing a signal adjustment model to dynamically generate a preliminary test signal; designing a sensor network to monitor a preliminary test signal and response of the semiconductor device in real time, dynamically adjusting sensor data, and designing a data optimization acquisition strategy; dividing the parameters into a high priority and a low priority, dynamically compressing the parameters, implementing fast Fourier transform, extracting spectrum components as features, and analyzing the features; decompressing and preprocessing the compressed data, and performing deep fault analysis and positioning; and optimizing test data of the conductor, carrying out secondary test, and verifying a parameter adjustment result. According to the invention, the test quality and efficiency of the semiconductor device can be obviously improved, the product failure rate caused by insufficient test can be reduced, and the method plays an important role in semiconductor manufacturing industry, especially high-end chip production.

The invention relates to the technical field of semiconductor power device testing, in particular to a dynamic reverse bias testing method and system for a semiconductor power device, which can accurately evaluate the performance of the device under a dynamic reverse bias condition and improve the testing efficiency and accuracy. The method comprises the following steps: acquiring a plurality of electrical characteristic data of a to-be-detected semiconductor power device to obtain an electrical characteristic data set; inputting the electrical characteristic data set into a dynamic reverse bias test model to obtain a first dynamic reverse bias test result; transmitting a fast changing backward voltage pulse signal to the to-be-detected semiconductor power device to obtain an output signal after the backward voltage pulse signal passes through the to-be-detected semiconductor power device; judging whether the output signal exceeds a preset abnormal threshold value or not; if not, outputting the first dynamic reverse bias test result as a dynamic reverse bias test result of the semiconductor power device; and if yes, extracting the obtained abnormal output signal, and inputting the abnormal output signal into the dynamic reverse bias failure analysis model.

The invention discloses a dynamic on-resistance test circuit based on a gallium nitride transistor and a test method thereof. Belongs to the technical field of power electronics. The circuit comprises a DPT test circuit, a switch state switching circuit and a clamping circuit, the test method comprises the following steps: monitoring the voltage between test points on the clamping circuit and the current on the coaxial resistor to obtain the on resistance of the to-be-tested tube; the switching between the hard switching test and the soft switching test is realized by changing the switch interface. According to the invention, a gallium nitride transistor and a clamping circuit are introduced into a traditional double-pulse test circuit, and a dynamic on-resistance test function in a soft switching mode and a hard switching mode is integrated. Compared with a traditional testing circuit, the clamping circuit can capture the dynamic on-resistance within nanosecond time delay, meanwhile, the peak of the clamping voltage is greatly reduced, the testing precision is improved, and rapid and accurate measurement of the dynamic on-resistance is achieved.

The invention relates to the technical field of semiconductor testing, and provides a semiconductor testing method and device.The method comprises the steps that electric signal parameters, temperature data and optical image information of a semiconductor device are collected and processed, and a standardized electric signal sequence, a continuous temperature distribution curve and device surface topography features are obtained; analyzing the standardized electric signal sequence and the continuous temperature distribution curve to generate a dynamic working condition mapping matrix; and performing mode matching on the dynamic working condition mapping matrix by using a preset fault mode library, identifying potential defect types and position coordinates, inputting the device surface topography features and the potential defect types and position coordinates into a composite scoring model, generating a comprehensive quality score, and then performing grading to obtain a semiconductor test result. By generating the comprehensive quality score and then grading, the semiconductor test result is obtained, so that the accuracy of defect identification is improved, and the problems that the multi-dimensional correlation analysis is lacked and the dynamic working condition of the device is difficult to comprehensively evaluate in the semiconductor test are solved.

The invention provides a wafer testing device capable of being rapidly maintained, and relates to the technical field of semiconductors, the wafer testing device comprises a fixed plate, the fixed plate is provided with a control module, and a power supply module, a probe card, a heating lifting module and at least one testing module which are connected with the control module, and a wafer to be tested is integrally arranged in the probe card. The power supply module is connected with the probe card to supply power to the to-be-tested wafer, a heater and a probe are arranged in the heating lifting module, and the heating lifting module is used for driving the to-be-tested wafer in the probe card to be in contact with the probe and heating the to-be-tested wafer. The test module comprises a bottom plate which is in push-pull connection with the fixed plate along the first direction and a switch array measurement assembly which is arranged on the bottom plate and is in plug-in connection with the bottom plate along the second direction, and the switch array measurement assembly is used for testing different parameters of the to-be-tested wafer when the to-be-tested wafer is in contact with the probe. The switch array measurement assembly is in plug-in connection with the bottom plate, and the bottom plate is in push-pull connection with the fixed plate, thereby facilitating the replacement of the test module, and achieving the quick disassembly and assembly.

To provide a technique advantageous for moving a stage on which an electronic component is placed.SOLUTION: A stage moving mechanism 13 for moving a stage 12 with respect to a base 11 comprises: a first direction driving unit having a first direction driving source 20 and a first direction movable portion 21 that is moved in a first direction dX together with the stage by a driving force output from the first direction driving source; a second direction driving unit having a second direction driving source 30 and a second direction movable portion 31 that is moved in a second direction together with the stage by a driving force output from the second direction driving source; a first direction guide unit 15 that allows the stage to move in the first direction with respect to the base; and a second direction guide unit 16 that allows the stage to move in the second direction with respect to the base.SELECTED DRAWING: Figure 1

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The invention relates to a power device online test system and a power device test control method. The system comprises an upper computer, a test board and a digital signal generator, the test board and the digital signal generator are connected with the upper computer, n aging circuits, driving circuits and measuring circuits are integrated on the test board, and the upper computer is used for determining test parameters of periodic tests of at least one to-be-tested power device and determining the test parameters of the to-be-tested power device for each test. Determining a performance test type of the to-be-tested power device according to the test parameters, generating a performance test instruction corresponding to the performance test type, and sending the performance test instruction to a digital signal generator; generating a corresponding pulse test signal, and transmitting the pulse test signal to the driving circuit; a relay in a test channel is controlled to be switched on and / or switched off according to the pulse test signal, a performance test corresponding to the performance test type is achieved for the to-be-tested power device through the test channel, and the test channel comprises an aging circuit and a measuring circuit.

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

To provide a technique advantageous for moving a stage on which an electronic component is placed.SOLUTION: A stage moving mechanism 13 for moving a stage 12 with respect to a base 11 comprises: XY moving devices 20 and 30 for moving the stage with respect to a base in XY directions dX and dY forming a right angle with respect to a rotation axis A; and a rotation moving device for rotating the stage with respect to the base in a rotation direction about the rotation axis. The rotation moving device includes: a rotation direction driving source 70; a rotation support portion 71 rotated in a rotation direction dR together with the stage by a driving force output from the rotation direction driving source; and a rotation relay portion 72 for transmitting the driving force output from the rotation direction driving source to the rotation support portion while allowing the rotation support portion to move in the XY directions with respect to the rotation direction driving source.SELECTED DRAWING: Figure 1

The invention relates to a fault diagnosis method of a photovoltaic inverter, a computer program product and equipment. The fault diagnosis method comprises the following steps: applying a test input signal to a photovoltaic inverter to be diagnosed, and collecting an actual measurement test signal of the photovoltaic inverter in response to the test input signal; performing analog simulation on the test input signal by using a photovoltaic inverter model pre-generated by the photovoltaic inverter to obtain an analog test signal; and comparing the actual measurement test signal with the simulation test signal to obtain the operation state of the photovoltaic inverter. According to the invention, whether the photovoltaic inverter is in an abnormal operation state or not can be known conveniently and quickly by comparing the actual measurement test signal with the simulation test signal. Furthermore, when the photovoltaic inverter is in an abnormal operation state, possible fault reasons of the photovoltaic inverter can be quickly positioned by analyzing the difference value between the actual measurement test signal and the simulation test signal, and a control scheme or a design scheme of the photovoltaic inverter can be adjusted.

Power switch device includes a wide-bandgap semiconductor switch, and a gate driver. The gate driver includes a driver circuit and a diagnostic circuit. The driver circuit is configured to provide a driver signal to control the wide-bandgap semiconductor switch. The diagnostic circuit is configured to sense an electrical characteristic of the wide-bandgap semiconductor switch, and perform a diagnostic test for the wide-bandgap semiconductor switch in response to the electrical characteristic of the wide-bandgap semiconductor switch.

The invention discloses a fault detection method and system for a fan frequency converter based on big data, and relates to the technical field of fault detection, and the method comprises the steps: arranging a sensor group, and obtaining the real-time operation data of the fan frequency converter; performing entity identification on the historical fault description data to obtain associated parameters of fault types; assigning an initial weight to the associated parameter of each fault type; calculating a real-time deviation ratio, a fault prediction accuracy error and a statistical deviation; calculating a dynamic adjustment coefficient obtained by real-time feedback of each sensor parameter; calculating an error index of each parameter, and optimizing a dynamic adjustment coefficient through a gradient descent algorithm; and calculating a comprehensive fault index by adopting the optimized dynamic adjustment coefficient, and establishing a hierarchical early warning mechanism. The technical problems that potential faults of the frequency converter are difficult to accurately and timely detect in the prior art, so that the operation efficiency of a fan is reduced, even serious consequences are generated, and normal production and operation are influenced are solved.

The invention discloses a SiC MOSFET junction temperature monitoring circuit and monitoring method based on high-frequency oscillation suppression. The SiC MOSFET junction temperature monitoring circuit comprises a SiC MOSFET to be detected, a PCB mutual inductance coil, a high-frequency oscillation extraction unit, a grid adjustable driving unit and a junction temperature evaluation unit. According to the system, the oscillation time of the transient drain current of the SiC MOSFET switch is used as a temperature-sensitive electrical parameter to represent the junction temperature of the device, and the temperature sensitivity of the oscillation time can be improved by adjusting the grid amplifier to suppress high-frequency oscillation. According to the invention, the rapid detection of the junction temperature of the SiC MOSFET is realized, and the sensitivity of temperature-sensitive electrical parameters and the detection integration level are superior to those of a traditional junction temperature monitoring method.

The invention discloses a semiconductor probe card electrical parameter extraction method and system based on an MEMS technology, and relates to the technical field of semiconductor testing, the method comprises the following components: initialization setting: aligning an MEMS probe card to a target test area on a wafer to be tested, firmly fixing the probe card and the wafer together by using a mechanical clamping device, and setting the MEMS probe card and the wafer to be tested; by integrating the decision tree model and the genetic algorithm, accurate mapping and optimization of semiconductor wafer surface features and optimal probe contact parameters are achieved, the intelligent level of testing is improved, the test time is shortened, the test efficiency is improved, and the test cost is reduced. The self-adaptability and stability of the testing process are remarkably enhanced, real-time adjustment of probe contact parameters is ensured through a dynamic monitoring and closed-loop control mechanism, the testing error is effectively reduced, the testing precision is improved, the optimal contact parameter combination is found through an optimization algorithm, the testing period is further shortened, and the testing efficiency is improved.

The invention provides an IGBT junction temperature prediction method and system based on dynamic thermal impedance correction. The method comprises the following steps: acquiring temperature data in real time, reversely deducing IGBT loss in combination with a pre-constructed thermal network model, and storing the IGBT loss in historical data; obtaining an IGBT loss average value under the same working condition, and calculating a difference value between the IGBT loss average value and the IGBT loss and a specific value of the IGBT loss average value to obtain a loss offset coefficient; judging whether the loss deviation coefficient is continuously greater than a preset value in a continuous period, if so, judging that the heat-conducting silicone grease is aged, calculating an aging coefficient through loss data and temperature data in the continuous period, and correcting the thermal network model by adopting the aging coefficient; and obtaining the corrected internal transient thermal impedance of the IGBT and the loss of the IGBT, and further predicting the junction temperature of the IGBT. According to the method, the thermal network model is adopted to reversely deduce the real-time loss power of the IGBT, and electric parameter drift errors are avoided; and a dynamic thermal impedance correction mechanism is introduced to ensure long-term accuracy of junction temperature prediction.

The invention provides an ion energy distribution testing device for immersed plasma injection equipment. The ion energy distribution testing device comprises a Faraday cup, a biasing circuit, a data acquisition unit and an upper computer, the Faraday cup is arranged around the wafer and configured to collect plasma energy around the wafer, and the plasma energy is converted into a current signal at a collector of the Faraday cup; the bias circuit is configured to apply bias voltage to the grid mesh of the Faraday cup under the enabling of the data acquisition unit; and the data acquisition unit is configured to drive the biasing circuit, acquire a current signal of the collector of the Faraday cup and a voltage signal of the grid, and upload the current signal and the voltage signal to an upper computer. According to the invention, through the design of the Faraday cups and the bias circuit, the whole measuring device can realize ion energy distribution measurement under high voltage, and the distribution condition and uniformity of ion energy around the wafer can be tested in cooperation with the arrangement of the plurality of Faraday cups.