3987results about "Individual semiconductor device testing" patented technology

An object of the invention is to provide a probe card capable of properly performing a measurement. A probe card according to the invention includes: probes 100 shaped to allow vertical elastic deformation; a supporting substrate 200 with the probes provided on the lower surface thereof; a main substrate 300 positioned opposing the upper surface of the supporting substrate 200; an intermediate substrate 400 disposed between the supporting substrate 200 and main substrate 300; a supporting member 500 that is a column-shaped member with one end thereof attached to the center of the supporting substrate 200 and the other end thereof attached to the intermediate substrate 400 and holds the supporting substrate 200 so that the supporting substrate 200 is inclinable; and elastic members for holding the supporting substrate 200 so that the supporting substrate 200 is in a horizontal position relative to the main substrate 300, which are provided between the supporting substrate 200 and main substrate 300.

The invention discloses a semiconductor packaging device electromagnetic compatibility comprehensive test method and system, and belongs to the technical field of electromagnetic compatibility testing. The method comprises the following steps: collecting structure parameters, packaging topology and predefined function states of a to-be-tested packaging device, and constructing a polymorphic working model; establishing a disturbance injection control model according to each state and configuring disturbance source parameters; implementing dynamic disturbance injection and acquiring response data in a real working state of the device; performing time domain and frequency domain conjoint analysis on the response data, constructing an electromagnetic response dynamic feature sequence, inputting the electromagnetic response dynamic feature sequence into a machine learning model, extracting multi-dimensional coupling features and predicting tolerance; calculating performance indexes such as an interference tolerance score and a coupling strength index based on model output indexes, comparing the performance indexes with a standard, and evaluating a compatible risk level in a full state; the method realizes quantitative evaluation of the EMC performance of the packaging device with high reduction degree and multi-state coverage, and has the advantages of comprehensive test, accurate prediction, explainable attribution and the like.

The invention relates to an inverter IGBT junction temperature prediction method and related equipment, and the method comprises the following steps: generating a loss characteristic spectrum through collecting IGBT electrical parameters and analyzing switching loss; calculating surface heat flux density, and constructing a heat flux distribution matrix. And performing thermal-electric coupling analysis by combining the two to obtain a junction temperature dynamic response sequence. Fourier transform is utilized to extract temperature fluctuation harmonic features, and a feature set is constructed; and extrapolating and predicting a junction temperature change trend based on the feature set, and outputting an IGBT junction temperature early warning signal through threshold judgment. The technical problem that the service life of a device is affected due to the fact that a large amount of loss is generated due to frequent switching actions in the working process of the inverter, the junction temperature of a chip rises and even temperature fluctuation occurs is solved.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

The invention relates to a probe suite multifunctional test method and system based on wafer test, and the method comprises the steps: obtaining the to-be-tested data of a wafer and the parameter information of a probe and a probe card; and through a preset intelligent algorithm, the contact state of the probe tip and the wafer is judged according to the working parameters, and the contact pressure and the probe impedance are dynamically adjusted. Meanwhile, environmental parameters including temperature, humidity and electromagnetic interference intensity in a test area are obtained, and when the environmental parameters exceed a preset range, the environment is automatically optimized. And detecting wafer characteristics based on the to-be-tested data, preprocessing the initial test data to obtain wafer test data, and performing real-time analysis and anomaly detection. And finally, according to an analysis detection result, whether the probe is adjusted or self-repaired is judged, and meanwhile, the test parameters and the working mode of the probe card are dynamically adjusted, so that high-precision and high-stability wafer test is realized, the performance of the probe and a test system is guaranteed, and the accuracy and the reliability of semiconductor test are improved.

The invention belongs to the technical field of semiconductor testing, and discloses a novel automatic detection system and method for the electrostatic protection performance of a power device. A distributed parasitic parameter network model is constructed by acquiring packaging structure parameters of a to-be-tested power device and physical layout data of a test fixture, key parasitic parameter distribution is identified in combination with a time domain reflection measurement technology, a waveform distortion coefficient is calculated, and a spatio-temporal evolution model of electrostatic pulse propagation is constructed. Based on the model, a compensatory predistortion waveform is generated to counteract the parasitic effect of a transmission path, a device port response signal is collected in real time, an energy dissipation characteristic spectrum is extracted through wavelet packet decomposition, and quantitative evaluation of the electrostatic protection performance is achieved. According to the invention, the test precision and repeatability are improved, and the method is suitable for electrostatic protection tests of various novel power devices, especially high-frequency wide-band gap devices.

The invention discloses an E-mode device nonlinear current model parameter extraction method considering a gate current effect, and relates to the technical field of enhanced device modeling. Comprising the following steps: establishing a nonlinear current model of an E-mode device; extracting parasitic resistance of the transistor; removing the influence of parasitic resistance of the transistor, and calculating gate-source and gate-drain node voltages of an intrinsic region in the nonlinear current model to obtain an intrinsic gate-source voltage and an intrinsic drain-source voltage; extracting intrinsic gate current model parameters; obtaining the drain-source current component of the intrinsic part from the influence of the fused gate current component in the actually measured drain-source current of the transistor; extracting intrinsic nonlinear drain-source current model parameters; and substituting the intrinsic nonlinear drain-source current model parameter value into an intrinsic nonlinear drain-source current model equation for verification. According to the method, gate current component calculation is introduced into a traditional nonlinear current model parameter extraction method, and accurate extraction of intrinsic nonlinear current source parameters is achieved.

To provide a technique advantageous for moving a stage on which an electronic component is placed.SOLUTION: A stage moving mechanism 13 for moving a stage 12 with respect to a base 11 comprises: a first direction driving unit having a first direction driving source 20 and a first direction movable portion 21 that is moved in a first direction dX together with the stage by a driving force output from the first direction driving source; a second direction driving unit having a second direction driving source 30 and a second direction movable portion 31 that is moved in a second direction together with the stage by a driving force output from the second direction driving source; a first direction guide unit 15 that allows the stage to move in the first direction with respect to the base; and a second direction guide unit 16 that allows the stage to move in the second direction with respect to the base.SELECTED DRAWING: Figure 1

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

To provide a technique advantageous for moving a stage on which an electronic component is placed.SOLUTION: A stage moving mechanism 13 for moving a stage 12 with respect to a base 11 comprises: XY moving devices 20 and 30 for moving the stage with respect to a base in XY directions dX and dY forming a right angle with respect to a rotation axis A; and a rotation moving device for rotating the stage with respect to the base in a rotation direction about the rotation axis. The rotation moving device includes: a rotation direction driving source 70; a rotation support portion 71 rotated in a rotation direction dR together with the stage by a driving force output from the rotation direction driving source; and a rotation relay portion 72 for transmitting the driving force output from the rotation direction driving source to the rotation support portion while allowing the rotation support portion to move in the XY directions with respect to the rotation direction driving source.SELECTED DRAWING: Figure 1

The invention relates to a fault diagnosis method of a photovoltaic inverter, a computer program product and equipment. The fault diagnosis method comprises the following steps: applying a test input signal to a photovoltaic inverter to be diagnosed, and collecting an actual measurement test signal of the photovoltaic inverter in response to the test input signal; performing analog simulation on the test input signal by using a photovoltaic inverter model pre-generated by the photovoltaic inverter to obtain an analog test signal; and comparing the actual measurement test signal with the simulation test signal to obtain the operation state of the photovoltaic inverter. According to the invention, whether the photovoltaic inverter is in an abnormal operation state or not can be known conveniently and quickly by comparing the actual measurement test signal with the simulation test signal. Furthermore, when the photovoltaic inverter is in an abnormal operation state, possible fault reasons of the photovoltaic inverter can be quickly positioned by analyzing the difference value between the actual measurement test signal and the simulation test signal, and a control scheme or a design scheme of the photovoltaic inverter can be adjusted.

Power switch device includes a wide-bandgap semiconductor switch, and a gate driver. The gate driver includes a driver circuit and a diagnostic circuit. The driver circuit is configured to provide a driver signal to control the wide-bandgap semiconductor switch. The diagnostic circuit is configured to sense an electrical characteristic of the wide-bandgap semiconductor switch, and perform a diagnostic test for the wide-bandgap semiconductor switch in response to the electrical characteristic of the wide-bandgap semiconductor switch.

The invention discloses a fault detection method and system for a fan frequency converter based on big data, and relates to the technical field of fault detection, and the method comprises the steps: arranging a sensor group, and obtaining the real-time operation data of the fan frequency converter; performing entity identification on the historical fault description data to obtain associated parameters of fault types; assigning an initial weight to the associated parameter of each fault type; calculating a real-time deviation ratio, a fault prediction accuracy error and a statistical deviation; calculating a dynamic adjustment coefficient obtained by real-time feedback of each sensor parameter; calculating an error index of each parameter, and optimizing a dynamic adjustment coefficient through a gradient descent algorithm; and calculating a comprehensive fault index by adopting the optimized dynamic adjustment coefficient, and establishing a hierarchical early warning mechanism. The technical problems that potential faults of the frequency converter are difficult to accurately and timely detect in the prior art, so that the operation efficiency of a fan is reduced, even serious consequences are generated, and normal production and operation are influenced are solved.

The invention provides an IGBT junction temperature prediction method and system based on dynamic thermal impedance correction. The method comprises the following steps: acquiring temperature data in real time, reversely deducing IGBT loss in combination with a pre-constructed thermal network model, and storing the IGBT loss in historical data; obtaining an IGBT loss average value under the same working condition, and calculating a difference value between the IGBT loss average value and the IGBT loss and a specific value of the IGBT loss average value to obtain a loss offset coefficient; judging whether the loss deviation coefficient is continuously greater than a preset value in a continuous period, if so, judging that the heat-conducting silicone grease is aged, calculating an aging coefficient through loss data and temperature data in the continuous period, and correcting the thermal network model by adopting the aging coefficient; and obtaining the corrected internal transient thermal impedance of the IGBT and the loss of the IGBT, and further predicting the junction temperature of the IGBT. According to the method, the thermal network model is adopted to reversely deduce the real-time loss power of the IGBT, and electric parameter drift errors are avoided; and a dynamic thermal impedance correction mechanism is introduced to ensure long-term accuracy of junction temperature prediction.

The invention discloses an IGBT driver fault prediction method and a safety system, and relates to the technical field of power electronics, and the method comprises the steps: constructing a dynamic causal reasoning matrix based on degradation characteristics, and carrying out the reverse reasoning of an accidental fault mode of an IGBT driver through the dynamic causal reasoning matrix; establishing a multi-stage fault prediction model based on the accidental fault mode of the IGBT driver, and predicting the fault occurrence frequency of each life cycle stage of the IGBT driver by using the multi-stage fault prediction model; and identifying a vulnerable element in the IGBT driver based on the fault occurrence frequency, performing fault tracing analysis on the vulnerable element, and optimizing the multi-stage fault prediction model according to a tracing analysis result. According to the method, the causal structure model with the dynamic evolution ability and the causal tracing ability is constructed, the search space of the causal relationship is effectively compressed, and the accuracy and expression ability of the causal path are improved.

The present invention provides an electro-conductive contact pin which can implement a narrow-pitch and an inspection device including same. Furthermore, the present invention provides an electro-conductive contact pin which uses a guide housing formed to have consistent thickness overall, including a portion corresponding to a lower part of an interference member and prevents damage due to interference with the interference member, and an inspection device including same.

The invention discloses a multi-source heterogeneous data processing method and system based on a test chip, and the method comprises the steps: employing a distributed message queue to access a multi-protocol data stream in real time, collecting the multi-source heterogeneous data related to a chip test, and carrying out the normalization preprocessing; performing cross-domain spatio-temporal feature alignment and mapping on the preprocessed multi-source heterogeneous data, constructing a hybrid incidence matrix based on linear correlation degree and nonlinear correlation degree, extracting three-dimensional joint features, and generating a dynamic metadata tag; generating nodes and edges by using the incidence matrix and the extracted three-dimensional joint features, constructing a parameter association graph structure, performing graph embedding training and generating an index structure, positioning Top-K candidates based on the index structure by using query features and labels, and sorting and returning a result according to a comprehensive distance; the problem that cross-domain association analysis is difficult to carry out due to the fact that the format difference of multi-source heterogeneous data generated by existing chip testing is large is solved, and the precision and efficiency of multi-source heterogeneous data processing are improved.

The present application relates to the technical field of power module loss determination. Specifically, provided are a method for determining the loss of an IGBT power module, and a storage medium and a computer device, wherein the IGBT power module operates in a DPWM mode. The method comprises: acquiring present phase current information of an IGBT power module, present busbar voltage information thereof and present power factor angle information thereof; acquiring the present modulation ratio information in a DPWM mode; and determining the present loss of the IGBT power module on the basis of the present phase current information, the present busbar voltage information, the present power factor angle information and the present modulation ratio information, wherein there is a linear relationship between the present phase current information and the present loss, between the present busbar voltage information and the present loss, and between the present modulation ratio information and the present loss. By means of the technical solution provided in the present application, losses of power modules can be more conveniently and accurately determined in real time in a DPWM mode, thereby significantly reducing a system load rate.

The present disclosure relates to a tester, a test system, and a test method. The tester comprises a plurality of function boards, a main control module, and a co-processing module. The function boards implement different functions. The main control module is connected to the function boards and the host respectively and is configured to receive test item(s) sent by the host and send test sequences in the test item(s) to the function boards. The plurality of function boards is connected to at least one device under test, and is configured to send excitation signals to the at least one device under test according to the received test sequences, and receive response signals fed back by the at least one device under test based on the excitation signals, obtain test data, and send the test data to the co-processing module. The co-processing module is connected to the plurality of function boards respectively, and is configured to process the test data obtained by the function boards to obtain test result(s), and send them to the host. The present disclosure can improve the testing efficiency.

The invention belongs to the technical field of semiconductor defect detection, and relates to a deep learning-based deep energy level defect identification method, system and device, and a medium. According to the method, transient curve data of an external capacitor is modulated to obtain a time sequence feature vector containing time, temperature and bias voltage information, then a multi-defect-induced weighted capacitor feature vector is obtained through calculation and modulation of a neural network model, and the time sequence feature vector and the multi-defect-induced weighted capacitor feature vector are trained after being spliced. Until the neural network model converges, the trained neural network model predicts a defect parameter vector, defect weight distribution and transient capacitance response at the (i + 1) th moment at the ith moment; according to the method, DLTS test data is modeled and analyzed in combination with a deep learning algorithm and a semiconductor deep energy level defect kinetic model, precise recognition and quantification of a complex defect system are achieved, the problem that defect recognition precision is insufficient in an existing DLTS test method is solved, and meanwhile the method is low in requirement for test equipment and high in applicability.

The invention provides a single-phase four-quadrant rectifier IGBT open-circuit fault diagnosis method under multiple working conditions, and relates to the technical field of IGBT fault diagnosis. Historical data of alternating current side voltage, alternating current side current and direct current side voltage of the single-phase four-quadrant rectifier are obtained, and a total harmonic distortion rate threshold value, a direct current side voltage threshold value and an alternating current side current first threshold value are obtained. And constructing and training an IGBT open-circuit fault positioning identification model. Detecting the total harmonic distortion rate of the alternating-current side current of the single-phase four-quadrant rectifier in real time, if the total harmonic distortion rate exceeds a threshold value, entering fault positioning, collecting and calculating the average value of the direct-current side voltage and the alternating-current side current in the period, and judging the fault of the single-phase four-quadrant rectifier under the specific working condition according to the comparison of the average value and the threshold value. Or using an IGBT open-circuit fault positioning identification model to diagnose the fault; if the threshold value is not exceeded, the next period is continuously monitored. According to the invention, the IGBT fault diagnosis efficiency and accuracy of the single-phase four-quadrant rectifier are improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) transistors, and discloses a method and a device for testing a packaging level of an MOS transistor. The method comprises the following steps: applying a multi-frequency pulse signal to a packaged MOS transistor to obtain MOS transistor response data under different frequencies; performing parameter synchronous acquisition on the MOS transistor response data to obtain original test data; performing packaging parasitic effect compensation processing on the original test data to obtain corrected test data; performing signal characteristic decomposition on the correction test data to obtain a characteristic parameter set of the MOS transistor; and packaging defect analysis is carried out based on the characteristic parameter set, and a defect identification report is obtained. According to the invention, hidden dangers causing device failure can be identified in advance, and the safety of high-power application is greatly improved.

The invention discloses a junction temperature testing device and method for a high-electron-mobility transistor. A current measuring module in the junction temperature testing device for the high-electron-mobility transistor is used for acquiring current flowing through a tested device; the power supply module is electrically connected with the other end of the switch module, and the power supply module and the switch module are connected in parallel with the bus capacitor; the control module is electrically connected with the control end, the driving end and the regulation and control end of the switch module, and the control module is used for providing switching signals for the control end, the driving end and the regulation and control end of the switch module so as to control the switching states of the switch protection module, the tested device and the switch module; the heating plate is used for heating a tested device; the temperature detection module is used for measuring the temperature of the detected device; and the waveform analysis module is electrically connected with the control module, the temperature detection module and the current measurement module, and is used for obtaining and forming an experimental oscillogram of the tested device at the temperature according to the temperature, the current and the conduction time of the tested device controlled by the control module.

The invention relates to the technical field of automobile inflator pump monitoring, and discloses an automobile inflator pump and a dynamic voltage monitoring control system thereof. The system comprises a voltage data acquisition module, a dynamic noise suppression module, a voltage fluctuation modeling module, a self-adaptive compensation control module and the like. The voltage data acquisition module acquires and processes multi-dimensional data, the dynamic noise suppression module removes noise, the voltage fluctuation modeling module extracts voltage and load correlation characteristics, and the adaptive compensation control module optimizes control parameters to stabilize the voltage. In addition, the system is further provided with a digital twinborn simulation module monitoring gas circuit, a distributed updating module optimization model based on federated learning, a redundancy protection circuit guarantee safety, and a fault mode library for providing preventive maintenance suggestions. The system can improve the running stability, safety and efficiency of the automobile inflator pump, and effectively overcomes the defects of a traditional inflator pump in the aspects of voltage monitoring control and the like.

The utility model provides a high-voltage pulse generating device and a test system. The high-voltage pulse generating device comprises a main control unit, a driving circuit, a pulse control circuit with a wide bandgap semiconductor power device, and an output circuit, the first end of the main control unit is coupled with the first end of the driving circuit, the second end of the driving circuit is coupled with the first end of the pulse control circuit, and the second end of the pulse control circuit is coupled with the output circuit; the main control unit is configured to generate two paths of first PWM (Pulse Width Modulation) signals with dead time control; the two paths of first PWM signals are sent to the driving circuit; and the driving circuit is configured to process the first PWM signal and then drive the pulse control circuit, so that the output circuit generates a high-voltage pulse signal. According to the utility model, the structure is simple, the cost can be greatly reduced, the output pulse speed can be flexibly set, and the CMTI test requirements of different isolated gate drivers can be met.

The invention relates to the technical field of power electronic equipment monitoring, in particular to a power semiconductor fault early-warning method and system based on data driving, and the method comprises the steps: receiving a fault early-warning instruction of a power semiconductor, determining a fault early-warning system based on the fault early-warning instruction, obtaining an electrical evaluation node based on the power semiconductor, and determining the fault early-warning system based on the electrical evaluation node. Based on a preset electrical monitoring time period, a preset electrical monitoring time interval and an electrical parameter node set obtained by the electrical parameter monitoring unit, a frequency evaluation proportion is obtained by using a low-frequency monitoring module and a high-frequency monitoring module; a primary monitoring state of the power semiconductor is confirmed based on an electrical parameter node set, a frequency evaluation proportion and an electrical evaluation node, a monitoring temperature set and a temperature change rate set are acquired by using a temperature monitoring module set, and a secondary monitoring state of the power semiconductor is confirmed based on a comprehensive monitoring temperature value and the temperature change rate set. And fault early warning of the power semiconductor is realized. According to the invention, the accuracy and reliability of power semiconductor fault early warning can be improved.

The invention discloses a low-temperature CMOS carrier MFP and microscopic parameter extraction method and system, which are corresponding schemes, in the scheme, a carrier MFP extraction model for eliminating a microscopic unknown quantity is constructed by utilizing a geometric scaling rule of quasi-ballistic transport and an existing effective mobility extraction technology, and an MFP extraction model for eliminating the microscopic unknown quantity is constructed by utilizing the geometric scaling rule of quasi-ballistic transport and the existing effective mobility extraction technology; the MFP extracted by the carrier MFP extraction model is ensured to be a pure experiment observation value on the basis that effective quality, Fermi velocity and scattering time do not need to be predicted based on the self-consistency of macroscopic current and voltage data along with the change of channel length; meanwhile, on the basis, the microcosmic parameters are decoupled, so that the decoupled microcosmic parameters are extracted one by one; compared with an existing scheme, the method can be directly applied to a standard wafer-level test board in the industry, MFP distribution of hundreds of devices can be rapidly counted, and a feasible engineering scheme is provided for low-temperature process monitoring.

The invention discloses an aging performance evaluation method and platform for a super junction MOS device, and relates to the technical field of performance evaluation, and the method comprises the steps: carrying out the test scene matching, and obtaining a target acceleration test scene group; calling a plurality of aging trend curves according to the target acceleration test scene group; locally calling a historical operation data set of the to-be-tested super junction MOS device; performing degradation feature extraction on the historical operation data set to obtain multiple groups of historical operation time sequence fragments; performing degradation increment correlation prediction on multiple groups of historical operation time sequence fragments, and outputting a device aging time sequence trend curve; comparing the aging time sequence trend curve of the device based on a preset failure threshold value, and outputting the remaining service life of the device; and interactively obtaining an equipment life design index of the target power electronic system, and quantitatively outputting an aging performance evaluation result in combination with the residual service life of the device. The technical problem that the aging performance evaluation accuracy is insufficient in the prior art is solved, and the technical effect of improving the aging performance evaluation precision is achieved.

A chip test system and method are provided. The chip test system includes a memory chip, a test device, and a test interface. The memory chip has a power pad and a driver pad coupled to the power pad. The test device is configured to provide a test signal. The test interface is configured to provide multiple signal transmission paths. The test device transmits the test signal to the power pad of the memory chip through the test interface, obtains a monitor voltage generated by the driver pad, and adjusts a test voltage value of the test signal according to the monitor voltage. The test device comprises a precise measurement unit configured to measure the monitor voltage, and a switch element coupled to the precise measurement unit, and when the memory chip starts to be tested, the switch element is turned on.