2758results about "Individual semiconductor device testing" patented technology

An object of the invention is to provide a probe card capable of properly performing a measurement. A probe card according to the invention includes: probes 100 shaped to allow vertical elastic deformation; a supporting substrate 200 with the probes provided on the lower surface thereof; a main substrate 300 positioned opposing the upper surface of the supporting substrate 200; an intermediate substrate 400 disposed between the supporting substrate 200 and main substrate 300; a supporting member 500 that is a column-shaped member with one end thereof attached to the center of the supporting substrate 200 and the other end thereof attached to the intermediate substrate 400 and holds the supporting substrate 200 so that the supporting substrate 200 is inclinable; and elastic members for holding the supporting substrate 200 so that the supporting substrate 200 is in a horizontal position relative to the main substrate 300, which are provided between the supporting substrate 200 and main substrate 300.

The invention belongs to the technical field of semiconductor testing, and discloses a novel automatic detection system and method for the electrostatic protection performance of a power device. A distributed parasitic parameter network model is constructed by acquiring packaging structure parameters of a to-be-tested power device and physical layout data of a test fixture, key parasitic parameter distribution is identified in combination with a time domain reflection measurement technology, a waveform distortion coefficient is calculated, and a spatio-temporal evolution model of electrostatic pulse propagation is constructed. Based on the model, a compensatory predistortion waveform is generated to counteract the parasitic effect of a transmission path, a device port response signal is collected in real time, an energy dissipation characteristic spectrum is extracted through wavelet packet decomposition, and quantitative evaluation of the electrostatic protection performance is achieved. According to the invention, the test precision and repeatability are improved, and the method is suitable for electrostatic protection tests of various novel power devices, especially high-frequency wide-band gap devices.

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The present invention provides an electro-conductive contact pin which can implement a narrow-pitch and an inspection device including same. Furthermore, the present invention provides an electro-conductive contact pin which uses a guide housing formed to have consistent thickness overall, including a portion corresponding to a lower part of an interference member and prevents damage due to interference with the interference member, and an inspection device including same.

The invention belongs to the technical field of semiconductor defect detection, and relates to a deep learning-based deep energy level defect identification method, system and device, and a medium. According to the method, transient curve data of an external capacitor is modulated to obtain a time sequence feature vector containing time, temperature and bias voltage information, then a multi-defect-induced weighted capacitor feature vector is obtained through calculation and modulation of a neural network model, and the time sequence feature vector and the multi-defect-induced weighted capacitor feature vector are trained after being spliced. Until the neural network model converges, the trained neural network model predicts a defect parameter vector, defect weight distribution and transient capacitance response at the (i + 1) th moment at the ith moment; according to the method, DLTS test data is modeled and analyzed in combination with a deep learning algorithm and a semiconductor deep energy level defect kinetic model, precise recognition and quantification of a complex defect system are achieved, the problem that defect recognition precision is insufficient in an existing DLTS test method is solved, and meanwhile the method is low in requirement for test equipment and high in applicability.

The invention provides a single-phase four-quadrant rectifier IGBT open-circuit fault diagnosis method under multiple working conditions, and relates to the technical field of IGBT fault diagnosis. Historical data of alternating current side voltage, alternating current side current and direct current side voltage of the single-phase four-quadrant rectifier are obtained, and a total harmonic distortion rate threshold value, a direct current side voltage threshold value and an alternating current side current first threshold value are obtained. And constructing and training an IGBT open-circuit fault positioning identification model. Detecting the total harmonic distortion rate of the alternating-current side current of the single-phase four-quadrant rectifier in real time, if the total harmonic distortion rate exceeds a threshold value, entering fault positioning, collecting and calculating the average value of the direct-current side voltage and the alternating-current side current in the period, and judging the fault of the single-phase four-quadrant rectifier under the specific working condition according to the comparison of the average value and the threshold value. Or using an IGBT open-circuit fault positioning identification model to diagnose the fault; if the threshold value is not exceeded, the next period is continuously monitored. According to the invention, the IGBT fault diagnosis efficiency and accuracy of the single-phase four-quadrant rectifier are improved.

The utility model provides a high-voltage pulse generating device and a test system. The high-voltage pulse generating device comprises a main control unit, a driving circuit, a pulse control circuit with a wide bandgap semiconductor power device, and an output circuit, the first end of the main control unit is coupled with the first end of the driving circuit, the second end of the driving circuit is coupled with the first end of the pulse control circuit, and the second end of the pulse control circuit is coupled with the output circuit; the main control unit is configured to generate two paths of first PWM (Pulse Width Modulation) signals with dead time control; the two paths of first PWM signals are sent to the driving circuit; and the driving circuit is configured to process the first PWM signal and then drive the pulse control circuit, so that the output circuit generates a high-voltage pulse signal. According to the utility model, the structure is simple, the cost can be greatly reduced, the output pulse speed can be flexibly set, and the CMTI test requirements of different isolated gate drivers can be met.

The invention relates to the technical field of power electronic equipment monitoring, in particular to a power semiconductor fault early-warning method and system based on data driving, and the method comprises the steps: receiving a fault early-warning instruction of a power semiconductor, determining a fault early-warning system based on the fault early-warning instruction, obtaining an electrical evaluation node based on the power semiconductor, and determining the fault early-warning system based on the electrical evaluation node. Based on a preset electrical monitoring time period, a preset electrical monitoring time interval and an electrical parameter node set obtained by the electrical parameter monitoring unit, a frequency evaluation proportion is obtained by using a low-frequency monitoring module and a high-frequency monitoring module; a primary monitoring state of the power semiconductor is confirmed based on an electrical parameter node set, a frequency evaluation proportion and an electrical evaluation node, a monitoring temperature set and a temperature change rate set are acquired by using a temperature monitoring module set, and a secondary monitoring state of the power semiconductor is confirmed based on a comprehensive monitoring temperature value and the temperature change rate set. And fault early warning of the power semiconductor is realized. According to the invention, the accuracy and reliability of power semiconductor fault early warning can be improved.

The invention discloses a low-temperature CMOS carrier MFP and microscopic parameter extraction method and system, which are corresponding schemes, in the scheme, a carrier MFP extraction model for eliminating a microscopic unknown quantity is constructed by utilizing a geometric scaling rule of quasi-ballistic transport and an existing effective mobility extraction technology, and an MFP extraction model for eliminating the microscopic unknown quantity is constructed by utilizing the geometric scaling rule of quasi-ballistic transport and the existing effective mobility extraction technology; the MFP extracted by the carrier MFP extraction model is ensured to be a pure experiment observation value on the basis that effective quality, Fermi velocity and scattering time do not need to be predicted based on the self-consistency of macroscopic current and voltage data along with the change of channel length; meanwhile, on the basis, the microcosmic parameters are decoupled, so that the decoupled microcosmic parameters are extracted one by one; compared with an existing scheme, the method can be directly applied to a standard wafer-level test board in the industry, MFP distribution of hundreds of devices can be rapidly counted, and a feasible engineering scheme is provided for low-temperature process monitoring.

The invention discloses an aging performance evaluation method and platform for a super junction MOS device, and relates to the technical field of performance evaluation, and the method comprises the steps: carrying out the test scene matching, and obtaining a target acceleration test scene group; calling a plurality of aging trend curves according to the target acceleration test scene group; locally calling a historical operation data set of the to-be-tested super junction MOS device; performing degradation feature extraction on the historical operation data set to obtain multiple groups of historical operation time sequence fragments; performing degradation increment correlation prediction on multiple groups of historical operation time sequence fragments, and outputting a device aging time sequence trend curve; comparing the aging time sequence trend curve of the device based on a preset failure threshold value, and outputting the remaining service life of the device; and interactively obtaining an equipment life design index of the target power electronic system, and quantitatively outputting an aging performance evaluation result in combination with the residual service life of the device. The technical problem that the aging performance evaluation accuracy is insufficient in the prior art is solved, and the technical effect of improving the aging performance evaluation precision is achieved.

The invention discloses a broadband oscillation characterization platform of a multi-chip power module and a near-field characteristic evaluation method, and belongs to the technical field of power electronics. The continuous operation condition of the power converter is decoupled into a series of discrete switching points, transient near-field radiation data of a to-be-tested power module under the discrete switching points are obtained through a double-pulse test, and near-magnetic field radiation signals are reconstructed; performing time-frequency analysis on the reconstructed near magnetic field radiation signal to generate a two-dimensional time-frequency matrix; and calculating a radiation energy entropy value based on the two-dimensional time-frequency matrix, fusing the radiation energy entropy value with the peak amplitude in the two-dimensional time-frequency matrix to generate a comprehensive EMI index for evaluating the broadband oscillation electromagnetic interference risk, and triggering EMI risk early warning when the comprehensive EMI index exceeds a threshold value. According to the method, the spectrum complexity is quantified through the radiation energy entropy, the multi-dimensional EMI risk assessment is carried out by fusing the peak amplitude of the time-frequency matrix, and the broadband oscillation in the multi-chip parallel power module can be accurately and efficiently represented.

The invention relates to the technical field of on-line health monitoring of wide bandgap semiconductor power devices, and discloses an on-line gate leakage current monitoring method and system for a GaN power device, and the method comprises the steps: extracting an average gate driving current which is within a complete switching period, an average value of instantaneous currents flowing into or out of the gate of the GaN power device; and on the basis of the average gate driving current, gate leakage current is obtained, so that online gate leakage current monitoring of the GaN power device can be carried out. The system corresponds to the method. According to the invention, the core problem that the traditional voltage detection method is insufficient in resolution and cannot realize early warning is fundamentally solved; meanwhile, a source electrode series sampling and non-intrusive signal conditioning circuit is adopted, a switch and a voltage stabilizing circuit are prevented from being introduced into a grid electrode driving loop, and therefore interference on parasitic parameters of the grid electrode loop is eliminated, and feasibility and reliability of application in a high-frequency and high-sensitivity GaN power device are ensured.

The invention provides a low-on-resistance shield gate trench MOSFET fault diagnosis method and system, and relates to the technical field of MOSFET fault diagnosis, and the method comprises the steps: applying preset transient electrical excitation to a contact interface of a probe and a wafer bonding pad and an MOSFET before the steady-state on resistance of the MOSFET is measured; according to the obtained electrical response information of the contact interface and the MOSFET under each transient electrical excitation effect, constructing a transient feature vector; analyzing the transient feature vector according to a preset discrimination rule for contact part abnormity and a discrimination rule for device structure defects to determine whether an abnormity source is the contact part abnormity or the device structure defects; according to the determined abnormal source, the measured on-resistance value is adjusted, and the problem that the test system misjudges that the on-resistance of the device is abnormally increased due to instantaneous fluctuation of the contact resistance caused by the change of the microscopic geometrical shape of the tip of the probe is solved.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The invention is suitable for the technical field of semiconductor testing, and provides a data acquisition method and device based on a DDIC chip, and testing equipment, and the data acquisition method comprises the steps: receiving a test pattern, controlling the DDIC chip to output a corresponding gray scale voltage signal, and achieving the comprehensive testing of the response capability of the chip in a full gray scale range; secondly, a target acquisition link composed of functional units including impedance conversion, single-ended to differential conversion, programmable gain amplification, filtering, analog-to-digital conversion and the like is utilized, so that the signal driving capability and the anti-interference capability are effectively improved, meanwhile, high-frequency noise and nonlinear distortion are reduced, and the basic quality of sampled data is guaranteed; on the basis, sampling optimization processing is carried out on the sampling data based on the FPGA unit, and the data stability is improved. According to the scheme, through high-precision transmission of the signal link, the data acquisition precision of the DDIC chip is improved, and then the technical requirements of high-precision DDIC chip testing are met.

The invention discloses a control system and method for a full-automatic probe platform, and relates to the technical field of semiconductor manufacturing and testing equipment, and the system comprises a contact event sensing and processing module which is connected with a signal output interface of a testing machine, applies a DC bias voltage to a selected testing channel, continuously monitors a loop current at a high sampling rate, and transmits the current to the testing machine; generating an electrical feedback signal, calculating the current change rate of the electrical feedback signal in real time, and calibrating a preset threshold value based on background noise for comparison and analysis; a contact starting event is judged by capturing current in real time, the control mode is switched immediately, the system can actively respond but not passively bear the change of the contact state, intelligent and self-adaptive control of the contact process is achieved, the control mode switching adopts a direct force control mode as a main control strategy of the contact process, and the control mode switching speed is high. The overall contact pressure is ensured not to exceed a safety threshold value, and overpressure damage and poor contact are effectively prevented.

The invention discloses a SiC MOSFET service life prediction method and device, equipment and a medium, and relates to the technical field of health detection of power electronic devices. The method comprises the following steps: acquiring an acquisition signal set acquired by a multi-channel sensor; the collected signals are preprocessed, smoothing and fusion estimation are carried out by adopting an extended Kalman filtering algorithm, and multi-dimensional degradation features including drain-source conduction voltage drift rate and thermal resistance change rate are extracted through feature engineering. And carrying out global optimization on the key hyper-parameters and the initial weight of the LSTM network by adopting an improved artificial fish swarm algorithm. The algorithm comprises an adaptive optimization strategy, a mixed local search operator and a boundary constraint processing mechanism. And training the optimized LSTM network by using the multi-dimensional degradation characteristics, establishing a mapping relationship between the multi-dimensional degradation characteristics and the device life, and obtaining a trained prediction model. And acquiring a to-be-predicted acquisition signal set to extract multi-dimensional degradation features and input the multi-dimensional degradation features into the prediction model to obtain a residual life prediction result.

A dynamic on-resistance and threshold voltage instability evaluation circuit for power devices and its operation method thereof are provided. The evaluation circuit includes a first switch element and a device under test which forms a half bridge circuit, an RL load, as well as a second switch element in parallel with a capacitor. The device under test is connected as a lower switch of the half bridge circuit. And the RL load enables repetitive hard switching operation of the device under test for dynamic on-resistance measurement. The second switch element in parallel with the capacitor enables threshold voltage measurement of the device under test. By adopting the circuit to characterize both instabilities of dynamic on-resistance and gate threshold voltage, the present invention is beneficial to achieving in shorter pulse width, faster measuring speed and inexpensive measuring equipment, and can thus be widely applied to group III-N based power devices.

The invention belongs to the technical field of semiconductor device performance testing, and particularly relates to a VCSEL epitaxial wafer resistivity distribution measuring method and system, and the method comprises the steps: constructing a three-dimensional discretization model representing an epitaxial wafer and an unknown parameter vector containing the vertical resistivity, the top transverse resistivity and the substrate leakage junction nonlinear resistance; a physical response function is defined, the vector is iterated through a discrete point fitting algorithm, so that the total residual error between the analog voltage difference output by the function and the actually measured voltage value under the cross-order-of-magnitude current is minimum, and the real vertical resistivity is extracted from the optimal parameter vector; and obtaining the vertical resistivity of each point on the two-dimensional test point grid so as to generate a distribution diagram and carry out anomaly detection. According to the invention, the problem of measurement distortion caused by the leakage defect of the substrate is solved, and the measurement accuracy of the vertical resistivity is improved.

The embodiment of the invention provides a gallium nitride totem-pole circuit and a control evaluation system of the gallium nitride totem-pole circuit, and the circuit comprises a gallium nitride power device which comprises an integrated semiconductor tube and an integrated drive circuit; the isolation chip is connected between the control module and an integrated driving circuit of the gallium nitride power device and is used for sending the pulse width modulation signal sent by the control module to the integrated driving circuit, and the isolation chip can ensure the electrical safety of weak current and strong current; the gallium nitride power device is used for controlling the on-off state of the integrated semiconductor tube through the integrated driving circuit according to the pulse width modulation signal sent by the isolation chip; under the condition that the integrated semiconductor tube is conducted, the voltage is output to the control module based on the bus voltage through the integrated semiconductor tube, and the driving circuit is integrated on the gallium nitride power device, so that the circuit design can be simplified, overcurrent protection and undervoltage protection are simultaneously carried out, and the safety of the gallium nitride totem pole circuit is improved.

The invention provides a method and a device for determining credibility of a wafer detection result, and belongs to the technical field of semiconductor manufacturing. The method comprises the steps that the target grade of a wafer to be detected is determined, the target grade is selected from a plurality of preset product grades, and different product grades correspond to different preset quality thresholds; multiple times of virtual measurement are carried out on the wafer to be measured, a predicted value set is obtained, and the predicted value set comprises predicted values corresponding to each time of virtual measurement; and determining a virtual measurement result and the credibility of the virtual measurement result based on the predicted value set and a preset quality threshold value corresponding to the target grade. The credibility is matched with the target grade, so that differential evaluation can be carried out according to different product grades, the detection requirements of wafers of different product grades are met, and the accuracy of virtual measurement result evaluation is improved.

The invention relates to the technical field of semiconductor material photoelectric detection, and discloses a whole-course calibration method of a microwave photoconductive attenuation tester, which comprises the following steps: steady-state optical calibration: establishing reference mapping from light intensity to absolute carrier concentration; performing sweep frequency perturbation measurement at each concentration working point to obtain multiple groups of complex response data; separating an instrument transfer function from sample differential response sensitivity by adopting a system identification algorithm; an integral differential sensitivity reconstruction curve is converted into an absolute calibration model by using an anchor point; starting closed-loop feedback control to lock a specific phase, and verifying the model; and outputting an absolute calibration model and an instrument transfer function as a static reference and a dynamic operator. According to the invention, the absolute concentration anchor point is established through steady-state optical calibration, integral reconstruction is carried out on the differential response sensitivity decoupled by dynamic frequency sweep measurement, and finally, the anchor point is utilized to determine the integral constant, so that the accuracy and reliability of carrier concentration quantitative analysis are improved.

The invention provides an IGBT (Insulated Gate Bipolar Translator) turn-off time measuring method, system, equipment and medium, and belongs to the field of power semiconductor device testing technology and state monitoring, and the method comprises the following steps: firstly, selecting 20% Vdc and 80% Vdc as turn-off initial measuring points, secondly, carrying out first error correction by adopting a linear estimation method, and finally, carrying out second error correction by adopting a linear estimation method; performing linear fitting on the voltage difference Vce data through a least square method to obtain initial turn-off time; and finally, aiming at systematic deviation caused by inherent concavity and convexity characteristics of the voltage curve, performing secondary error correction by adopting a convex hull algorithm, acquiring a lower envelope line of the ic-tOFF relation curve through an Andriw algorithm, and identifying and eliminating the problem of Overestimation of the turn-off time based on a convex hull accurate point set. According to the invention, accurate measurement of the turn-off time of the IGBT under the condition of low sampling rate is realized, the hardware cost is significantly reduced, and a reliable technical basis is provided for IGBT state monitoring and life prediction.

The invention provides a method for plasma bombardment energy distribution detection and life prediction of a silicon carbide part, and belongs to the technical field of semiconductor processing based on deep learning. The method comprises the following steps: firstly, arranging a magnetic probe array to obtain local electromagnetic parameters, and obtaining plasma luminescence characteristics by using optical imaging and spectrum acquisition equipment; preprocessing the acquired data to obtain multi-source fusion features; designing an energy distribution reconstruction framework based on a generative adversarial network, wherein a generator is used for deducing a three-dimensional energy distribution field of plasma; and inputting the three-dimensional energy distribution field time sequence characteristics into a bombardment dynamic characteristic modeling time sequence depth network, establishing a nonlinear mapping relation between energy distribution and material aging, further obtaining life prediction parameters, and finally obtaining the remaining service life of the silicon carbide part. According to the method, a complex degradation mechanism can be reflected more accurately, and the precision and robustness of life prediction are remarkably improved.

The invention relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) surge failure real-time discrimination method and system, and the method comprises the steps: 1, collecting SiC MOSFET surge waveform data, and carrying out the multi-scale physical feature extraction, and obtaining a physical frequency band energy feature; 2, performing feature alignment on the physical frequency band energy features to form a standardized feature vector; and 3, constructing a surge failure prediction model, performing temperature compensation on an output result of the surge failure prediction model, and judging a failure state. Current and voltage waveforms in a surge event are captured through a high-speed data acquisition system, key physical frequency band energy features are extracted by adopting an adaptive wavelet packet decomposition technology, a pulse width normalization coding model is constructed to realize feature alignment, and a physical guide degradation path auto-encoder model is designed to perform failure prediction. The method innovatively solves the problem of failure discrimination of surges with different pulse widths, and has the characteristics of high precision and strong real-time performance.

The invention discloses a switching tube fault analysis and construction system and method based on an SVM algorithm, and belongs to the technical field of switching tube fault diagnosis. The system comprises a data acquisition module, a database, an intelligent analysis module, an intelligent adjustment module and a fault judgment module. The data acquisition module is used for acquiring control data and electrical parameter data in the operation process of a plurality of switch tubes in the offshore wind generating set; the database is used for storing historical control data and historical electrical parameter data; the intelligent analysis module is used for training an SVM model and analyzing the influence on the accuracy of the SVM model under the condition of different switching frequencies and losses of a switching tube; the intelligent adjusting module is used for adaptively adjusting the electrical parameter data acquisition frequency at different switch tube nodes; and the fault judgment module is used for inputting the collected electrical parameter data into the trained SVM model to diagnose the fault of the switching tube.

The embodiment of the invention provides a testing device and an interface resistivity detection method, and relates to the field of semiconductors. The testing device is used for detecting a to-be-tested sample. The testing device comprises a sample table, and an image detection device, a first detection device and a second detection device which are arranged on the sample table, the testing device further comprises a current source, a voltage detection device and a processor. The current source and the voltage detection device are connected with the first detection device and the second detection device. Wherein the image detection device is used for acquiring an image of a to-be-detected sample placed on the sample table; the processor is used for controlling the first detection device to be in contact with a first electrode in the to-be-detected sample and controlling the second detection device to be in contact with a second electrode in the to-be-detected sample according to the image, displayed by the image detection device, of the to-be-detected sample; the current source is used for providing constant current for the to-be-tested sample; the voltage detection device is used for detecting a voltage value between the first electrode and the second electrode of the to-be-detected sample.

The invention relates to an IGBT module junction temperature estimation method and system, and the method comprises the following steps: obtaining a performance curve set of an IGBT module under different working conditions, and carrying out the fitting optimization, and obtaining an optimal performance curve set; constructing a transient thermal resistance curve model according to a transient thermal resistance principle, and constructing a second-order Foster thermal network model based on the transient thermal resistance curve model; performing Laplace transformation and discretization processing based on a backward difference method on the second-order Foster thermal network model to obtain a junction temperature estimation model; collecting a phase current instantaneous value, and calculating the total power loss of the IGBT module in real time in combination with the optimal performance curve set; and finally, the junction temperature of the IGBT module is obtained in real time by using the total power loss of the IGBT module obtained through real-time calculation and the junction temperature estimation model, and junction temperature estimation is completed. According to the method, the effect of improving the power loss precision of the IGBT module is achieved by optimizing the performance curve, and then the junction temperature estimation precision is improved.

The invention relates to the technical field of electronic circuits, in particular to a field effect transistor dynamic threshold voltage measuring method and system. The method comprises the following steps: generating a high-speed pulse signal with preset rise time through a pulse signal generator; applying the high-speed pulse signal to the grid electrode of the field-effect tube to be tested, and collecting the voltage waveform of the grid electrode of the field-effect tube through an oscilloscope, and recording the voltage waveform as a grid electrode voltage waveform; the current probe monitors the current response of the drain electrode of the field effect transistor in real time, the current response is recorded as drain electrode current response, and the sampling rate of the drain electrode current response is synchronous with the sampling rate of the grid voltage waveform. According to the invention, the channel establishment delay is quantified in situ on the electrical characteristic, so that the threshold voltage is redefined by the potential at the completion moment of the channel formation, and the concealment of the transient characteristic caused by direct current slow scanning is eliminated.

The invention belongs to the technical field of power systems, and particularly discloses a fault prediction method for a thyristor and a BOD (Biochemical Oxygen Demand) in an SVC (Static Var Compensator), which comprises the following steps: an optimized data acquisition stage: continuously acquiring and storing data by utilizing a long short-term memory network, and dividing fault types into thyristor open circuit, thyristor short circuit, trigger angle deviation and normal state; establishing a prediction model: analyzing historical operation data by using a time sequence method, generating the prediction model by using a convolutional neural network and a long-short-term memory method, predicting the operation trend of the equipment in real time, and generating an early warning notice; a BOD protection circuit is optimized, wherein a BOD overvoltage detection branch and low-pass filtering branches R1 and C1 are established on a thyristor main circuit.