2138 results about "DC bias" patented technology

A waveform adaptive transmitter that conditions and/or modulates the phase, frequency, bandwidth, amplitude and/or attenuation of ultra-wideband (UWB) pulses. The transmitter confines or band-limits UWB signals within spectral limits for use in communication, positioning, and/or radar applications. One embodiment comprises a low-level UWB source (e.g., an impulse generator or time-gated oscillator (fixed or voltage-controlled)), a waveform adapter (e.g., digital or analog filter, pulse shaper, and/or voltage variable attenuator), a power amplifier, and an antenna to radiate a band-limited and/or modulated UWB or wideband signals. In a special case where the oscillator has zero frequency and outputs a DC bias, a low-level impulse generator impulse-excites a bandpass filter to produce an UWB signal having an adjustable center frequency and desired bandwidth based on a characteristic of the filter. In another embodiment, a low-level impulse signal is approximated by a time-gated continuous-wave oscillator to produce an extremely wide bandwidth pulse with deterministic center frequency and bandwidth characteristics. The UWB signal may be modulated to carry multi-megabit per second digital data, or may be used in object detection or for ranging applications. Activation of the power amplifier may be time-gated in cadence with the UWB source thereby to reduce inter-pulse power consumption. The UWB transmitter is capable of extremely high pulse repetition frequencies (PRFs) and data rates in the hundreds of megabits per second or more, frequency agility on a pulse-to-pulse basis allowing frequency hopping if desired, and extensibility from below HF to millimeter wave frequencies.

A coupling circuit arrangement for data communication over a power line comprises a modulator/demodulator circuit for modulating data signals for transmission over the power line, and for demodulating signals which have been transmitted over the power line into data signals, a power supply circuit, and isolation means for providing galvanic isolation from the power line. The isolation means comprises light emitting elements and light detecting elements, which are arranged between the modulator/demodulator circuit and the power line. The isolation means may also be used to transmit a digital control signal which indicates the status of the power supply circuit or an over-temperature condition, or which is a transmit enable signal. The digital control signal may be encoded in the analog data signal by a digital shift in the DC bias level or by a complete removal of the DC biasing signal.

On a transparent substrate, by use of, for instance, vapor deposition, an Al film is formed. Subsequently, with a DC-bias applied on a surface of the Al film, a first zinc oxide thin film is formed by use of a sputtering method. On a surface of the first zinc oxide thin film, according to an atmospheric MO-CVD method, a second zinc oxide thin film is formed. When the second zinc oxide thin film deposited by use of an MO-CVD method is formed on the first zinc oxide thin film having a-axis orientation, the second zinc oxide thin film becomes to have the a-axis orientation. Since the Al thin film, owing to heat during the deposition by use of the MO-CVD method, is absorbed in the first zinc oxide thin film, the transparency is improved. As a result, a sample having a ZnO/ZnO/Al/glass structure becomes high in the transparency as a whole.

A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

A conventional plasma applied ALD apparatus has a problem in that physical shock is directly imposed on a substrate and a thin film thereby damaging the thin film. Further, many reports have said that since an apparatus for controlling plasma energy is not arranged well, the thin film is not formed uniformly due to plasma nonuniformity. Therefore, there is provided a remote plasma atomic layer deposition apparatus using a DC bias comprising: a reaction chamber having an inner space; a substrate supporting body on which a substrate on which a thin film is to be formed is loaded arranged at one side of the inner space of the reaction chamber; a remote plasma generating unit arranged outside of the reaction chamber to supply a remote plasma into the inner space of the reaction chamber; a DC bias unit controlling energy of the remote plasma; and a source gas supply unit supplying a source gas for forming the thin film into the reaction chamber.

Provided is an apparatus for generating remote plasma, which can improve thin-film quality by preventing an arc at a bias electrode. The apparatus includes a radio frequency (RF) electrode installed inside an upper portion of a chamber, a bias electrode installed apart from the RF electrode, and including a plurality of through holes through which plasma passes, wherein a bias power is supplied to the bias electrode, a plasma generating unit formed between the RF electrode and the bias electrode, wherein a plasma gas is supplied to the plasma generating unit, and a ground electrode installed under and spaced apart from the bias electrode, and including plasma through holes corresponding to the through holes of the bias electrode, wherein a pulsed DC bias of a second voltage level, which has a first voltage level periodically, is applied to the bias electrode.

The invention discloses a configurable multi-mode multi-band satellite navigation receiving method and a radio frequency front end module constructed by the method. The front end module can receive signals of satellite navigation and positioning systems such as a global positioning system (GPS), the Big Dipper, a Galileo positioning system and a global navigation satellite system (Glonass), and comprises a configurable low-noise amplifier (LNA) with a buffer and an active balun, a folding passive mixer with a configurable frequency synthesizer, a configurable multi-mode filter, an automatic gain control (AGC) amplifier, a direct-current bias circuit, and a multi-mode multi-band program controlled and coded on-off control word from a receiving system. The radio frequency front end module can meet the requirement of multi-band multi-mode work through the control word programmed by the receiving system, has a simple and reliable structure, does not need complicated time division multiplexing control system and off-chip module, has low cost and high flexibility, and improves the noise performance of the radio frequency front end of the whole receiver and multi-mode multi-band signal processing capacity; and a one-channel signal is input into the module, and the module outputs a two-channel differential signal. The receiver can be used for receiving and processing multi-mode satellite navigation signals asynchronously, and receiving and processing satellite navigation signals with the required mode in different time intervals according to the requirement.

A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

A DC-DC converter of synchronous rectification type is provided which comprises: a current detector (51) for discerning electric current (I_Q1, I_Q2) flowing through a primary side circuit; first and second DC biasing power supplies (53, 54) for producing a bias voltage (V_BS1, V_BS2) higher than voltage corresponding to excitation current through transformer (4); and first and second comparators (55, 57) for activating first and second rectifying MOS-FET (7, 8) when current detector (51) produces the detection voltage (V_DT) over bias voltage (V_BS1, V_BS2) of first and second DC biasing power supplies (53, 54). As each of first and second rectifying MOS-FETs (7, 8) in secondary side circuit is driven synchronously with electric current (I_Q1, I_Q2) flowing through the primary side circuit except excitation current component through transformer (4), the converter can minimize switching loss in each rectifying MOS-FET (7, 8) in secondary side circuit to improve conversion efficiency.

An integrated photodetector means for controlling the output of a light source, where the control means is a photodetector formed on a silicon-on-insulator substrate. The integrated photodetector senses the optical power from the light source and provides an electrical feedback signal which can be used to adjust the DC bias levels of the light source control driver circuit. The approach readily lends itself to large arrays of light sources bonded to silicon-on-sapphire driver circuits and is especially suitable for controlling light sources such as VCSELs in arrays such as are found in communications systems.

Substantial improvements in frequency reuse in microwave communications systems is achieved by canceling co-channel interference and transmitter leakage. Interferometric beam-narrowing reduces beamwidth without reducing preak magnitude of the beam pattern. Frequency-dependent beam-shaping compensates for frequency-dependent distortions of the beam pattern thereby improving bandwidth. A spatial demultiplexing technique utilizes spatial gain distributions of received signals to separate signals, even from co-located transmit sources, and uses microwave lensing to enhance received spatial gain distributions. Predetermined cross-polarization interference is used to separate differently polarized receive signals. A reference branch provides a cancellation signal to a receiver to cancel transmitter leakage signals. An error signal controls an impedance-compensation circuit that is responsive to changes in antenna impedance but not to receive signals. A dc bias magnetic field applied to a magnetic permeable material adjusts non-linear distortion in a cancellation circuit for canceling distortion in a transmitter leakage signal. Discreet impedance elements approximate a circuit having distributed impedance.

In low-voltage circuits, there is often insufficient voltage to use a current source to bias a transconductance amplifier stage. This is particularly true in mixers where a switching circuit must be stacked on top of the transconductance input stage. One way around this problem is to get "double-duty" out of the input differential pair, using it both for gain stage and for DC bias. This is done by AC coupling in a high-frequency input signal, while using a low-frequency, DC-coupled circuit to establish the proper bias level. One common technique is to use a simple current mirror scheme to establish the DC level. Proper biasing using this technique requires good matching of resistance. In some implementations of transconductance amplifiers, particularly those that use inductors as degeneration elements, series resistance of the inductor and interconnect resistance can cause significant errors in the bias current. This invention addresses that problem by using an operational amplifier with a current-sensing resistor and a low-frequency feedback loop to compensate automatically for any resistance errors. The operational amplifier drives the feedback voltage (generated in accordance with the sensed voltage at the current-sensing resistor and applied to one input of the operational amplifier) towards a reference voltage that is applied to the other input of the operational amplifier to bias the transistor(s) in the transconductance amplifier for desired operating conditions.

A method of reducing visible flicker in a transflective display device, having a plurality of pixels, each pixel comprising a transmissive sub-pixel and a reflective sub-pixel, is disclosed. The method comprises the steps of: driving the pixels with an alternating voltage; determining a first desired compensation voltage for the transmissive sub-pixels and a second desired compensation voltage for the reflective sub-pixels; deriving a common compensation voltage from said first desired compensation voltage and said second desired compensation voltage; and applying said common compensation voltage to both the transmissive and the reflective sub-pixels. Thus, the flicker resulting from a DC bias of the driving voltage is substantially reduced. In a preferred embodiment, the method further comprises the steps of: determining a lowest available frame frequency setting for which any remaining flicker is invisible; and setting a frame frequency at which the display is driven to said lowest available frame frequency. According to another embodiment, a backlight is manually controlled and the common compensation voltage is derived as a function of a mode of operation of the backlight. A transflective display device implementing the above methods is also disclosed.

A voltage-controlled oscillator comprising a resonant circuit and MOS transistors which constitute a negative resistance circuit of a differential structure. The resonant circuit consists of an inductance element and a MOS variable capacitance element connected in parallel therewith. The MOS variable capacitance element is divided into plural pairs connected in parallel with each other. A voltage division circuit generates staircase different-step DC bias voltages to be applied respectively to the gates of the plural divided MOS transistors. The divided MOS variable capacitance elements have a common terminal to which a common control voltage is applied. The resonant circuit is capable of reducing a load on the control voltage generator and improving the characteristics of the voltage-controlled oscillator.

An Inverted-F antenna (IFA) includes a tunable parallel LC resonator physically inserted between two antenna bodies of the IFA structure. The LC resonator is comprised of a tunable capacitor C1 connected in parallel with a combination of a DC blocking capacitor C2 and an inductor L1 connected in series to each other. A DC bias voltage is applied to the tunable capacitor C1 through a DC bias resistor R1, in order to adjust the capacitance of the tunable capacitor C1. The IFA exhibits dual band characteristics, and its resonant frequencies and bandwidths may be turned by adjusting the capacitance of the tunable capacitor C1. The tunable capacitor C1 may be a BST capacitor.

Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.