1293results about "Amplifier modifications to reduce detrimental impedence" patented technology

An apparatus for establishing and applying a voltage to precharge current-driven elements in a matrix. During ordinary scan cycles, a conduction voltage is sensed while the elements conduct a selected current. One or more such sensed conduction voltages are combined to provide a basis for a precharge voltage. Conduction and transient errors are determined, and are compensated for by offsetting the final precharge voltage from the conduction voltage basis. The final precharge voltage is provided to one or more columns during a precharge period of the scan cycle.

Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

A digital switching power amplifier with Multivariable Enhanced Cascade Controlled (MECC) includes a modulator, a switching power stage and a low pass filter. In the first preferred embodiment an enhanced cascade control structure local to the switching power stage is added, characterised by having a single local feedback path A (7) with a lowpass characteristic and local forward blocks B1 or B (3, 4). The leads to a much improved system with a very low sensitivity to errors in the switching power stage. In the second preferred embodiment of the invention the control structure is extended with a global structure composed of a single feed-back path C (8) and forward paths blocks D1 or D (1, 2). This provides further improvements and a very low sensitivity to load variations and filter errors. Both MECC embodiments are characterised by being simple in implementation, stable and extendible by adding / removing simple local (3) or global (1) forward path blocks. A third embodiment of the invention is a controlled self-oscillating pulse modulator, characterised by first a non-hysteresis comparator as modulator and second by a higher order oscillating loop realized in both forward path B1 and feedback path A to determine stable self-oscillating conditions. An implemented 250W example MECC digital power amplifier has proven superior performance in terms of audio performance (0.005% distortion, 115 dB dynamic range) and efficiency (92%).

A method and apparatus to control output power of a digital amplifier capable of automatically determining an impedance of an earphone or headphone connected to a portable audio device and outputting a power that is optimized according to the impedance. The apparatus is usable with a digital amplification device and includes a signal processing unit to convert a pulse signal into a direct current (DC) voltage by power-amplifying the pulse signal, an impedance measuring unit to connect a resistance device between the signal processing unit and a speaker unit and to detect a voltage value applied to the resistance device and the speaker unit, and a micom unit to generate a pulse signal having a predetermined duty cycle in the signal processing unit if the speaker unit is connected to the device, to determine an impedance of the speaker unit based on the voltage value detected by the impedance measuring unit, to control a power amplification by providing a voltage level control signal to the signal processing unit according to the determined impedance, and to control an audio level in an audio reproduction mode accordingly.

A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor.

According to an exemplary embodiment, a multimode power amplifier configured to receive an RF input signal and provide an RF output signal in linear and saturated operating modes includes an output stage configured to receive a fixed supply voltage and to provide the RF output signal. The multimode power amplifier further includes at least one driver stage coupled to the output stage, where the at least one driver stage is configured to receive the RF input signal and an adjustable supply voltage. The adjustable supply voltage controls an RF output power of the RF output signal when the multimode power amplifier is in the saturated operating mode. The at least one driver and the output stage are each biased by a low impedance voltage in the linear and saturated operating modes. The adjustable supply voltage can be controlled by a fixed control voltage in the linear operating mode.

A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

A low noise amplifier (LNA) operates over multiple frequency bands while occupying less silicon area than known LNA implementations. The LNA includes output matching that can be tuned by an adjustable inductor together with a tunable capacitor bank.

An amplifier comprises a source degeneration inductance and at least two field effect transistors coupled in parallel and having mutually different gate biasing. Source connections of the field effect transistors are coupled along different positions of the source degeneration inductance.

A method and apparatus is described for controlling conduction between two nodes of an integrated circuit via a stack of FETs of common polarity, coupled in series. In an RF Power Amplifier (PA) having appropriate output filtering, or in a quad mixer, stacks of two or more FETs may be used to permit the use of increased voltages between the two nodes. Power control for such RF PAs may be effected by varying a bias voltage to one or more FETs of the stack. Stacks of three or more FETs may be employed to control conduction between any two nodes of an integrated circuit.

Circuits and methods are provided for providing high speed operational amplifiers and, in particular, operational amplifiers having frequency compensation circuits that provide improved slew rates with low power dissipation when configured with feedback. Frequency compensation schemes are provided to enable dynamic configuration of frequency compensation circuits implementing miller compensation whereby nodal connections of compensation capacitors are changed during driver setup and driving periods such that compensation capacitors are connected to source voltages to rapidly charge / discharge compensation capacitors using supply source currents during setup period, while providing frequency compensation during the setup and driving periods to maintain circuit stability and prevent oscillation of an output voltage due to the feedback.

A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A method and system for providing a mixed-mode (current- and voltage-source) audio amplifier is disclosed. The mixed-mode amplifier includes a voltage sensing feedback path including a first network comprising at least one circuit; and a current sensing feedback path including a second network comprising at least one circuit. According to the method and system disclosed herein, the first and second networks vary an output impedance or transconductance of the amplifier as a function of frequency of the input voltage signal, such that at a first frequency range, the amplifier operates substantially as a current amplifier, and at a second frequency range, the amplifier operates substantially as a voltage amplifier, thereby inheriting distortion reduction of the current amplifier and stability of the voltage amplifier.

A mixer includes a reference current source, a programmable gain RF transconductance section or an RF transconductance section, switching quad native transistors or switching quad transistors, and a folded-cascoded common mode output section or an output section. When the mixer included the programmable gain RF transconductance section, the gain of the mixer is adjustable. When the mixer includes the switching quad native transistors, flicker noise of the mixer is reduced. When the mixer includes the folded-cascoded common mode output section, the mixer operates reliably from low supply voltages.

A three stage amplifier is disclosed provided with a novel frequency compensation technique. Only a single feedback loop with a single compensation capacitance is provided. Instead of a conventional nested compensation technique, damping factor control is provided by means of a fourth gain stage in order to stabilize the amplifier. The resulting amplifier is particularly useful to drive large capacitive loads for low-voltage low-power applications.

A balanced power amplifier that includes two or more power amplifiers with equal but phase-shifted signal paths. Balanced power amplifiers need to achieve phase delay and also need to perform power combining. A power amplifier includes at least one quadrature hybrid (also referred to as a branch-line coupler). The quadrature hybrid is utilized for multiple functions, such as power dividing, power combining, impedance matching or a combination thereof. This implementation with the quadrature hybrid reduces the amount of area needed to implement the balanced power amplifier.

A radio frequency device has an input transistor from which a capacitance is seen, and a fast charging circuit for charging the capacitance. The input transistor receives a radio frequency signal. The capacitance is quickly charged when the device is switched from off to on and / or from low gain to high gain, thereby reducing the switching-on time of the device.

A power amplifier circuit comprising a transistor for receiving a signal to be amplified at an input and for outputting an amplified signal at an output; a modulated power supply connected to the transistor output; and a resistive element connected at the transistor output such that a low impedance is maintained at the transistor output across a range of operational frequencies.

A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

A variable capacitor is formed by a multilayer circuit board having a plurality of dielectric layers; a first conductive plate, provided within the multilayer circuit board, for serving as one electrode of the variable capacitor; a second conductive plate, provided within the multilayer circuit board, for serving as the other electrode of the variable capacitor; a plurality of third conductive plates provided between the first conductive plate and the second conductive plate; and a plurality of switching means provided for grounding the third conductive plates selectively.

A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is provided with positive feedback to substantially increase the gain of the first stage amplifier. In the described examples, the positive feedback is provided either by connecting a capacitor from the output to the input of the first stage amplifier or by connecting a shunt transistor in parallel with an input transistor and driving the transistor from the output of the first stage amplifier. The substantially increased gain resulting from the positive feedback allows the gain of the switched capacitor amplifier to be set by the ratio of the capacitance of an input capacitor to the capacitance of a feedback capacitor. The amplifier also includes switching transistors for periodically discharging the input capacitor and the feedback capacitor.

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Preferred fabrication techniques include stacking multiple FETs to form switching devices. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.