9results about "Amplitude modulation details" patented technology

Provided is a wireless power transmitting system and device, the wireless power transmitting device including: a signal generator configured to generate an initial signal; a controller configured to output an amplitude control signal and a phase control signal; a phase modulator configured to generate a phase-modulated signal by modulating a phase of the initial signal based on the phase control signal; a power amplifier configured to generate a power signal by amplifying the phase-modulated signal; a voltage converter configured to control a magnitude of a power voltage of the power amplifier based on the amplitude control signal; and an antenna configured to externally output the power signal.

This invention discloses an amplitude-phase adjustable carrier generation device and method, belonging to the field of precision measurement and signal synthesis. The phase accumulator of this invention incorporates a phase adjuster. The phase adjuster counts the system clock, and when a set count value C is reached, it outputs a phase adjustment value S. At this time, the value of the phase register is simultaneously added to the frequency control word FCW and the phase adjustment value S. Subsequently, the phase register overflows, is cleared to zero, and accumulation restarts. The phase adjuster supplements the decimal part discarded during the rounding of the frequency control word FCW, which helps improve the frequency stability of the carrier. The CORDIC calculator of this invention employs a parallel interpolation structure, which can use n CORDIC cores to calculate the sine values ​​of n consecutive phases in parallel. The interval between two adjacent phases is the frequency control word FCW. The interpolation unit arranges the n data streams and outputs them serially. The parallel interpolation structure improves the speed and accuracy of CORDIC calculation through parallel computation, which can greatly reduce phase truncation errors and help reduce carrier spurious emissions.

The utility model discloses a logic circuit for increasing the common-mode transient immunity of an OOK modulation and demodulation digital isolator, the logic circuit comprises a transmitting terminal TX and a receiving terminal RX, the receiving terminal RX comprises a cross-coupled common-gate pre-drive amplifier composed of a plurality of transistors, the common-gate pre-drive amplifier amplifies signals sent by the transmitting terminal TX, and the common-gate pre-drive amplifier is used for amplifying the signals sent by the receiving terminal TX; the envelope comparator is used for comparing the output voltage of the common-gate pre-drive amplifier and outputting a corresponding high-level signal or a low-level signal; the forward common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected with the common-gate pre-drive amplifier, and the transistor MN5 is switched on or switched off by an output voltage signal of the transmitting end TX; the negative common-mode voltage change rate detection circuit is a transistor MP5, the transistor MP5 is connected with the common-gate pre-drive amplifier, and the transistor MP5 is switched on or switched off by an output voltage signal of the common-gate pre-drive amplifier; and the logic circuit is used for comparing an output signal of the output end of the envelope comparator, an output signal of the positive common-mode voltage change rate detection circuit and an output signal of the negative common-mode voltage change rate detection circuit, and outputting a logic processing result.

The application provides an SST driving structure of a multi-pulse amplitude modulation signal and a pre-process system thereof. n -1 standard unit, wherein all the standard units are divided into n groups, the number of standard units in the kth group is 2 k‑1 ; wherein n and k are integers, n>=2, and k<=n; and the first group is defined as an LSB group, and the nth group is defined as an MSB group; wherein M standard units in the MSB group are divided for resistance correction; wherein M is an integer, and M<=2 n‑1 The application can effectively solve the problem that the existing scheme is easy to affect the linearity of the circuit when correcting the resistance and reduce the output SST swing.

The utility model discloses a logic circuit for increasing common-mode transient immunity of a digital isolator for edge modulation and demodulation. The logic circuit comprises a transmitting end TX and a receiving end RX, the receiving end RX comprises a latch; a fully differential amplifier; an envelope comparator; the forward common-mode voltage change rate detection circuit is a transistor MP1, the transistor MP1 is connected with the output end of the latch, and the transistor MP1 is switched on or switched off by an output voltage signal of the latch; the negative common-mode voltage change rate detection circuit is a transistor MN5, the transistor MN5 is connected with the output end of the latch, and the transistor MN5 is switched on or switched off by an output voltage signal of the latch; and the logic circuit is used for comparing an output signal of the output end of the envelope comparator, an output signal of the positive common-mode voltage change rate detection circuit and an output signal of the negative common-mode voltage change rate detection circuit, and outputting a logic processing result.

To provide a driving circuit producing a DSB-SC modulation signal.SOLUTION: A driving circuit comprises a first capacitor. During a sampling operation, the first capacitor is coupled between first and second input terminals. During a transferring operation, an end of the first capacitor receives a voltage, and another end of the first capacitor is coupled to a load. The driving circuit produces a first driving signal to drive the load, the first driving signal comprises a plurality of first portions with a first polarity, and a plurality of second portions with a second polarity opposite to the first polarity. The plurality of first portions and the plurality of second portions form a generalized DSB-SC modulated component of the first driving signal, which is modulated according to an input signal between the first input terminal and the second input terminal.SELECTED DRAWING: Figure 3

The application provides a kind of electric quantity sensor circuit, comprising: hall element circuit;First signal modulation circuit is connected with hall element circuit, to amplify the output signal of hall element circuit with modulation;Current amplification circuit is connected with current amplification circuit, to amplify the output current of first signal modulation circuit with processing;Wherein, first signal modulation circuit includes resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, resistance R21, capacitor C5, diode D5, operational amplifier chip U5 and triode Q4;Current amplification circuit includes resistance R22, resistance R23, resistance R24, resistance R25, capacitor C6, capacitor C7, capacitor C8, diode D6 and triode Q5.The signal processed by the above-mentioned mode can be stably output, and the reliability and detection accuracy of output signal can be improved.

The application provides an on-chip radio frequency acoustic wave amplitude modulator and a communication device, and belongs to the field of signal processing.The on-chip radio frequency acoustic wave amplitude modulator comprises a signal input end, a first phase shifter, a second phase shifter and a phased transducer array.The first phase shifter and the second phase shifter are connected with the signal output end.The phased transducer array comprises a first phased array and a second phased array.The first phased array is connected with the first phase shifter, and the first phased array comprises a plurality of first array elements.The second phased array is connected with the second phase shifter, and the second phased array comprises a plurality of second array elements.The first array elements and the second array elements are arranged alternately, and the shortest distance between adjacent first array elements and second array elements is (N+1 / 4)λ.The modulator device can keep the miniaturization of the device and significantly improve the modulation efficiency of the wide-band radio frequency signal.

The present disclosure relates to a modulation / demodulation method and circuit configuration for a PEAPSK modulation / demodulation communication system. In a configuration of a PEAPSK modulation / demodulation circuit, there may be provided a low-power wideband pre-emphasis amplitude phase shift keying modulation / demodulation communication system comprising: a pre-emphasis amplitude phase shift keying modulation transmission unit that uses, as a carrier of a BPSK modulator, a pre-emphasis baseband signal obtained by amplitude-modulating, onto a baseband carrier, a pre-emphasis synthesized signal obtained by synthesizing a multi-level pre-emphasis signal of a binary data (aDATA) signal to be transmitted at high speed and a signal obtained by pre-emphasizing an edge signal of a binary data (pDATA) signal, wherein a PEAPSK baseband signal is generated when the phase of the carrier is changed by the pDATA signal, and a PEAPSK RF signal, obtained by converting the PEAPSK baseband signal to a transmission frequency through an RF mixer and a transmission-side BPF, is transmitted; a transmission unit through which a PEAPSK RF transmission signal may be transmitted with distortion through a wired or wireless path; and an asynchronous amplitude phase shift keying demodulation and data clock recovery unit that separates, through high-frequency loss of the transmission unit and a reception-side BPF, a bandwidth-limited and distorted PEAPSK baseband signal into sideband analog signals and demodulates a pDATA signal by using an asynchronous BPSK demodulator that phase-aligns and demodulates the sideband analog signals, demodulates an aDATA signal from the pre-emphasis baseband signal on the basis of a lower sideband digital signal generated by a comparator and a pCLOCK signal recovered by using the pDATA signal, and recovers an aCLOCK signal.