211 results about "Adder" patented technology

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

The application discloses a signal equalization device, system and method, and belongs to the electronic information technical field. The signal equalization device comprises an adder and a controller. The first input end of the adder is connected with a signal source. The output end of the adder is connected with the input end of the controller. The output end of the controller is connected with the second input end of the adder. The adder receives a target signal generated by the signal source and a control signal output by the controller. The target current is determined according to the control signal. The target signal is equalized according to the target current, and an equalized signal is obtained. The control signal is determined by the controller according to characteristic information. The characteristic information indicates the signal rate of a first signal output by the adder to the controller. The first signal is obtained by equalizing a previous signal of the target signal by the adder according to an initial current. The application determines the current according to the signal rate, so that the adder can generate stable gain to the signal in the equalization process according to the current.

The invention belongs to the technical field of in-memory computing, and discloses an in-memory computing architecture supporting native transpose, comprising: a plurality of in-memory computing sub-arrays; the hierarchical shared addition tree comprises a plurality of adders of different hierarchies and is used for performing hierarchical accumulation on calculation results of the sub-arrays; the reconfigurable routing module is arranged at the input end of each level of summator and is used for selecting a data transmission path according to the working mode; the working mode comprises transverse accumulation and longitudinal accumulation. According to the technical scheme, the huge area cost caused by configuration of double adder trees for achieving transposition is avoided, particularly, the situation that the number of a large number of low-order adders is doubled is avoided, only the MUX module with the small area overhead is added to the input end of the adder, the chip layout area is remarkably saved, and the chip cost is reduced. And meanwhile, the efficient native transpose calculation capability is provided.

The application discloses a frequency divider and a frequency division system, and relates to the field of signal processing.The frequency divider comprises an input port, an all-pass filter, a first adder and a second adder.The input port is connected with the input end of the all-pass filter, the input end of the first adder and the input end of the second adder.The output end of the all-pass filter is connected with the input end of the first adder and the input end of the second adder.The all-pass filter filters an original signal input by the input port based on preset filter coefficients to obtain a filtered first signal.The output end of the first adder is connected with a high-pass output port of the frequency divider, and the output end of the second adder is connected with a low-pass output port of the frequency divider.The first adder is used for adding a negative value of the first signal to the original signal to obtain a high-pass signal of the frequency divider.The second adder is used for adding the first signal to the original signal to obtain a low-pass signal of the frequency divider.The application provides a frequency divider based on an all-pass filter, which effectively reduces the occupied computing resources of the frequency divider.

The application discloses a ternary computing method and system based on a double-chain difference coupling principle. A difference value (XnYn) is directly generated by a forward component Xn and a reverse component Yn in a difference coupling area, forming a three-value logic {‑1, 0, +1}, and a threshold comparison circuit is omitted, and operation follows BH=Σ(XnYn)×3^n. A hierarchical logic system composed of basic operators, minimum complete operators and global operators is constructed, and arbitrary three-value logic operation is realized; a circular waveguide structure is adopted to configure an optical path difference, so that coherent light directly forms three interference states at an output end, and optical three-value logic gates and optical full adders are realized; a double-chain six-bit structure is adopted for symbol coding, a two-dimensional geometric framework is driven to generate a symbol form, and logical and geometric expression unification is realized.

A displacement decoding unit (205) of a mesh decoding device (200) according to the present invention includes: a bypass arithmetic decoding unit (205A) configured to generate a coefficient level value by performing bypass arithmetic decoding on a displacement bit stream; an inverse quantization unit (205B) configured to generate a first transformed coefficient by performing inverse quantization on the coefficient level value; an adder (205D) configured to generate a second transformed coefficient by adding a prediction transformed coefficient and a prediction residual; an inter prediction unit (205F) configured to generate the prediction transformed coefficient by performing inter prediction by using the second transformed coefficient of a reference frame read from the frame buffer; and a second inverse transform unit (205G) configured to generate a decoded displacement by performing second inverse transform on the second transformed coefficient.

This disclosure provides a signed adder circuit, chip, computing device, and electronic device. The circuit includes: a cascaded half-adder, at least one full-adder, and a sign processor. The half-adder performs addition on the least significant bit of a first multi-bit number and the least significant bit of a second multi-bit number, outputting a first carry-value and a least significant bit result value. The at least one full-adder performs addition on the middle bit of the first multi-bit number, the middle bit of the second multi-bit number, and the first carry-value or the second carry-value output by the previous full-adder, outputting at least one second carry-value and at least one middle bit result value. The sign processor performs addition on the most significant bit of the first multi-bit number, the most significant bit of the second multi-bit number, and the second carry-value output by the previous full-adder, outputting the most significant bit result value and a sign result value.

The utility model discloses a digital signal processor (DSP) sampling conditioning circuit, which relates to the technical field of digital signal processing, and is characterized in that the output end of a voltage stabilizing circuit is connected with the input end of an anti-phase proportion operation circuit, and the output end of the anti-phase proportion operation circuit is connected with one input end of an adder circuit; the other input end of the adder circuit is connected with the output end of the sensor, and the output end of the adder circuit is connected with the input end of the DSP. According to the utility model, the measurement precision of the DSP can be improved.

The application discloses a control system for improving load response rate of a coal-fired thermal power unit under an ACE mode, which comprises a PID controller with feedforward, a first adder, a first analog AI input module, a second analog AI input module, a first analog AO output module, a second adder, a third analog AI input module, a fourth analog AI input module and a fifth analog AI input module; the output end of the fourth analog AI input module and the output end of the fifth analog AI input module are connected with the input end of the second adder, the output end of the third analog AI input module and the output end of the second adder are connected with the input end of the first adder, and the output end of the first analog AI input module, the output end of the second analog AI input module and the output end of the first adder are connected with the input end of the PID controller with feedforward; the system can realize the purpose of fast response of the coal-fired thermal power unit to load instruction change.

A circuit for transmitting an n-bit phase value between circuits includes a system clock input, an n-bit phase value generator coupled to the system clock input that generates a phase value output and an edge output indicating that the phase output value is valid, a latched clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to a control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to an output of the variable phase delay circuit, a clock input coupled to a latched clock output of the variable output clock delay circuit, and a phase out output.

The present disclosure relates to image signal and phase detection autofocus signal extraction and storage in an arithmetic logic unit. An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. A first input of an adder stage is coupled to receive an output of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive the output of the GC to binary stage. An adder input multiplexer stage includes an output coupled to a second input of the adder stage and first and second inputs coupled to outputs of the first and second adder input latches, respectively.

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

This invention provides an optimized method for integrating floating-point multiply-accumulate algorithms in a single-precision floating-point multiply-accumulate unit. During the single-precision floating-point multiply-accumulate calculation, the pipeline is implemented as follows: P0 stage: The first pipeline stage receives three operands a, b, and c as input; it performs special value judgment, product mantissa calculation, product leading zero pre-statistics, and exponent difference and comparison logic; P1 stage: The second pipeline stage receives the multiplication result, compares the product exponent with the exponent of operand c, compares the exponent difference with the product leading zero, and performs exponent difference and product leading zero comparison; after exponent alignment, the mantissa of the aligned result is summed; P2 stage: The third pipeline stage receives the mantissa summed result, adjusts the exponent data, the sign bit to be operated on, and compares the results; after completion of normalization and rounding operations, the final result is adjusted accordingly, and abnormal states are judged. A single data path is used to ensure reuse of the same logic module within the pipeline, reducing area overhead.

Inter-chip communication circuits and methods, communication interval determination circuits and methods, and chips are provided. An inter-chip communication circuit may include: a receiving circuit for receiving data frames; a memory for storing the received data frames; a counter circuit for determining the duration of the received data frames; a decoder circuit for obtaining a negative feedback adjustment value based on the amount of data to be transmitted stored in the memory; an adder circuit for determining an interval time based on the received frame duration and the negative feedback adjustment value; and a transmitting circuit for transmitting data frames by using the determined interval time as the transmission interval between data frames.

A touch detection circuit, a touch sensing chip and an electronic device are disclosed. The touch detection circuit includes: a charge / discharge circuit, a 1st-order N-bit ΔΣADC comprising an adder, an integrator, an N-bit ADC and an N-bit DAC, the adder comprising two input terminals coupled respectively to an output terminal of the charge / discharge circuit and an output terminal of the N-bit DAC, the N-bit DAC comprising an input terminal coupled to an output terminal of the N-bit ADC, wherein the integrator is configured to integrate net incoming charge that the integrator receives; the N-bit ADC is configured to quantize an output of the integrator into an N-bit digital signal; the N-bit DAC is configured to provide subtractive reference charge according to the instruction of the N-bit digital signal; and the adder is configured to derive the net incoming charge by subtracting the subtractive reference charge from the sense charge.

The invention belongs to the technical field of in-memory computing, and discloses a multi-precision in-memory computing circuit with balanced output bit width, a memory and a chip, which are characterized in that through the collaborative change of a broadcast mode of an input side and an accumulation mode of an output side, under different computing precisions, the multi-precision in-memory computing circuit with balanced output bit width is obtained; the external interface bandwidth (the number of ADCs / the number of adders) of the physical array is kept constant. According to the invention, the contradiction between high bandwidth demand in a low-precision mode and low bandwidth demand in a high-precision mode in a multi-precision in-memory computing architecture is solved, the idle waste of the output bandwidth during high-precision computing is avoided, the relatively balanced bit width of an output interface is realized, and the area cost of a chip can be greatly reduced.

A digital filter includes a delay line; coefficients coupled to the delay line; and a summer coupled to at least one of the of coefficients, wherein the coefficients each include a first value during a normal mode of operation, and wherein at least one of the coefficients comprises a second value during a transient mode of operation.

The application relates to the technical field of artificial intelligence chips, and particularly discloses an addition tree architecture supporting DNN sparse sensing and an implementation method thereof. The architecture comprises an index and data reordering module, a reconfigurable sparse addition array, an address mapping module, a partial sum storage area and an interface control unit thereof. The dynamic accumulation of random sparse data is realized by indexing and reordering the sparse multiplication results and adopting an adder array activated only when the indexes are consistent. The architecture removes the local accumulators in the traditional processing units, supports the parallel operation of calculation and accumulation decoupling, effectively improves the hardware utilization and accumulation efficiency, is suitable for the efficient addition accumulation of various neural network layers such as convolution, full connection and normalization, and has the advantages of strong structure universality, high energy efficiency ratio and low area overhead.

This invention relates to the field of adder circuit technology, specifically providing a 5-bit adder, an arithmetic operation circuit, a computing chip, and an electronic device. The adder consists of 40 transistors, including multiple XOR gates and inverters. The first input node of the third XOR gate is the first data input node, the second input node of the third XOR gate is the second data input node, the output node of the second inverter is the third data input node, the first input node of the first XOR gate is the fourth data input node, the second input node of the first XOR gate is the fifth data input node, the output node of the first inverter is the data output node, the output node of the third inverter is the first carry signal node, and the output node of the fifth inverter is the second carry signal node. This addresses the problem of the lack of high-efficiency, small-area, and high-speed 5-bit adders in related technologies.

A system and method for combining and separating non-orthogonal signals. A transmitting component includes a set of generators of non-orthogonal signals and an adder for forming a group mixture. A receiving component includes a band-pass selective filter, an analog-to-digital converter and a calculator-solver for separating signals or channels. The system and method are designed to provide an almost ideal channels separation due to a new original group mixture processing procedure performed by the calculator-solver. The system and method provide significant increase in noise-immunity and the achievement of transmission rates that are exceeded the Shannon's Capacity of the group path.

The application relates to the technical field of integrated circuit design, and discloses a reconfigurable Ising device and a chip based on FeFET construction. The application provides a reconfigurable Ising device, which comprises a calculation array part and a spin updating part. The calculation array part comprises N columns of Ising calculation columns based on FeFET construction, supports flexible setting of mutual relationships between different spins, and can realize mapping of a complex irregular spin network; the architecture of the application supports simultaneous calculation of multiple spin interaction relationships, and directly compares voltages to obtain spin results, thereby reducing timing overhead and additional hardware overhead of setting adders; according to the Ising model, the array is built based on FeFET, hardware overhead can be further reduced, and related coefficients can be long-term stored and read-write consumption can be reduced due to the non-volatility of FeFET.

A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row.

The invention relates to a method for realizing a full adder based on Flash, and belongs to the technical field of Flash storage and calculation fusion. The invention designs a full adder implementation method based on the association of inherent characteristics (multi-word line sensing (MWS), RowCopy operation and NOT logic) of Flash and multi-input majority voting (MAJ3 / MAJ5) operation, is suitable for machine learning multiply-accumulate (MAC), edge AI reasoning and other data intensive internal memory calculation scenes, and does not need to perform structural modification on Flash hardware.

The invention discloses a PE unit and a PE array based on a ripple counter, the PE unit comprises a 4b + 4b unsigned adder and a 16b ripple counter, and the working process of the PE unit comprises the following steps: obtaining the weight and activation input in a single period; adding bias to the activation; adding bias to the activation; acquiring a corresponding accumulated value according to the weight; a 16b-based ripple counter records the occurrence frequency of each weight; and subtracting the number of times of occurrence of the weight from the data subjected to pre-addition processing, and multiplying and summing with a corresponding possible value of the weight to obtain a final output. The PE array comprises a plurality of PE units as described above. According to the invention, the problems of multiplication redundancy and overhigh power consumption of the adder when the traditional INT4MAC is used for processing the overlong vector multiplication can be solved. The method can be widely applied to the field of high-resolution imaging.

This disclosure relates to a feedback loop circuit for an electrical signal. The feedback loop comprises a first branch having a first switch and a second switch, the first branch to receive an input signal and provide a first signal based on the input signal to a first adder and to provide a second signal based on the input signal to a second adder; and a second branch having a feedback line coupled between a third switch and the first adder, the second branch to provide an output signal based on the first signal and the second signal.

A per-column bias-initialization architecture for synchronous column-oriented neural-network compute arrays is disclosed. Before the start of a matrix-multiplication operation, each column's Hierarchical Integrated Latch Tree (HILT) loads a bias value and presents it as the initial operand of a recirculating adder that forms the column's output sum. All columns operate synchronously under a common array clock and advance row-synchronously through activations. This bias-initialization method eliminates the need for global post-processing bias addition, allowing each column's output-sum path to add its bias value without incurring extra latency, thereby improving utilization and preserving CASCADE's deterministic timing and column isolation.

The invention discloses an FSK signal generator based on digital logic and an implementation method. The generator comprises a synchronization module, lookup tables LUT1 and LUT2, an accumulator ADDER and a trigger. The synchronous module processes a DATA / SELECT signal by using a high-frequency clock which is not lower than ten times of the highest output frequency, the LUT1 stores a frequency division coefficient, the LUT2 stores a pulse width ratio parameter and supports 1%-99% adjustment, the accumulator counts to a threshold according to the frequency division coefficient and is reset and triggered, and the trigger stably outputs an FSK (Frequency Shift Keying) signal. The implementation method comprises the following steps: the synchronization module processes a DATASELECT signal by using a high-frequency clock, the synchronized signal drives the LUT1 to output a frequency division coefficient, the accumulator counts to a threshold value, zero clearing is carried out to generate a trigger signal, the LUT2 controls level overturning by combining a parameter and the trigger signal, and the trigger latches and outputs a stable FSK (Frequency Shift Keying) signal. The method can be used for FPGA verification, burr and delay are avoided, the test cost and difficulty are reduced, and the application range is wide.