808 results about "Adder" patented technology

The invention discloses an SM4 encryption method based on an FPGA, and relates to the technical field of data encryption, and the method comprises the steps: obtaining to-be-encrypted plaintext data; a plurality of SM4 encryption cores are configured on the FPGA chip to perform parallel encryption operation on plaintext data to be encrypted; wherein each SM4 encryption core adopts a pipeline architecture, and the pipeline architecture comprises an access device, a round function arithmetic unit and a key adder; an extraction circuit based on physical noise and integrated on the FPGA chip is utilized to generate N-bit random numbers as encryption keys of each SM4 encryption core; handshake signals are collected to calculate the operation efficiency of each SM4 encryption core; adjusting FPGA resource allocation among the SM4 encryption cores by adopting a priority scheduling algorithm according to the operation efficiency; in the encryption operation process, power consumption equalization is carried out by adopting polynomial and logical operation hybrid calculation, and time sequence randomization is carried out by adopting a random waiting period. Aiming at the problem of weak anti-difference sensitivity in the prior art, the side channel attack resistance is improved.

A system and method of performing sparse accumulation in column-wise sparse general matrix-matrix multiplication (SpGEMM) algorithms. The method includes receiving a request to perform SpGEMM based on a first matrix and a second matrix. The method includes accumulating, in a hardware buffer, a hash key and an intermediate multiplication result of the first matrix and the second matrix. The method includes performing a probe search of a hardware cache to identify a match between the hash key and a partial sum associated with the first matrix and the second matrix. The method includes generating, by a hardware adder, a multiplication result based on the partial sum and the intermediate multiplication result from the accumulation waiting buffer.

The invention provides a storage and calculation integrated neural network acceleration method and accelerator based on Fibonacci coding, and the method comprises the steps: a Fibonacci encoder of the storage and calculation integrated neural network accelerator encodes an activation value and a weight value participating in a neural network operation task from a binary system to a Fibonacci code; the Fibonacci activation and the Fibonacci weight are obtained, a DAC of a storage and calculation integrated unit in the storage and calculation integrated neural network accelerator converts the Fibonacci activation into a plurality of analog voltages, and the analog voltages are applied to word lines of each row of an SRAM array in the storage and calculation integrated unit; each unit of the SRAM array multiplies an input analog voltage by a corresponding Fibonacci weight to obtain an intermediate operation result, an adder of each column of the SRAM array redistributes charges to the intermediate operation result to complete an accumulation operation of an inner product, and the accumulation operation result is converted into a Fibonacci coded digital format through an ADC (Analog to Digital Converter) of the storage and calculation integrated unit, so as to complete the accumulation operation of the inner product. And taking the result as an operation result of the neural network operation task.

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

A disclosed approximate tensor processing unit (APTPU) includes two main components: (1) approximate processing elements (APEs) consisting of a low-precision multiplier and an approximate adder, and (2) pre-approximate units (PAUs) which are shared among the APEs in the APTPU's systolic array, functioning as the steering logic to pre-process the operands and feed them to the APEs. Performance of the disclosed APTPU across various configurations and various workloads shows that the disclosed APTPU's systolic array achieves delay, area, and power reductions, while realizing comparable accuracy to previous designs.

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

The embodiment of the invention discloses a static random access memory in-memory computing system and method, and the system comprises a feature memory which is used for storing an input signal of a neural network model; the SRAM storage array is used for storing each weight of the neural network model and performing logical operation on an input signal and each weight to obtain a plurality of logical operation results, each weight is divided into a plurality of binary blocks after CSD coding, complementary mode blocks are reserved after processing of eliminating all-zero mode blocks, and each binary block is divided into a plurality of binary blocks; after information is extracted from each complementary mode block, an index, a symbol and a value are obtained, and each weight is stored in a complementary mode block mode; the metadata storage is used for storing indexes and symbols; the adder tree is used for performing decoding and additive operation on the plurality of logical operation results according to the indexes and the symbols; the shift accumulation unit is used for performing shift accumulation on the addition result; and the post-processing unit is used for post-processing the shift accumulation result to obtain an output signal of the neural network model.

The embodiment of the invention discloses a floating point calculation device and method for a processor, electronic equipment and a storage medium, and the device comprises a mantissa alignment module which is used for carrying out the interception processing of a first mantissa of a first floating point number based on an interception digit to obtain a first addend, and carrying out the first addend based on a shift digit to obtain a second addend; the second mantissa of the second floating-point number is shifted to obtain a second addend, and the first addend and the second addend are two mantissas with aligned indexes; the interception bit number and the shift bit number are determined based on an index difference value between a first index of the first floating-point number and a second index of the second floating-point number; the adder is used for adding the first addend and the second addend to obtain a first mantissa sum; and the post-processing module is used for performing normalization processing and rounding processing on the first mantissa sum to obtain a target mantissa. Therefore, the selector processing process before the mantissa is shifted in the floating point addition calculation process can be reduced, the calculation path is shortened, and the calculation speed is improved.

The invention provides an arithmetic logic unit of a processor and a floating-point number calculation method, and belongs to the technical field of floating-point numbers. The arithmetic logic unit comprises a format conversion module and a mixed precision multiplier-adder, the format conversion module performs format conversion on a high-precision floating-point number to obtain a low-precision floating-point number, and retains an index lost in the conversion process as index auxiliary information, and when the mixed precision multiplier-adder performs multiply-add operation on the low-precision floating-point number, the mixed precision multiplier-adder performs multiply-add operation on the low-precision floating-point number. And the index auxiliary information is used for compensating the lost index, so that the precision loss of the floating-point number can be reduced when the mixed precision multiplier-adder is used.

The invention discloses an unmanned aerial vehicle inertial navigation model parameter identification method based on robust adaptive filtering. The method comprises the following steps: 1, establishing an unmanned aerial vehicle motion model and a maneuvering action library; 2, simulating and generating an ideal flight path of the unmanned aerial vehicle; 3, simulating error characteristics of the inertial navigation assembly to generate a gyroscope, and adding inertial navigation assembly output; 4, setting an initial estimation error value of the navigation physical quantity of the inertial navigation system; 5, adding the set navigation error into the reference trajectory to obtain actual navigation data; step 6, setting an initial parameter of a robust adaptive filtering algorithm; and the like. According to the method, identification of the error state quantity of the inertial navigation model of the unmanned aerial vehicle is realized, a software platform supporting modeling simulation and parameter identification of the inertial navigation model of the unmanned aerial vehicle is also established, and inertial navigation model parameter identification with good identification precision, real-time performance and reliability is realized; therefore, the inertial navigation model capable of supporting high-fidelity flight autonomous navigation simulation of the unmanned aerial vehicle is established.

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a first comparator, a first divider, a first summator and a texel adjusting unit. A first comparator to determine a first value, the first value being determined based on a smaller value of the integer portion of the input texture coordinate and the maximum offset; the first divider is used for calculating a ratio between the input offset and the first divisor to obtain a first ratio; the first summator is used for calculating the quotient of the first ratio and the sum of the first numerical value and the second numerical value to obtain a first calculation result; and the texel adjusting unit is used for determining a target texel index corresponding to the input texture coordinate according to at least one of the first calculation result and the addressing mode. According to the method, the first calculation result can be determined based on the smaller value in the two, and the value of the integer part of the input texture coordinate can be reduced within a certain limit, so that the bit width of the calculation unit is reduced.

In some embodiments, the method for scaling to a super resolution based on machine learning is provided. The method may include receiving a data stream. The device may include circuitry to upscale media by a scale factor to a super resolution. The circuitry can be configured with a number of one or more multipliers and adders for one or more neurons of one or more layers of a neural network. The number of one or more multipliers and adders can be determined based at least on the scale factor. The method may include determining a plurality of output data points corresponding to the one or more data points upscaled by the scale factor to the super resolution. The method may include providing as output the super resolution of the media. The method may further include identifying one or more features of one or more data points from the data stream.

The invention discloses a look-ahead sliding decision feedback equalizer and a Serdes receiver, and the look-ahead sliding decision feedback equalizer comprises a two-stage assembly line which is composed of an m-tap adder and an n-tap decision device based on a look-ahead structure. Each tap of the n-tap decision device comprises a three-decision device unit 3T-D, a four-decision device unit 4T-D and a five-decision device unit 5T-D, the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation, the five-decision device unit 5T-D comprises two one-out-of-four multiplexers 4-to-1 MUX used for performing look-ahead calculation, and the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation. And a judgment result output by the three-decision-device unit 3T-D is used as a selection signal to act on the four-decision-device unit 4T-D and the five-decision-device unit 5T-D. The invention aims to efficiently process data from the feed-forward equalizer and reduce the delay of a critical path in a decoding part of the sliding decision feedback equalizer.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

The embodiment of the invention provides an S-box circuit, and relates to the technical field of information security. The S-box circuit receives first data and mask data as input and outputs second data, and includes: a confusion adder that receives the first data and the mask data and outputs mask data; a first isomorphic mapping circuit that receives the masking data and outputs third data and fourth data; the first calculation circuit receives the third data, the fourth data and the fifth data and outputs sixth data; the inversion circuit is used for receiving sixth data and outputting seventh data; the second calculation circuit receives the third data, the fourth data and the seventh data and outputs eighth data; a third calculation circuit which receives the fourth data and the seventh data and outputs ninth data; and the second isomorphic mapping circuit receives the eighth data and the ninth data and outputs second data. The S-box circuit masks input data and output data through mask data, and has the capability of resisting power consumption analysis attack.

The invention discloses a hybrid precision storage and calculation control circuit based on a Sense-Switch type pFLASH. The hybrid precision storage and calculation control circuit comprises an NOR FLASH type SSpF storage and calculation array, a hybrid precision array controller, a hybrid precision shift adder and an AD module. The NOR FLASH type SSpF storage and calculation array is used for realizing convolution operation; the mixed precision array controller divides the NOR FLASH type SSpF memory calculation array according to the configured calculation precision, and completes input control and output sampling of 4, 8 or 16-bit convolution operation, and 4-bit weight programming and reading; the mixing precision shift adder performs shift addition on the output of the mixing precision array controller according to the sequence and the channel according to the configured calculation precision to obtain a 4, 8 or 16-bit convolution calculation result; the AD module is used for converting current output of the NOR FLASH type SSpF storage array into voltage output and converting an analog signal into a 4-bit digital signal. According to the method, 4, 8 or 16-bit convolution calculation can be realized in parallel, and the calculation precision can be configured.

In described examples, an integrated circuit (IC) includes a comparator, a shift calculator, an aligner, a compressor, and an adder. The comparator determines a largest one of multiple exponents. The shift calculator subtract the exponents from the determined largest exponent to provide a set of shift values. The aligner shifts a subset of a set of data values in a least significant bit direction responsive to respective ones of the shift values to generate a first number of aligned data values. The compressor generates a second number of compressed data values responsive to the first number of aligned data values. The second number is less than the first number. An adder sums the compressed data values.

Systems and methods related to efficient compression instruction handling in a processing pipeline are disclosed herein. A processing pipeline may accept a mask vector from a first register, the mask vector including a set of set bits, and may accept a payload from a second register. The processing pipeline may determine a set of prefix sums for a set of portions of the mask vector by applying the portions to a set of adders in parallel to add the set bits independently for each of the portions. The processing pipeline may determine a set of indexes for the set bits, with respect to the mask vector, in parallel, using the set of prefix sums and the set of portions of the mask vector. The processing pipeline may store a set of identified values from the payload, as identified by the set of indexes, in at least one destination register.

The invention discloses a low-power FIFO (First In First Out) module, which comprises an FIFO memory and an FIFO controller, the FIFO memory comprises a writing unit, a memory unit and a multiplexer, the FIFO controller comprises a writing pointer register, a reading pointer register, a first adder and a second adder, the FIFO controller further comprises a mux selection register and a third adder, the third adder enables a mux selection pointer signal output by the mux selection register to increase by 1 only when valid data is cached in the storage unit or new valid data is to be cached while the storage unit outputs the last valid data; and when the read signal is high, the multiplexer selects the data on the corresponding address from the storage unit according to the mux selection pointer signal and outputs the data. According to the invention, the problem of invalid flipping caused by invalid data output is solved, so that the power consumption is reduced.

In a multiply accumulate (MAC) unit, an accumulator may be implemented in two or more stages. For example, a first accumulator may accumulate products from the multiplier of the MAC unit, and a second accumulator may periodically accumulate the running total of the first accumulator. Each time the first accumulator's running total is accumulated by the second accumulator, the first accumulator may be initialized to begin a new accumulation period. In one embodiment, the number of values accumulated by the first accumulator within an accumulation period may be a user-adjustable parameter. In one embodiment, the bit width of the input of the second accumulator may be greater than the bit width of the output of the first accumulator. In another embodiment, an adder may be shared between the first and second accumulators, and a multiplexor may switch the accumulation operations between the first and second accumulators.

The invention provides a signal offset calibration method and device and a high-speed DRAM interface, and relates to the technical field of high-speed communication, and the signal offset calibration method comprises the steps: obtaining an original signal and an error signal; adding the original signal and the error signal through a DFE adder, and outputting the added signal to a sampler for sampling so as to output a corresponding sampling result; and determining an offset adjustment direction corresponding to the sampling result through an offset control logic device, and adjusting a signal output by the DFE adder according to the offset adjustment direction until the state of the level output by the output end of the DFE adder changes. According to the invention, the deviation of the input buffer can be well relieved, and the distortion of the received signal is reduced.

The invention relates to a quantum computer which comprises NV centres in diamond as quantum bits and which comprises nuclear spins strongly bound to NV centres of atomic nuclei strongly coupled to these NV centres as nuclear quantum bits, hereinafter referred to as strong nuclear quantum bits, and which comprises nuclear spins weakly bound to NV centres of atomic nuclei weakly coupled to these NV centres as nuclear quantum bits, hereinafter referred to as weak nuclear quantum bits. The resonance energy for the coupling of these weakly coupled nuclear spins of these atomic nuclei that are weakly coupled to the corresponding NV centre depends only weakly on the particular spin state of the electron configuration of the respective NV centre that is weakly coupled to this nuclear spin. The quantum computer controls nuclear spins that are weakly bound to an NV centre differently than nuclear spins that are strongly bound to the NV centre. For this purpose, it preferably has a database of nuclear quantum bits, which provides information as to whether it is a strongly or weakly coupled nuclear quantum bit.

A computer implemented method includes receiving data on which to perform elliptic curve digital signature algorithm (ECDSA) and mapping ECDSA computations from affine coordinates to projective coordinates. A complete addition formula is executed on the data with operations changing based on bits of a secret key by minimizing execution time and power consumption differences via a finite adder. Modular multiplications are executed via a finite multiplier module. At least one countermeasure selected from the group consisting of randomizing a base point, generating a secret key using a two random number seed random number generator, using a randomized secret key to generate a signature, and randomizing signature generation is executed.

The invention discloses a data processing device and method, a medium and computing equipment, and relates to the field of data processing. The device comprises a first state machine, a second state machine, a third state machine, a fourth state machine and a multiplier-adder. The first state machine is used for determining a storage address and a cumulative vector address of each data sample contained in the data packet to be subjected to dimension reduction in the memory module and sending a plurality of reading requests to the memory module; the second state machine is used for receiving original vector data returned by each reading request and sending the original vector data to the multiplier-adder; the third state machine is used for receiving accumulated vector data returned by each reading request and sending the accumulated vector data to the multiplier-adder; the multiplier-adder is used for accumulating the original vector data and the accumulated vector data in the same reading request and sending an accumulation result to the fourth state machine; and the fourth state machine is used for updating the accumulation result to the memory module. The four state machines and the multipliers work in parallel, so that the data throughput and the data processing speed are improved.

The invention relates to a dual-mode storage-calculation-encryption integrated circuit and an operation method thereof, in particular to an integrated circuit with both a PUF (Physical Unclonable Function) mode and an eCIM (Enhanced Common Information Model) mode. The dual-mode signal processor, the vector coding circuit, the word line driving circuit, the bit line driving circuit, the external signal decoding circuit, the selector circuit, the comparator circuit, the analog-to-digital converter and the shift adder circuit are arranged on the periphery; according to the PUF mode, the coupling complexity of the PUF in the spatial dimension is improved through complementary word lines, nonlinear XOR operation is achieved in each basic unit through a pairing method of two state complementary transistors, Hamming distance comparison between two columns is introduced, and the machine learning modeling attack resisting safety of the PUF is improved; according to the eCIM mode, an encrypted data weight matrix stored in a transistor is protected through XOR encryption, high-energy-efficiency and high-parallelism in-memory calculation operation is achieved through a nonvolatile transistor array, and high-parallelism in-situ decryption in-memory calculation is completed through complementary word lines.

A normalizer for performing normalization on floating-point data includes a search circuit configured to receive selected mantissa data and to output reference exponent data and shift data, the selected mantissa data being either mantissa data of the floating-point data or 2's complement data of the mantissa data, an exponent adder configured to output normalized exponent data by adding exponent data of the floating-point data and the reference exponent data, and a unidirectional mantissa shifter configured to output normalized mantissa data by performing a unidirectional shift on the selected mantissa data based on a value of the shift data.

A touch detection circuit, a touch sensing chip and an electronic device are disclosed. The touch detection circuit includes: a charge / discharge circuit, a 1st-order N-bit ΔΣADC comprising an adder, an integrator, an N-bit ADC and an N-bit DAC, the adder comprising two input terminals coupled respectively to an output terminal of the charge / discharge circuit and an output terminal of the N-bit DAC, the N-bit DAC comprising an input terminal coupled to an output terminal of the N-bit ADC, wherein the integrator is configured to integrate net incoming charge that the integrator receives; the N-bit ADC is configured to quantize an output of the integrator into an N-bit digital signal; the N-bit DAC is configured to provide subtractive reference charge according to the instruction of the N-bit digital signal; and the adder is configured to derive the net incoming charge by subtracting the subtractive reference charge from the sense charge.

The circuit includes (2m−1)-th and 2m-th lookup tables of a layer x to restore (2m−1)-th and 2m-th reception address bit strings of the layer x and (2m−1)-th and 2m-th reception information bit strings of the layer x; an m-th address conversion lookup table of the layer x to convert the (2m−1)-th reception address bit string of the layer x into that of post-conversion; an m-th adder of the layer x to add the (2m−1)-th post-conversion reception address bit string of the layer x and the 2m-th reception address bit string of the layer x and output an addition result as an m-th reception shaping bit string of a layer x+1; and an m-th lookup table of the layer x+1 to restore an m-th reception address bit string of the layer x+1 and an m-th reception information bit string of the layer x.

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

A receiver includes a decision feedback equalizer therein. The equalizer, which includes a cascaded arrangement of a first stage having a first plurality of summers therein and a second stage having a second plurality of summers therein, is configured to: (i) generate a compensated data signal by summing a current value of a data signal and a plurality of feedback signals, in response to a plurality of selection signals, (ii) generate a sampled signal including a decision value by sampling bits of the compensated data signal, in response to a plurality of divided strobe signals, and (iii) generate the feedback signals in response to a plurality of weights, the sampled signal, and at least one delayed version of the sampled signal.