591 results about "Adder" patented technology

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

The embodiment of the invention discloses a floating point calculation device and method for a processor, electronic equipment and a storage medium, and the device comprises a mantissa alignment module which is used for carrying out the interception processing of a first mantissa of a first floating point number based on an interception digit to obtain a first addend, and carrying out the first addend based on a shift digit to obtain a second addend; the second mantissa of the second floating-point number is shifted to obtain a second addend, and the first addend and the second addend are two mantissas with aligned indexes; the interception bit number and the shift bit number are determined based on an index difference value between a first index of the first floating-point number and a second index of the second floating-point number; the adder is used for adding the first addend and the second addend to obtain a first mantissa sum; and the post-processing module is used for performing normalization processing and rounding processing on the first mantissa sum to obtain a target mantissa. Therefore, the selector processing process before the mantissa is shifted in the floating point addition calculation process can be reduced, the calculation path is shortened, and the calculation speed is improved.

The invention provides an arithmetic logic unit of a processor and a floating-point number calculation method, and belongs to the technical field of floating-point numbers. The arithmetic logic unit comprises a format conversion module and a mixed precision multiplier-adder, the format conversion module performs format conversion on a high-precision floating-point number to obtain a low-precision floating-point number, and retains an index lost in the conversion process as index auxiliary information, and when the mixed precision multiplier-adder performs multiply-add operation on the low-precision floating-point number, the mixed precision multiplier-adder performs multiply-add operation on the low-precision floating-point number. And the index auxiliary information is used for compensating the lost index, so that the precision loss of the floating-point number can be reduced when the mixed precision multiplier-adder is used.

The invention discloses an ALU, a processor, a chip, equipment and a texel index calculation method, and belongs to the technical field of chips. The ALU comprises a first comparator, a first divider, a first summator and a texel adjusting unit. A first comparator to determine a first value, the first value being determined based on a smaller value of the integer portion of the input texture coordinate and the maximum offset; the first divider is used for calculating a ratio between the input offset and the first divisor to obtain a first ratio; the first summator is used for calculating the quotient of the first ratio and the sum of the first numerical value and the second numerical value to obtain a first calculation result; and the texel adjusting unit is used for determining a target texel index corresponding to the input texture coordinate according to at least one of the first calculation result and the addressing mode. According to the method, the first calculation result can be determined based on the smaller value in the two, and the value of the integer part of the input texture coordinate can be reduced within a certain limit, so that the bit width of the calculation unit is reduced.

The invention discloses a look-ahead sliding decision feedback equalizer and a Serdes receiver, and the look-ahead sliding decision feedback equalizer comprises a two-stage assembly line which is composed of an m-tap adder and an n-tap decision device based on a look-ahead structure. Each tap of the n-tap decision device comprises a three-decision device unit 3T-D, a four-decision device unit 4T-D and a five-decision device unit 5T-D, the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation, the five-decision device unit 5T-D comprises two one-out-of-four multiplexers 4-to-1 MUX used for performing look-ahead calculation, and the four-decision device unit 4T-D is a one-out-of-four multiplexer 4-to-1 MUX used for performing look-ahead calculation. And a judgment result output by the three-decision-device unit 3T-D is used as a selection signal to act on the four-decision-device unit 4T-D and the five-decision-device unit 5T-D. The invention aims to efficiently process data from the feed-forward equalizer and reduce the delay of a critical path in a decoding part of the sliding decision feedback equalizer.

Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.

The invention discloses a hybrid precision storage and calculation control circuit based on a Sense-Switch type pFLASH. The hybrid precision storage and calculation control circuit comprises an NOR FLASH type SSpF storage and calculation array, a hybrid precision array controller, a hybrid precision shift adder and an AD module. The NOR FLASH type SSpF storage and calculation array is used for realizing convolution operation; the mixed precision array controller divides the NOR FLASH type SSpF memory calculation array according to the configured calculation precision, and completes input control and output sampling of 4, 8 or 16-bit convolution operation, and 4-bit weight programming and reading; the mixing precision shift adder performs shift addition on the output of the mixing precision array controller according to the sequence and the channel according to the configured calculation precision to obtain a 4, 8 or 16-bit convolution calculation result; the AD module is used for converting current output of the NOR FLASH type SSpF storage array into voltage output and converting an analog signal into a 4-bit digital signal. According to the method, 4, 8 or 16-bit convolution calculation can be realized in parallel, and the calculation precision can be configured.

In described examples, an integrated circuit (IC) includes a comparator, a shift calculator, an aligner, a compressor, and an adder. The comparator determines a largest one of multiple exponents. The shift calculator subtract the exponents from the determined largest exponent to provide a set of shift values. The aligner shifts a subset of a set of data values in a least significant bit direction responsive to respective ones of the shift values to generate a first number of aligned data values. The compressor generates a second number of compressed data values responsive to the first number of aligned data values. The second number is less than the first number. An adder sums the compressed data values.

Systems and methods related to efficient compression instruction handling in a processing pipeline are disclosed herein. A processing pipeline may accept a mask vector from a first register, the mask vector including a set of set bits, and may accept a payload from a second register. The processing pipeline may determine a set of prefix sums for a set of portions of the mask vector by applying the portions to a set of adders in parallel to add the set bits independently for each of the portions. The processing pipeline may determine a set of indexes for the set bits, with respect to the mask vector, in parallel, using the set of prefix sums and the set of portions of the mask vector. The processing pipeline may store a set of identified values from the payload, as identified by the set of indexes, in at least one destination register.

The invention discloses a low-power FIFO (First In First Out) module, which comprises an FIFO memory and an FIFO controller, the FIFO memory comprises a writing unit, a memory unit and a multiplexer, the FIFO controller comprises a writing pointer register, a reading pointer register, a first adder and a second adder, the FIFO controller further comprises a mux selection register and a third adder, the third adder enables a mux selection pointer signal output by the mux selection register to increase by 1 only when valid data is cached in the storage unit or new valid data is to be cached while the storage unit outputs the last valid data; and when the read signal is high, the multiplexer selects the data on the corresponding address from the storage unit according to the mux selection pointer signal and outputs the data. According to the invention, the problem of invalid flipping caused by invalid data output is solved, so that the power consumption is reduced.

In a multiply accumulate (MAC) unit, an accumulator may be implemented in two or more stages. For example, a first accumulator may accumulate products from the multiplier of the MAC unit, and a second accumulator may periodically accumulate the running total of the first accumulator. Each time the first accumulator's running total is accumulated by the second accumulator, the first accumulator may be initialized to begin a new accumulation period. In one embodiment, the number of values accumulated by the first accumulator within an accumulation period may be a user-adjustable parameter. In one embodiment, the bit width of the input of the second accumulator may be greater than the bit width of the output of the first accumulator. In another embodiment, an adder may be shared between the first and second accumulators, and a multiplexor may switch the accumulation operations between the first and second accumulators.

The invention relates to a quantum computer which comprises NV centres in diamond as quantum bits and which comprises nuclear spins strongly bound to NV centres of atomic nuclei strongly coupled to these NV centres as nuclear quantum bits, hereinafter referred to as strong nuclear quantum bits, and which comprises nuclear spins weakly bound to NV centres of atomic nuclei weakly coupled to these NV centres as nuclear quantum bits, hereinafter referred to as weak nuclear quantum bits. The resonance energy for the coupling of these weakly coupled nuclear spins of these atomic nuclei that are weakly coupled to the corresponding NV centre depends only weakly on the particular spin state of the electron configuration of the respective NV centre that is weakly coupled to this nuclear spin. The quantum computer controls nuclear spins that are weakly bound to an NV centre differently than nuclear spins that are strongly bound to the NV centre. For this purpose, it preferably has a database of nuclear quantum bits, which provides information as to whether it is a strongly or weakly coupled nuclear quantum bit.

The invention relates to a dual-mode storage-calculation-encryption integrated circuit and an operation method thereof, in particular to an integrated circuit with both a PUF (Physical Unclonable Function) mode and an eCIM (Enhanced Common Information Model) mode. The dual-mode signal processor, the vector coding circuit, the word line driving circuit, the bit line driving circuit, the external signal decoding circuit, the selector circuit, the comparator circuit, the analog-to-digital converter and the shift adder circuit are arranged on the periphery; according to the PUF mode, the coupling complexity of the PUF in the spatial dimension is improved through complementary word lines, nonlinear XOR operation is achieved in each basic unit through a pairing method of two state complementary transistors, Hamming distance comparison between two columns is introduced, and the machine learning modeling attack resisting safety of the PUF is improved; according to the eCIM mode, an encrypted data weight matrix stored in a transistor is protected through XOR encryption, high-energy-efficiency and high-parallelism in-memory calculation operation is achieved through a nonvolatile transistor array, and high-parallelism in-situ decryption in-memory calculation is completed through complementary word lines.

The circuit includes (2m−1)-th and 2m-th lookup tables of a layer x to restore (2m−1)-th and 2m-th reception address bit strings of the layer x and (2m−1)-th and 2m-th reception information bit strings of the layer x; an m-th address conversion lookup table of the layer x to convert the (2m−1)-th reception address bit string of the layer x into that of post-conversion; an m-th adder of the layer x to add the (2m−1)-th post-conversion reception address bit string of the layer x and the 2m-th reception address bit string of the layer x and output an addition result as an m-th reception shaping bit string of a layer x+1; and an m-th lookup table of the layer x+1 to restore an m-th reception address bit string of the layer x+1 and an m-th reception information bit string of the layer x.

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

A hardware acceleration circuit, a data processing acceleration method, a chip, and an accelerator are provided. The hardware acceleration circuit includes: an exponential function module, configured to obtain exponential function values of a plurality of data elements in a data set; an adder, configured to obtain an addition operation result of the exponential function values; a first processing circuit, configured to perform preset processing on the addition operation result, to process the addition operation result into at least first data and second data; a second processing circuit, configured to perform preset processing on at least the first data and the second data, to obtain a reciprocal of the addition operation result; and a third processing circuit, configured to perform preset processing on an exponential function value of an ith data element in the data elements and the reciprocal, to obtain a specific function value of the ith data element.

The invention discloses a randomized data weighted average algorithm circuit applied to a Sigma-Delta ADC, and relates to the technical field of integrated circuits, and the randomized data weighted average algorithm circuit applied to the Sigma-Delta ADC comprises a thermometer code-to-binary code circuit, a random number generation circuit, a full adder circuit and a shifter circuit. The output result of the quantizer is selected through the thermometer code-to-binary code module and the result of the random number generation module to judge whether a pointer needs to be subjected to randomized definition, and then the result of the previous moment is summed through the full adder circuit. And finally, the work of converting the thermometer code into the DWA code is completed through the barrel-shaped shifter circuit, so that the influence caused by the mismatch of the DAC unit can be reduced, the nonlinear problem caused by multi-bit quantization can be solved, the algorithm circuit is simple in structure, and the performance of the Sigma-Delta analog-to-digital converter circuit is greatly improved.

A communication device includes: a first adder that adds a reproduction sound to a communication sound of a remote utterer and outputs the communication sound additionally including the reproduction sound to a speaker; and an acoustic echo canceler that cancels, on the basis of the communication sound to serve as a reference signal, an echo component of the communication sound contained in an input signal acquired by a microphone configured to collect a sound in a vicinity.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

The invention discloses a circuit and a method for demodulating current received by an instrument bus host, and relates to the technical field of instruments. The current demodulation circuit comprises an adder, the first input end of the adder is connected with an instrument bus MBUS to receive MBUS signals, the second input end of the adder receives reference voltage signals, and the output end of the adder outputs summing voltage signals; the resistor and capacitor charging and discharging device is connected with the output end of the summator so as to process the summing voltage signal; and the reverse input end of the comparator receives the MBUS signal, and the positive input end of the comparator receives the summing voltage signal processed by the resistor-capacitor charging and discharging device so as to determine the logic level corresponding to the MBUS signal based on the signal level of the output end of the comparator. According to the invention, the problem that the MBUS host receiving circuit cannot be compatible with all MBUS meters is solved.

The invention discloses a floating-point number operation circuit based on an SRAM (Static Random Access Memory) and an in-memory operation chip. The operation circuit is used for S1, calculating the exponent sum and mantissa product of the multi-bit floating-point number input value and the multi-bit floating-point number weight value according to bits; s2, determining a maximum index in all the index sums, and calculating a difference value between the maximum index and the index sums of each row; s3, firstly generating a self-subtraction value with an adjustable initial value, then comparing the self-subtraction value with each difference value, generating an addition control signal, and finally judging whether each row of mantissa products are input into the adder tree for addition or not; s4, after comparison with the index sum of all rows is completed, performing self-subtraction operation on the self-subtraction value, and executing the step S3; when the self-subtraction value returns to zero, the mantissa accumulation result is used as the sum of digits; and S5, generating a multiply-accumulate operation result according to the maximum index and the sum of digits. According to the invention, through a mechanism of ''global difference value decreasing traversal + multi-round row data screening'', a complex shift circuit is avoided, and the calculation efficiency is improved.

A system includes a computation circuit, a memory array operably coupled with the computation circuit, and a controller configured to input a plurality of input data bits to the computation circuit, identify a number of accumulation associated with the plurality of input data bits, based on the number of accumulation, determine whether to enable or disable at least one component of the computation circuit, and based on a determination to enable or disable, generate a control signal to enable or disable the at least one component of the computation circuit.

Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.

The invention discloses a hierarchical attention enhancement remote sensing image super-resolution system based on a state space model, and relates to the field of computer vision and remote sensing image processing. According to the system, a low-resolution remote sensing image, a primary feature extraction module, a multistage state space model feature extraction module, a first adder module, an image reconstruction module and a high-resolution remote sensing image interact in sequence; the primary feature extraction module and the first adder module interact front and back; and the multi-level state space model feature extraction module, the hierarchical feature attention enhancement module and the first adder module interact in sequence. According to the method, the problem that shallow-layer high-frequency information is forgotten during multi-layer feature extraction in a traditional super-resolution method can be relieved, and then hierarchical features are enhanced; and the limited global-local consistency feature learning capability of the state space model is compensated, and competitive calculation complexity is achieved while the super-resolution performance of the remote sensing image is improved.

A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.

A computer-implemented method includes receiving performing a fused modular multiply and add operation to compute d=((a*b)+c) % p, wherein a, b, and c, are provided as a set of operands. A first multiply-and-accumulate unit computes a binary multiplication to compute a*b. A second multiply-and-accumulate unit computes a first intermediate result by updating a result of the binary multiplication using p. An accumulator of a third multiply-and-accumulate unit is initialized with c. The third multiply-and-accumulate unit computes a second intermediate result using the first intermediate result and c. An adder unit subtracts a portion of the second intermediate result from a portion of the result of the binary multiplication. The output of the adder is provided as a result of the fused modular multiply and add operation.

A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.

The invention discloses a decision feedback equalizer and a receiver. The decision feedback equalizer comprises four data paths with the same structure, and each data path comprises an adder, a comparator module, a data selector, a latch, a primary clock control latch and a secondary clock control latch which are electrically connected in sequence. In the application, after receiving the input data, the adders in the four data paths are summed with the tap coefficients of the last four taps to obtain the summed data, then the comparator sums the summed data and the first tap coefficient, and sampling is carried out to obtain the sampling data; the data selector selects a correct summation result according to the output data and the sampling data of the previous path; the data output by the data selector is converted into non-return-to-zero code data through the latches, and the non-return-to-zero code data passes through the first-stage clock control latch and the second-stage clock control latch to obtain delayed data, so that rapid and accurate data equalization is realized, and the equalization capability of the decision feedback equalizer is improved.

The invention provides a digital intercept error optimization circuit and a communication device wherein the digital intercept error optimization circuit comprises: a first adder, a first input end of which is connected with a signal input end; the input end of the bit intercepting circuit is connected with the output end of the first summator, the output end of the bit intercepting circuit is connected with the signal output end, and the bit intercepting circuit is used for performing bit intercepting processing on the signal output by the first summator to obtain a bit intercepting signal; the first input end of the intercept error processing circuit is connected with the output end of the intercept circuit, the second input end of the intercept error processing circuit is connected with the output end of the frequency factor generation circuit, and the third input end of the intercept error processing circuit is connected with the output end of the first adder; and the output end of the intercept error processing circuit is connected with the second input end of the first adder. According to the invention, the effect of improving the in-band signal-to-noise ratio of the signal is achieved.