555 results about "Adder" patented technology

A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes providing a plurality of successive full adders, each one of the full adders being associated with a corresponding one of the bits of the plural bit read data. Each one of the full adders has a summation output, a carry bit input and a carry bit output. The method includes adding in each one of the full adders: (a) a corresponding bit of plural bit input data provided by the director; (b) the corresponding one of the bits of the plural bit read data; and, (c) a carry bit fed the carry bit input from a preceding full adder. Each one of the full adders provides: (a) a carry bit on the carry output thereof representative of the most significant bit produced by the full adder; and, (b) a bit on the summation output representative of a least significant bit produced by the full adder. The bit on the summation output is stored in a corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, the carry bit produced from one of the full adders to the carry bit input of a next successive full adder selectively in accordance with a corresponding bit of a plural bit carry bit mask provided by the director providing a full adder for each one of the bits of the plural bit read stored. The full adder has a carry bit input and a carry bit output. The method includes adding each one of a bits of plural bit input data provided by the director with a corresponding one of the bits of the plural bit read data in the provided full adder together with a carry bit fed the carry bit input of such provided full adder. The full adder provides: a carry output bit; and, a summation of the bits fed to such provided full adder to the corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, a carry bit produced by one full adder provided for a lower order bit of the plural bit read data to the carry bit input of a second full adder provided by for next, successive higher order bit of the plural bit read data selectively in accordance with one of a plurality of bits of a carry bit mask provided by the director.

To provide an intra prediction apparatus which can circumvent a hazard problem and improve the time reduction effect. An intra prediction apparatus 11 performs intra predictions of a picture. The intra predictions include: second intra predictions of respective second blocks (blocks) which are obtained by dividing a first pixel block; and a first intra prediction of the first block (macroblock) which constitutes the picture. The intra prediction apparatus 11 includes: an intra prediction unit (a prediction unit 113, an orthogonal transform and quantization unit 115, an inverse orthogonal transform and inverse quantization unit 116, and an adder 117) which performs the intra predictions; and a control unit 119 which controls the intra prediction unit to perform in parallel the intra prediction of the macroblock and the intra predictions of the respective pixel blocks.

An adder unit (60e) reads a desired CGH pattern from a pattern memory unit (60a) and a phase distortion correction pattern from a distortion-correction pattern memory unit (60d) and adds both patterns together to generate a phase distortion corrected pattern. A control unit (60g) controls a phase modulation module (40) in accordance with the phase distortion corrected pattern. Accordingly, phase-modulated light based on the desired phase pattern can be generated precisely, easily and quickly.

A circuit for calculating a sum of products, each product having a q-bit binary operand and a k-bit binary operand, where k is a multiple of q,includes a q-input carry-save adder (CSA); a multiplexer (10) by input of the adder, having four k-bit channels respectively receiving the value 0, a first (Yi) of the k-bit operands, the second k-bit operand (M[63:0], mi), and the sum of the two k-bit operands, the output of a multiplexer of rank t (where t is between 0 and q−1) being taken into account by the adder with a t-bit left shift; and each multiplexer having first and second path selection inputs, the bits of a first of the q-bit operands being respectively supplied to the first selection inputs, and the bits of the second q-bit operand being respectively supplied to the second selection inputs.

This invention relates to a method for automatically configuring address in MANET which combines itself with AODV route to increase repeated address test efficiency including: first of all, the s, a node of MANET, generates a temporary address for transmitting address configuration information and generates an experiment address then to broadcast AREQ and test the uniqueness of the requested address. The nodes who got the AREQ should refresh the route lists, if MANET node finds its own IP address or that in the route list is the same with the adder, that shows the adder is used. AREP is broadcast to s which generates a new address after receiving AREP and repeats the adder test. If s does not receive AREP, it assigns the adder to netcards.