11results about "Amplitude demodulation" patented technology

Receiving device, comprising: a frequency mixer (11) configured to mix a received signal input therein and a local signal generated by a local oscillator (12) in order to convert a frequency of the received signal into a baseband; an envelope demodulator (13) configured to perform an envelope demodulation of an output of the frequency mixer (11); an upper sideband demodulator (14) configured to demodulate only one upper sideband of an output from the frequency mixer (11) by single-sideband demodulation; a lower sideband demodulator (15) configured to demodulate only one lower sideband of the output from the frequency mixer (11) by single-sideband demodulation; a first adder (16) configured to add an output from the envelope demodulator (13) and a first inverted output obtained by inverting an output from the upper sideband demodulator (14); a second adder (17) configured to add the output from the envelope demodulator (13) and a second inverted output obtained by inverting an output from the lower sideband demodulator (15); and a third adder (18) configured to add the output from the envelope demodulator (13), a third inverted output obtained by inverting an output from the first adder, and a fourth inverted output obtained by inverting an output from the second adder to produce a demodulation signal.

To provide a demodulation signal generator.SOLUTION: A demodulation signal generator is coupled to an air-pulse generator comprising a flap pair, and includes a resonance circuit. The resonance circuit produces a first demodulation signal and a second demodulation signal. The resonance circuit and the flap pair co-perform a resonance operation, so that the first demodulation signal and the second demodulation signal are generated via the co-performed resonance operation and have opposite polarity. The flap pair performs a differential movement to form an opening to perform a demodulation operation on a modulated air pressure variation.SELECTED DRAWING: Figure 1

Method for unmapping a modulation symbol comprising: a classification (101) of each bit of the symbol into a first group or a second group; a determination (102) of different pairs, each defining a slope and a y-intercept of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation; for each bit of the first group, a calculation (103) of LLR as a product between a multiplicative factor and a real or imaginary part of the symbol; a verification (104) of inequalities; for each bit of the second group, a calculation (108) of LLR as a function of the real and imaginary parts of the symbol and as a function of parameters selected (107) from subsets of the results obtained for the inequalities (105, 106). Figure for the abstract: Fig. 1

An electronic circuit (12) connected to a variable-excitation sensor (24) and comprising:a digital envelope detector (20) arranged to acquire signal that is produced by the sensor in response to an excitation signal, the detector comprising:an analog-to-digital converter (22) arranged to sample the measurement signal in such a manner as to produce sample points during successive observation windows of duration T that comprise a number NS of sample points, the sample points being spaced apart by a sampling period TS, the sampling period TS and the duration T being such that:TS=NP·T0+(NT / NS)·T0 and T=NS·TS,where T0 is one excitation period of the excitation signal, where NP, NT, and NS are non-zero natural integers, and where NT is not a multiple of NS.

Device (100) comprising the following: a processor (120); and a receiver that is configured to: to receive a phase-shift keying (PSK) modulated signal from a transceiver (113), to unwind the PSK-modulated signal, to feed the PSK-modulated signal to a maximum probability sequence estimation (MLSE) equalizer, wherein the MLSE equalizer has a first main tap gain lookup table (LUT) and a first inter-symbol interference (ISI) LUT corresponding to even time samples, and a second MTG LUT and a second ISI LUT corresponding to odd time samples.

The invention relates to a synchronous modulation system using amplitude modulation, which basically consists of a modulator and a demodulator able to transmit digital signals at double the frequency of its carrier wave. For this purpose, the system uses analog and digital circuits that combine to modulate, separately, the positive half and the negative half of the carrier sine wave, such that in a single cycle of the carrier wave, two different information bits can be sent. The demodulator-modulator unit can be easily combined with other units to form wired or wireless communication systems and even optical or sonic systems with minimal generation of parasitic harmonics, resulting in a minimum bandwidth requirement for operation.

A system and method to process received quadrature signals is presented. A received signal is processed into in-phase and quadrature components. A multiplexer alternately outputs the analog in-phase component signal and the analog quadrature component signal at the output terminal as a multiplexer output signal. An analog-to-digital converter digitizes the signals. A demultiplexer is configured to receive the digital output stream, and, at a frequency determined by a second control signal, alternately output the digital output stream at a first output terminal of the demultiplexer as a digital representation of the in-phase component signal and a second output terminal of the demultiplexer as a digital representation of the quadrature component signal. A filter system is configured to impose a one-half sampling period delay on at least one of the digital representation of the in-phase component signal and the digital representation of the quadrature component signal.

Method for unmapping a modulation symbol comprising: a classification (101) of each bit of the symbol into a first group or a second group; a determination (102) of different pairs, each defining a slope and a y-intercept of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation; for each bit of the first group, a calculation (103) of LLR as a product between a multiplicative factor and a real or imaginary part of the symbol; a verification (104) of inequalities; for each bit of the second group, a calculation (108) of LLR as a function of the real and imaginary parts of the symbol and as a function of parameters selected (107) from subsets of the results obtained for the inequalities (105, 106). Figure for the abstract: Fig. 1

The invention relates to a method for demodulation comprising the following steps: - exciting a oscillation element (1) which is mounted such that it can oscillate and is designed as a beam, at least in some sections, to oscillate in the range of a resonant frequency of the oscillation element (1), an excitation signal (Aact) which varies over time, particularly periodically, being used for the excitation, and at least the variation of the excitation signal (uact) over time being known or being determined; - detecting a modulated oscillation of the oscillation element (1) by means of at least one sensor (2), the sensor (2) supplying a sensor measured variable (SMG) which varies over time as a function of an amplitude (Ac) and a phase (φc) of the modulated oscillation of the oscillation element (1). According to the invention, the method comprises the following step: - generating a first comparison signal (VS1) by amplitude modulation of a known demodulation signal (DMS) which varies over time, particularly periodically, by means of the sensor measured variable (SMG) which varies over time.

Exemplary embodiments are disclosed of demodulator circuits for amplitude shift keying (ASK) communication demodulation. In an exemplary embodiment, a demodulator circuit is configurable (e.g., modular and / or scalable, etc.) to include any number of levels (one or more N-Levels) of demodulation. Each level of the demodulator circuit includes a peak detector, a bandpass filter, and a lowpass filter and control capacitor(s). The bandpass filter is coupled with and between the peak detector and the lowpass filter and control capacitor(s). Each level of the demodulator circuit may be identical to each other and include the same or similar components (e.g., peak detector, bandpass filter, lowpass filter and control capacitor(s)). And each demodulator circuit level (Level-1, Level-2 . . . Level-N) may be coupled with a summing voltage amplifier. The summing voltage amplifier may be coupled with an adaptive DC-offset and a lowpass filter, which, in turn, is coupled with a microcontroller.