321 results about "Phase error" patented technology

The invention relates to the technical field of artificial intelligence, in particular to an electrical connection safety management and control method based on intelligent monitoring, which comprises the steps of data acquisition, time synchronization, quality evaluation, feature engineering and the like. According to the method, electric, thermal, mechanical, acoustic and other channels are placed on the same time axis through unified alignment and quality marking of multi-modal data and two-stage time synchronization and resampling, explicit marking is carried out on missing, noise and abnormal points, the weight of a subsequent algorithm can be reduced or skipped according to marks, and misjudgment caused by phase errors and dirty data is reduced.

The invention discloses a GNSS anti-interference closed-loop phase self-correction method based on deep learning, and relates to the technical field of satellite navigation and artificial intelligence, and the method comprises the steps: obtaining an anti-interference array output signal and weight information through an array antenna and space-time adaptive processing; extracting a carrier-to-noise ratio, a weight phase feature and historical positioning quality, and constructing a deep learning feature vector; reasoning an array element-level phase correction reference quantity by using a multi-layer perceptron model, and realizing accurate phase compensation of an array output signal by combining phase error layered modeling, quick-change disturbance prediction and weight sensitivity estimation; an anti-interference perception observation covariance dynamic scaling mechanism is introduced into RTK positioning calculation; on-line learning and model updating are triggered through a positioning quality evaluation result, so that the system has an adaptive evolution capability. According to the method, the GNSS carrier phase quality and the positioning precision under the strong interference condition can be remarkably improved, deep fusion of anti-interference processing and high-precision positioning is realized, and the method has important engineering application value.

The invention particularly relates to a method for converting pseudo code capture into tracking phase compensation under clock frequency offset. The method comprises the steps of band-pass sampling and digital down-conversion, local pseudo code sequence generation, twice pseudo code capture and phase compensation. Selecting a sampling frequency and processing a signal through a band-pass sampling theorem, and generating a local pseudo code based on a Gold code; a PMF-FFT method of a mobile pseudo code is adopted to complete first-time pseudo code capture, a multiplexing capture module executes second-time full-range capture, and pseudo code phase offset is accurately calculated; and finally, adjusting the local pseudo code phase through the total phase compensation value, so that the phase difference between the input signal and the local pseudo code is controlled within a half chip. According to the method, hardware cost does not need to be increased, the problem of inaccurate phase compensation under clock frequency offset, large frequency offset and low carrier-to-noise ratio scenes is effectively solved, it is guaranteed that pseudo code capture is smoothly converted into tracking, and the tracking reliability of a receiver is improved.

The invention relates to the technical field of microwave photonics, and discloses a full-band noise microwave source system and a microwave signal generation method. An optical reference unit is used for generating an optical reference signal; the photoelectric phase detection unit is connected with the optical reference unit and is used for receiving the optical reference signal and a feedback signal sent by the microwave oscillation unit and outputting a beat frequency electric signal for reflecting a phase error; the servo control unit is connected with the photoelectric phase detection unit and the microwave oscillation unit and is used for separating the beat frequency electric signal into a low-frequency control signal and a high-frequency control signal; the microwave oscillation unit is connected with the servo control unit and outputs a target microwave signal in response to the low-frequency control signal and the high-frequency control signal. A beat frequency electric signal is separated into a low-frequency path and a high-frequency path by using the servo control unit, so that targeted suppression of phase noise of different frequency bands in a single signal source is realized.

The invention discloses a drill rod signal transmission monitoring control method, which comprises the following steps: capturing drill rod axial vibration waveform and peripheral magnetic field vector change data in real time, analyzing and marking potential resonance frequency points, calculating magnetic field intensity break variable, and judging a geomagnetic anomaly region; determining the relevance between a resonance frequency point and geomagnetic mutation through time alignment processing, and separating and coupling interference signals; generating an anti-phase damping wave according to the resonance frequency point, dynamically adjusting the amplitude, and injecting a pre-compensation phase to counteract carrier offset; the signal-to-noise ratio and the phase error after suppression are calculated in real time, and a parameter readjustment process is triggered to ensure the suppression effect; when the rock drilling vehicle enters a new rock stratum, parameters are automatically recorded and updated to adapt to different rock stratum interference characteristics; the drilling stability and the signal quality are obviously improved, and the equipment loss and the maintenance cost are reduced.

The invention relates to the technical field of simulation design, in particular to a design method and system based on a radar antenna, and the method comprises the following steps: resolving a phase error based on thermal deformation, analyzing a dynamic sidelobe variance in combination with displacement spectrum integration and covariance mapping, and generating a waveguide skeleton through electromagnetic energy mapping fluid damping; according to the method, thermally induced phase error data is introduced, the influence of structural deformation on the phase is accurately calculated, and meanwhile, calculation of dynamic group delay and group delay difference is combined, so that the phase correction accuracy is improved. Prediction of influence of structural deformation on electrical performance, data fusion of multiple physical fields and automatic process optimization are realized, design precision and efficiency are improved, limitation of single simulation software is avoided, factors such as material loss and gain evolution are accurately corrected in the design process, performance requirements of the high-frequency radar are met, and complex environment adaptability is improved.

The invention discloses an impedance-invariant vector synthesis phase shifter, an array element and a phased array, and relates to the technical field of phased array design. According to the impedance-invariant vector synthesis phase shifter provided by the invention, two capacitive compensation branches are arranged in each Gilbert unit of a variable gain amplifier, and the capacitive compensation branches are connected to a circuit only when bits are turned off, so that the output impedance of the unit is kept unchanged when the bits are turned on and turned off, and the output impedance of the unit is not changed when the bits are turned off. The phase shifting precision of the phase shifter is effectively improved, the root mean square phase error of the phase shifter is reduced to be within the acceptable range of the engineering field, phase shifting is directly carried out according to the most ideal condition based on IQ orthogonal signals, complicated calibration work is avoided, and the calibration problem of the vector synthesis phase shifter is solved. The invention further provides an array element which adopts the impedance-invariant vector synthesis phase shifter, the continuous time linear equalizer and the current mode attenuator and has the advantage of being convenient to deploy.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention discloses a carrier ring auxiliary code delay phase-locked loop tracking method, system and device and a medium, and belongs to the technical field of signal tracking, and the method comprises the steps: obtaining a digital intermediate frequency signal, and constructing a code loop model; executing code tracking through the code loop model to obtain a code phase error measurement value, and determining a relationship between a carrier-to-noise ratio and a noise covariance; a measurement noise covariance matrix model is obtained through combination of a code phase error measurement value and a carrier-to-noise ratio dynamic state and is used for first adjustment of a filter. According to the invention, a measurement noise covariance matrix is dynamically adjusted based on real-time carrier-to-noise ratio estimation, so that the filter can accurately adapt to signal quality change, fully trust an accurate measurement value when a signal is strong, greatly reduce tracking jitter, achieve higher pseudo-range measurement precision, and automatically reduce dependence on the measurement value under noise interference when a signal is weak. In turn, the method depends on smooth prior model prediction.

The invention discloses a millimeter wave dual-polarization phased-array antenna beam forming method and device, and relates to the technical field of high-frequency communication, and the method comprises the following steps: obtaining a complex weight signal of each array element in an antenna array under a horizontal polarization channel and a vertical polarization channel, respectively carrying out amplitude response and phase response acquisition and calibration processing on the complex weight signal; performing dynamic extraction and modeling on amplitude errors and phase errors of each array element in different polarization channels; on the basis of error estimation, constructing a machine learning prediction module comprising a time sequence prediction model; performing joint estimation on a real-time error estimation result and a prediction error result; constructing a hardware-software collaborative calibration structure comprising a dynamic gain control module on the basis of the compensation weight; beam focusing of the target space area is realized; according to the invention, the hidden problems of beam offset, sidelobe lifting, gain loss and the like caused by inconsistency of polarization channels are solved.

The invention discloses a loop resistance measuring method, system and device, and relates to the technical field of electrical measurement. The method comprises the following steps of: performing loop data acquisition at each interface of the disconnecting switch adopting a three-channel wiring mode, injecting excitation current by an excitation source, and acquiring three-channel voltage original signals and initial sampling flow by a differential isolation amplifier to obtain the initial sampling flow; time sequence identification is carried out on the initial sampling flow to complete sample starting and ending point identification, inter-channel time alignment is completed, and a synchronous voltage sample set is output. According to the invention, by constructing a complete data chain covering high-precision synchronous sampling, adaptive signal processing, phase compensation calculation and intelligent statistical diagnosis, the problems of low measurement precision and insufficient anomaly identification capability caused by poor synchronism, phase error and lack of deep analysis in a traditional method are solved; the accuracy and anti-interference performance of loop resistance measurement and the intelligent level of state diagnosis are improved.

The invention discloses an encryption burst communication receiving method based on an FPGA, and belongs to the technical field of burst communication. According to the invention, the problems of poor synchronization performance and poor anti-interference capability at the receiving end in the existing method are solved. According to the method, the carrier synchronization range is expanded by introducing the pilot frequency to enable the synchronization heads to be '1', the limitation that a conventional frequency offset estimation algorithm can only work under the condition that the Doppler frequency shift is smaller than 0.5 times of the symbol rate is broken through, and the capacity of the system for adapting to the high-dynamic environment is improved. A spreading code continuous tracking working mode is designed, coarse estimation and synchronization are carried out in a frame header part, spreading codes are still adopted in an information part, and continuous tracking is carried out, so that the system can adjust the phase of the spreading codes in real time in the whole frame to solve the problem of phase error accumulation caused by adopting a low-precision clock; the problems that when one frame of data at the sending end is long, the synchronization performance is reduced when a low-precision clock is adopted, and even effective synchronization cannot be achieved are solved. The method can be applied to the field of burst communication.

The invention discloses an amplitude-phase corrector parameter design method and system, and belongs to the technical field of flexible direct current transmission, and the method comprises the steps: constructing a flexible direct current system broadband impedance model comprising an alternating current side impedance, a current converter impedance and a direct current side impedance; selecting an amplitude-phase corrector structure and constructing a parameter space of the amplitude-phase corrector structure; establishing a multi-objective optimization function fusing an impedance amplitude error, a phase error, oscillation modal damping and formant suppression; performing automatic optimization in the parameter space by adopting an intelligent optimization algorithm to obtain candidate optimal parameters; carrying out quantitative verification on the parameters to ensure that the impedance is smooth, the stability margin is sufficient, the resonance suppression is effective and the damping reaches the standard; if the verification is passed, outputting final parameters, otherwise, re-optimizing until the requirements are met. According to the method, automation and multi-target collaborative optimization of parameter design of the amplitude-phase corrector are realized, the design efficiency and the broadband oscillation suppression effect are remarkably improved, and safe and stable operation of the flexible direct current system is guaranteed.

The application discloses a frequency divider-free phase-locked loop and a reference double-delay frequency locking method thereof. The sub-sampling phase-locked loop architecture receives an output of an oscillator and feeds back the output to a reference double-delay frequency locking loop. The output end of a reference double-delay generator in the reference double-delay frequency locking loop is electrically connected with the input end of a sample-and-hold circuit, and the output end of the sample-and-hold circuit is electrically connected with the input end of an automatic phase error state detector. The sample-and-hold circuit simultaneously receives an oscillator output feedback signal of the sub-sampling phase-locked loop architecture. The output end of the automatic phase error state detector is electrically connected with the input end of an adaptive output frequency corrector, and the output end of the adaptive output frequency corrector is electrically connected with the sub-sampling phase-locked loop architecture. Unequal double-reference clock delays are introduced, the sample-and-hold circuit is combined to realize the detection of the output frequency, a new frequency locking loop working at a reference frequency is used to replace a traditional frequency locking loop, and the problem of high power consumption caused by a high-frequency frequency divider is solved.

The invention discloses a characteristic higher harmonic low-frequency sampling method, an APF, equipment and a storage medium, belongs to the technical field of power system harmonic detection, and solves the problem of how to reduce the sampling frequency of characteristic higher harmonics. According to the method, the characteristic higher harmonic signal is sampled into the fundamental wave signal by adopting the sampling frequency with lower frequency, so that the amplitude of the characteristic higher harmonic signal is obtained; meanwhile, sampling the characteristic higher harmonic signal into a direct current signal by adopting a second sampling frequency with a relatively low frequency, so as to obtain the phase of the characteristic higher harmonic signal; combining the known angular frequency of the characteristic higher harmonic signal to obtain all characteristics of the characteristic higher harmonic signal; the sampling frequency is reduced to a fraction or even lower than that of a traditional method, and the sampling frequency requirement is remarkably reduced; a high-frequency sampling chip does not need to be upgraded, and system modification cost is reduced; the phase relative error is greatly reduced in a low-order harmonic band, the overall phase error is controlled within 5%, and the phase detection precision is improved.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

The application discloses a full-range error live calibration device and method for a low-voltage current transformer, comprising: a current control unit for outputting full-range calibration current control signals of each frequency; a hetero-frequency calibration current source for outputting full-range hetero-frequency current signals based on the current control signals and injecting the signals into the measured current transformer and a standard current transformer; an open current sensor for measuring a background current signal in real time; a signal decoupling unit for acquiring a mixed-frequency error voltage signal, eliminating a voltage component generated by the background current signal in the mixed-frequency error voltage signal, and acquiring a hetero-frequency error voltage signal; an error measurement unit for calculating ratio error and phase error of the measured current transformer based on the hetero-frequency standard signal and the hetero-frequency error voltage signal; and a data processing unit for determining calibration error under a power frequency frequency mapping based on the ratio error and the phase error under each hetero-frequency frequency.

The application provides a phase precision debugging method, which comprises the following steps: firstly, processing a debugging board and a positive sample plate for each LTCC combined substrate, obtaining initial phase precision of a beam forming matrix through the debugging board, and then designing a surface phase line of the positive sample plate according to the initial phase precision to realize coarse adjustment of the phase precision; secondly, printing the corrected surface phase line on the surface of the positive sample plate; and finally, cutting the debugging phase line on the surface of the positive sample plate to change the path length of the signal, and then to improve the phase precision and realize fine adjustment of the phase precision. As can be seen, the application can concentrate the phase errors of all components in the system by printing the phase line on the surface of the positive sample plate, and then eliminate or reduce the phase errors by debugging the surface printed phase line, so that the operation is simple and convenient, the reliability of the system is not affected, and other devices and circuits are not needed, which can ensure the overall structure of the system unchanged and solve the phase precision problem through debugging.

This invention discloses a method, system, medium, and product for diagnosing high-resistance faults in low-voltage distribution networks, belonging to the field of distribution network fault diagnosis technology. The method first constructs a comprehensive statistical model integrating amplitude and phase errors, time asynchrony errors, and communication packet loss to obtain measurement data with uncertainty; then, it extracts multi-dimensional node features and incorporates uncertainty to construct feature vectors; next, it constructs and trains a Bayesian graph convolutional neural network based on the power grid topology; finally, it outputs the fault probability and cognitive uncertainty, and combines dual thresholds to complete fault determination. This invention can effectively address the measurement uncertainty problem of smart meters, enhance the ability to identify weak features of high-resistance faults, reduce false alarms and missed alarms, and exhibits excellent robustness and diagnostic accuracy under different fault resistance and noise levels.

The invention discloses an all-digital fractional frequency division phase-locked loop based on high-level synthesis and an implementation method thereof, and the phase-locked loop comprises a time-to-digital converter which is implemented based on a register transmission stage and is used for outputting a phase error signal according to an externally input reference clock signal and a feedback clock signal input by a feedback frequency divider; the digital loop filter is realized based on high-level integration and is used for outputting a frequency control word according to the phase error signal; the numerical control oscillator is realized based on the IP core and is used for outputting a digital sine wave signal according to the frequency control word; and the feedback frequency divider is realized based on high-level integration and is used for outputting a feedback clock signal according to the digital sine wave signal. According to the all-digital phase-locked loop, the modules in the all-digital phase-locked loop are strategically divided, high-level synthesis and register transfer level design are strategically combined, the all-digital phase-locked loop which is high in performance and efficiency and can be stably locked is achieved, and the all-digital phase-locked loop can be widely applied to the technical field of digital circuit design.

The application discloses a kind of conformal array rotation interference amplitude-phase error correction design methods, first, construct rotating array signal receiving model, according to the radius of rotating platform and angular velocity calculation rotating guide vector, construct rotating array channel amplitude-phase error model, correction source incident signal information acquisition, record the rotation angle of precision turntable;Covariance matrix is solved to the received data and eigenvalue decomposition, construct amplitude-phase error calculation equation;Solve amplitude-phase error matrix, construct amplitude-phase error correction matrix and correct the received data;Solve adaptive weight vector, and weighted output is carried out to the corrected data.The application compared with traditional array amplitude-phase error correction scheme, system structure is simple and easy to realize, without specific algorithm can be completed to the amplitude-phase error caused by array receiving channel is accurately corrected, effectively solve the receiving channel mismatch problem, improve array anti-interference performance.

This invention discloses a method and system for separating AIS aliasing signals using a four-circular array antenna. The steps are as follows: S100: AIS signals are received through multiple antennas to obtain the spatial baseband signal matrix X, and the phase error Δφ is calculated using interval calculation. k S200: Calculate the phase compensation matrix p; S200: Compensate the baseband signal according to the phase compensation matrix to obtain the baseband signal X. comp S300: For baseband signal X comp By expanding the spatial and temporal dimensions, we obtain the spatiotemporal snapshot matrix X. st (t); S400: The covariance matrix R is obtained by estimating the spatiotemporal snapshot matrix. xx S500: For the covariance matrix R xx Eigenvalue decomposition is performed to obtain the signal subspace and noise subspace; S600: DOA estimation is performed using the MUSIC algorithm to construct the spatial spectrum P(θ); S700: The beam w at the optimal solution is obtained using the space-time constrained minimum variance algorithm; S800: The separated signal is output through the sparse separation method of protocol features. This method can significantly improve the availability of AIS self-organizing network and provide more reliable protection for ship navigation safety.

An event timing-based method and apparatus for fiber-optic frequency transfer are provided, relating to the fields of time-frequency transfer and precision time measurement. According to the method, an event timer is used to detect a time stamp of each rising edge of a radio frequency (RF) signal, which reflects a link delay jitter, a reference time stamp is subtracted from the time stamp to obtain a phase error, and an actuator is driven to compensate the phase error, thereby improving tolerance of a system to link noise while ensuring the stability of optical frequency transfer. Thus, the link delay jitter is suppressed, ensuring that a phase of an output transferred beam remains in long-term stability with a phase of an input reference light.

The application provides an optical signal synchronous calibration device and method of an optical computing system, the device comprising: an optical probe array arranged on a chip, an AI coprocessor, an optical path tuning engine and a low-speed electrical feedback line arranged on a board card; the optical probe array detects optical signals of wavelength channels corresponding to a plurality of optical computing units and converts the optical signals into electrical signals; the AI coprocessor drives the corresponding optical computing unit to emit a detection pulse according to a pre-allocated time slot index variable, extracts a phase error from the electrical signal and calculates a final calibration quantity based on the phase error; the optical path tuning engine performs an optical path tuning operation based on the final calibration quantity to calibrate the error of the corresponding optical computing unit; and the low-speed electrical feedback line transmits the electrical signal to the AI coprocessor and transmits the detection pulse to the chip. The application realizes real-time calibration in a dynamic environment through spatial distributed detection and board-level centralized processing cooperation.

Aspects of the subject disclosure may include, for example, obtaining, from a sampling device of a receiver, samples of a signal that is received from a transmitter, and facilitating acquisition between the receiver and the transmitter by deriving, based on the samples, a phase error output for centering a sampling clock of the sampling device with respect to a transmitter clock, wherein the deriving involves estimating group delay using a detection algorithm that is based on a blind Godard LMS algorithm.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A method for synchronous excitation of multiple exciters relates to the field of dynamic testing and vibration control technology for large civil structures. The method includes the following steps: after constructing a unified time reference based on satellite navigation signals and a rubidium atomic clock, excitation amplitude and phase parameters are obtained based on the target modal requirements, and these parameters are sent to all exciter slave stations; the exciter slave stations generate a reference trajectory based on the excitation amplitude and phase parameters, enabling the exciter motor shaft angle to follow the reference trajectory in real time and output the target excitation; the phase error is obtained based on the measured excitation phase value and the reference trajectory, and then the motor angular velocity of the exciter is corrected based on the phase error. This invention solves the problems of startup phase error and long-term frequency drift in master-slave triggering schemes, ensuring synchronous start-up of all exciters. Combined with dynamic correction of the exciter motor angular velocity, it suppresses phase drift during long-term operation, significantly improving the excitation efficiency of higher-order modes and the clarity of the response signal.

The utility model provides an installation assembly of a phase shifter and an antenna, and relates to the technical field of antennas. The mounting assembly comprises a pair of fixing frames and a first connecting piece, the bottoms of the pair of fixing frames are connected with the reflecting plate, and the fixing frames are used for mounting the phase shifter; the first connecting piece is detachably connected with the tops of the pair of fixing frames. The stability of the phase shifter can be improved, the distance between a pair of phase shifters can be accurately controlled, and the phase error of the phase shifter can be reduced.

This invention discloses a multi-domain joint error correction system for a dual-frequency swarm array, belonging to the field of radar signal processing technology. It obtains correction signals from multiple correction sources through time diversity, with each source transmitting correction signals to the swarm array with a position error exceeding half a wavelength via two carrier frequencies. A simplified SMSSWF method is used to estimate the actual steering vectors of the two carrier frequencies. Based on these steering vectors, the equivalent frequency method is used to calculate the position error, obtaining estimated values ​​for the array element position error parameters. After updating the array element position information using these estimated values, the received signals from the two carrier frequencies are used to estimate the position error, phase error, and communication delay error, respectively, completing the joint error correction for the swarm array with a position error exceeding half a wavelength. The dual-frequency position error estimation based on the equivalent frequency method fully utilizes the large error estimation range of the dual-frequency method while retaining the high accuracy of traditional methods, successfully correcting errors even when the position error exceeds half a wavelength.