The present invention provides a prefetching FIFO circuit, comprising a FIFO controller, a RAM memory, a buffer register group, a buffer controller, an output register group, an output controller, a state machine, a first data selection module, a second data selection module, A first matrix module and a second matrix module. The present invention also provides a data first-in-first-out method, through the control of the state machine, it can selectively decide whether to skip the data in the RAM, and directly store the data in the output register group, which greatly saves the delay of data transmission.