A kind of prefetch fifo circuit and method

Abstract

The present invention provides a prefetching FIFO circuit, comprising a FIFO controller, a RAM memory, a buffer register group, a buffer controller, an output register group, an output controller, a state machine, a first data selection module, a second data selection module, A first matrix module and a second matrix module. The present invention also provides a data first-in-first-out method, through the control of the state machine, it can selectively decide whether to skip the data in the RAM, and directly store the data in the output register group, which greatly saves the delay of data transmission.

Description

technical field [0001] The invention belongs to the field of electronic circuit design, in particular to a prefetch FIFO circuit. Background technique [0002] In the design of logic circuits, FIFO (First_In_First_Out) is one of the most commonly used circuit units. According to the difference of data delay, FIFO can be divided into prefetch FIFO and non-prefetch FIFO, and many complex logic designs need to use prefetch FIFO to meet the requirements of application functions. [0003] A common prefetch FIFO includes a memory storage unit, a FIFO control circuit, and a data prefetch control circuit. After data enters the prefetch FIFO, it is first cached in the memory storage unit, and then the data is read by the FIFO controller and the data prefetch circuit. fetch function. The Memory storage unit is mainly divided into register groups and physical IP units. In ASIC circuit design, register groups are usually used to build storage units only in applications that store a sm...

AI Technical Summary

Problems solved by technology

In the prefetch FIFO design using custom physical memory, due to the circuit characteristics of the memory itself, it takes a long time for the data to enter the prefetch FIFO unit and be read out, which leads to the delay of data transmission in the prefetch FIFO larger

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