1151results about "Data conversion" patented technology

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

The invention discloses a multifunctional analog instrument acquisition card based on a ZYNQ-7000 chip and a data processing method. The acquisition card takes a ZYNQ-7000 series main control chip as a core, a PS end is responsible for data storage and network transmission, and a PL end covers a data acquisition module, a data output module, a data cache module and the like. A four-channel single-channel ADC circuit is adopted for data acquisition, and the data is cached and converted by FIFO and then transmitted to a PS end by DMA; the signal output module generates an analog signal according to an instruction of the upper computer; high-speed and stable data transmission is realized by means of multi-channel DMA; the Ethernet module guarantees communication with an upper computer. By utilizing the unique architecture of the ZYNQ chip and combining the cooperative operation of each functional module, the system has the advantages of modularization, high precision, high-speed processing, expandability and the like, effectively solves many defects of an existing data acquisition system, can be widely applied to analog signal acquisition and processing in multiple fields, improves the efficiency and precision of data acquisition and processing, and has a great market application prospect.

The invention discloses an asynchronous micro-pipeline structure based on a'sending-relaying-receiving 'structure, which comprises an asynchronous control component, the asynchronous control component comprises one or more of a sender (Sender), a relay (Relay), a receiver (Receiver) or a relay permission (PmtRelay), and the Sender comprises a trigger, a phase inverter and a delay module; the Relay is composed of an exclusive-OR gate, an XNOR gate, an AND gate, a D trigger, an inverter and a delay module, and is realized based on a Click asynchronous controller; the Receiver comprises a trigger; according to the PmtRelay, a pmt control mechanism is added in a Click controller; the asynchronous control assembly is one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge and a MutexMerge, and an asynchronous micro pipeline structure is constructed by one or more of the asynchronous control assemblies. According to the asynchronous micro-pipeline structure, fine-grained control is provided, event flow is used for driving control, a unified control chain template is adopted, the design is more direct and simple, the structure pays more attention to delay and generation conditions of event signals, and the design process is more flexible and efficient.

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

The invention relates to the technical field of natural language processing and deep learning, and relates to a self-speculation decoding method and system based on layered quantization KV cache. The method comprises the following steps: performing hierarchical quantization processing on KV cache of a target model, and decomposing original cache data into a high-bit quantization part and a low-bit quantization part; the draft model generates a candidate token sequence based on the KV cache of the high-order quantization part, and stores the candidate token sequence into an asynchronous queue; the target model obtains a candidate token sequence, combines the high-order quantization part and the low-order quantization part into a full-precision cache, and performs parallel verification on the candidate token sequence; and receiving the valid candidate token or regenerating a replacement token by the target model, and updating the hierarchical quantization KV cache. By optimizing the management and quantification strategy of the KV cache, the reasoning process of the large-scale language model is remarkably accelerated, and meanwhile the generation quality is kept.

The invention discloses an SATA (Serial Advanced Technology Attachment) bus system based on an FPGA (Field Programmable Gate Array) and an implementation method thereof, and the SATA bus system comprises a hierarchical protocol processing unit which is used for realizing command analysis, data encapsulation, channel coding and signal conversion functions; the control module is used for receiving a read-write command and read-write parameters sent by the host, and then controlling the hierarchical protocol processing unit to read target data of the storage device according to the read-write command and the read-write parameters, or controlling the hierarchical protocol processing unit to write the target data into the storage device; the command and data processing module is used for caching read-write commands, read-write parameters and upper computer data in FIFO (First In First Out) in a layered manner; and the test data processing module is used for testing whether the storage equipment reads and writes the data normally to obtain a test result. According to the method, the interface design is simple and clear, the delay is low, the data reading and writing function of the storage medium can be tested without intervention of a host or a CPU, and the method can be widely applied to the technical field of serial advanced technology accessory interface control.

The embodiment of the invention discloses an image encoding and decoding method, an encoder, a decoder and a storage medium, and the method comprises the steps: carrying out the unified modification of initial right shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter before the encoder carries out the encoding processing according to an MIP mode; wherein the offset parameter is used for indicating the right shift number of the predicted value; and when coding processing is carried out according to the MIP mode, coding processing is carried out according to the offset parameter. Before the decoder carries out decoding processing according to the MIP mode, initial right shift parameters corresponding to different sizes and different MIP mode numbers are subjected to unified modification according to the offset parameters; wherein the offset parameter is used for indicating the right shift number of the predicted value; and when decoding processing is carried out according to the MIP mode, decoding processing is carried out according to the offset parameter.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

An integrated circuit including a multiplier-accumulator circuit pipeline including a plurality of MAC circuits. Each MAC circuit includes: (A) a multiplier circuit to multiply first input data and filter weight data to generate and output first product data having a floating point data format, and (B) a coarse floating point accumulator circuit including: (1) an alignment shift circuit to shift at least one field of the first product data and generate shifted first product data, and (2) fixed point addition circuitry, coupled to the alignment shift circuit, to add second input data and the shifted first product data using the fixed point addition circuitry. The plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline, in operation, each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.

At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.

A system and method include forecasting a series of future data points in a long sequence time series data using a decoder-only transformer model by dividing the long sequence time series data into a plurality of sequences, converting each sequence of the plurality of sequences into a first vector to obtain a plurality of first vectors, creating a plurality of second vectors from the time stamps associated with the plurality of data points, combining the first vector with the second vector of each sequence of the plurality of sequences to obtain a plurality of third vectors, computing a context matrix from the plurality of third vectors, performing a convolution operation on the context matrix to forecast the series of future data points, and outputting the series of future data points from the prediction layer.

Aspects of the present invention relate to methods and systems for the see-through computer display systems with an extended field of view.

A system may receive, from a client device, a query requesting quality information of a target device. The system may access a set of data records associated with the target device, pre-process the set of data records for extracting raw data associated with the target device from the set of data records, and convert the pre-processed data to normalized data using a first large language model (LLM). The system may apply a second LLM to the normalized data for generating an output result, which includes the requested quality information of the target device. Applying the second LLM may include: retrieving contextual information related to the target device; generating a prompt to the second LLM, the prompt comprising at least the normalized data, the retrieved contextual information, and the query requesting quality information of the target device; and providing the generated prompt to the second LLM to receive the output result.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

Methods, systems, and apparatus for verified quantum phase estimation. In one aspect, a method includes repeatedly performing a experiment. Performing one repetition of the experiment includes: applying a second unitary to a system register of N qubits prepared in a target computational basis state; applying, conditioned on a state of a control qubit, a first unitary to the system register; applying an inverse of the second unitary to the system register and measuring each qubit to determine an output state of the system register; measuring the control qubit to obtain a corresponding measurement result m; and post-selecting on the target computational basis state by, in response to determining that the output state indicates that each qubit was in the target computational basis state prior to measurement, incrementing a first or second classical variable by (−1)m. Phases or expectation values of the first unitary are estimated based on the classical variables.

A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication / accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

The PIO communication device comprises a protocol conversion module and a PIO transaction processing module, the protocol conversion module and the PIO transaction processing module are connected with each other, the protocol conversion module is connected with a computing component connected to a network-on-chip NoC through an AXI interface, and when the computing component initiates a PIO read-write request, the PIO transaction processing module sends the PIO read-write request to the computing component; the protocol conversion module performs conversion of read-write requests between an AXI protocol and a PIO protocol and mapping of response states, and the PIO transaction processing module initiates register access and descriptor writing operation to the network protocol processing component by analyzing the converted PIO read-write requests and receives register read response data returned by the network protocol processing component. According to the invention, a decoupling design of an address channel, a data channel and a response channel is adopted, conversion of a PIO read-write transaction between an AXI interface and a network protocol interface is completed, and high-bandwidth and low-delay non-blocking PIO data transmission and processing are realized.

The invention discloses a fault diagnosis method, system and device based on a first-in first-out strategy and a medium. The method comprises the following steps: dynamically caching cache data of a preset duration according to the first-in first-out strategy through a circular queue; performing wavelet hierarchical compression processing on the cached data to obtain fundamental wave layer data and high-frequency layer data; if the cache data meets a preset condition, feature extraction is carried out on the fundamental wave layer data and the high-frequency layer data, and overload detection features and short circuit detection features are obtained; and inputting the overload detection characteristics and the short circuit detection characteristics into a preset diagnosis model to determine confidence corresponding to each fault type, determining a switch life state based on the switch opening driving signal, and determining a fault diagnosis result based on the confidence corresponding to each fault type and the switch life state. According to the invention, the identification accuracy and efficiency of the transient fault can be improved.

To reduce programming noise for matrix values stored in a memory array for use in an in-array vector-matrix multiplication, such as for a neural network, the matrix is partitioned into a linear combination of matrices that will preserve the output after the combination, with the small value component matrices being normalize to the lager, full range of values before being programmed into the memory arrays. After multiplying each matrix of the combination with the vector by applying a set of bias values, the outputs are rescaled to undo the normalization before adding the individual outputs back together for the final output. This re-scaling causes the effective noise of small weights to be reduced, providing large noise tolerance for these small weight values.

A direct memory access controller (DMAC) includes a virtual channel, a physical channel, and a context manager. The virtual channel is configured to generate a flow control signal for executing a direct memory access (DMA) command. The physical channel includes read and write control logic to initiate data transmission from the source device to the destination device in accordance with the DMA command in response to the flow control signal. In one embodiment, a context manager includes: allocation logic configured to arbitrate between allocation requests from virtual channels and to allocate physical channels to selected virtual channels; and routing logic configured to route a flow control signal from the selected virtual channel to the allocated physical channel, and to route a status signal between the allocated physical channel and the selected virtual channel.

The invention relates to the technical field of data processing, in particular to a remote management system for experimental detection data of a traffic road section, which comprises a state acquisition and occupancy calculation module, a time sequence storage structure, a state acquisition and occupancy calculation module and a state acquisition and occupancy calculation module, the fluctuation characteristic gradient analysis module calculates the difference between the current occupancy rate and the historical occupancy rate to generate a fluctuation degree value, the sampling period dynamic decision module compares the fluctuation value with a threshold value to generate a target sampling interval, and the hardware servo and data packaging module adjusts the scanning frequency and generates a detection data packet. According to the method, a time sequence storage structure is constructed, the traffic flow fluctuation degree is quantified, the sampling interval is intelligently decided according to the fluctuation numerical value, the scanning frequency is adjusted in real time, the frequency is reduced to reduce redundancy when the traffic flow is stable, sampling is encrypted to capture features when fluctuation is violent, the data integrity is guaranteed, and the storage and transmission pressure is reduced. And efficient utilization of monitoring resources is realized.

The invention discloses a floating-point in-memory calculation method and device for simultaneous processing of indexes and mantissas and a storage medium, and belongs to the technical field of in-memory calculation, and the method comprises the steps: obtaining a shared index of a floating-point number in an index calculation array according to sorted index data; according to the sorted mantissa data, mantissa products of the floating-point number in each row of the mantissa calculation array in each calculation period are obtained, and the calculation period number is consistent with the digit of the input mantissa of the floating-point number; respectively shifting each row of mantissa product in each calculation period based on the sharing index; the sum of multiple rows of shift mantissa products under each shift period is obtained, and the shift period number is consistent with the calculation period number; the product accumulation operation result of the floating-point number is obtained according to the sum of multiple rows of shift mantissa products in each shift period, a preprocessing unit for aligning mantissa in advance is reduced, and high efficiency and low communication overhead are realized in a floating-point number MAC task through parallel index addition and mantissa multiplication steps.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

The embodiment of the invention provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip. The butterfly computing unit comprises a first-in first-out cache unit, a butterfly computing module, a multiplier module, a twiddle factor storage module, a first external interface and a second external interface. The first external interface inputs radix-2 or radix-3 FFT data. And the first-in first-out cache unit caches the input data or the data output by the butterfly computing module or the data output by the multiplier module. And the butterfly calculation module receives the data output by the first-in first-out cache unit, and performs butterfly calculation to obtain butterfly calculation result data. And the multiplier module obtains the twiddle factor from the twiddle factor storage module and performs multiplication calculation on the data output by the first-in first-out cache unit or the data output by the butterfly calculation module according to the twiddle factor to obtain multiplication calculation result data. And the second external interface sends out multiplication calculation result data. According to the invention, the structure of the butterfly computing unit is simplified, and the hardware resource consumption is reduced.

The embodiment of the invention discloses an image encoding and decoding method, an encoder, a decoder and a storage medium, and the method comprises the steps: carrying out the unified modification of initial right shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter before the encoder carries out the encoding processing according to an MIP mode; wherein the offset parameter is used for indicating the right shift number of the predicted value; and when coding processing is carried out according to the MIP mode, coding processing is carried out according to the offset parameter. Before the decoder carries out decoding processing according to the MIP mode, initial right shift parameters corresponding to different sizes and different MIP mode numbers are subjected to unified modification according to the offset parameters; wherein the offset parameter is used for indicating the right shift number of the predicted value; and when decoding processing is carried out according to the MIP mode, decoding processing is carried out according to the offset parameter.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

The invention discloses a delay generation method and device of block equipment, a storage system and a storage medium, and relates to the technical field of computer storage. And after a plurality of instructions sent by the host side are received, the plurality of instructions are cached to the starting queue for buffering processing. And regularly executing the logic unit list query instruction by a timer of each thread to obtain a state code. And if the timer of each thread is judged not to recover the configuration according to the state code, triggering the host end to resend the logic unit list query instruction and delay the time for executing a plurality of instructions in the start queue until the timer of each thread is quitted when the configuration of each logic unit is judged to recover according to the latest state code. Regularly judging whether the timer of each thread exits or not by a public service timer; and if it is judged that the logic unit exits, the configuration of each logic unit is recovered. And executing the plurality of instructions in the start queue, so that the host side successfully generates the block device, and the service continuity is not influenced.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

A matrix multiplier includes an input vector scaler configured to generate a scaled input matrix based on a first input matrix and a plurality of scaling factors; a first data type converter configured to convert a data type of the scaled input matrix into a fixed point and generate a fixed point input matrix; a multiply-accumulate operator array configured to receive the fixed-point input matrix and the plurality of binary vectors, generate a fixed-point output matrix based on the fixed-point input matrix and the plurality of binary vectors, generate a first input matrix and a second input matrix, and generate a first output matrix based on the first input matrix and the second input matrix; and a second data type converter configured to convert a data type of the fixed point output matrix into a floating point and generate a second output matrix.