480results about "Data conversion" patented technology

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

The invention discloses a fault diagnosis method, system and device based on a first-in first-out strategy and a medium. The method comprises the following steps: dynamically caching cache data of a preset duration according to the first-in first-out strategy through a circular queue; performing wavelet hierarchical compression processing on the cached data to obtain fundamental wave layer data and high-frequency layer data; if the cache data meets a preset condition, feature extraction is carried out on the fundamental wave layer data and the high-frequency layer data, and overload detection features and short circuit detection features are obtained; and inputting the overload detection characteristics and the short circuit detection characteristics into a preset diagnosis model to determine confidence corresponding to each fault type, determining a switch life state based on the switch opening driving signal, and determining a fault diagnosis result based on the confidence corresponding to each fault type and the switch life state. According to the invention, the identification accuracy and efficiency of the transient fault can be improved.

A direct memory access controller (DMAC) includes a virtual channel, a physical channel, and a context manager. The virtual channel is configured to generate a flow control signal for executing a direct memory access (DMA) command. The physical channel includes read and write control logic to initiate data transmission from the source device to the destination device in accordance with the DMA command in response to the flow control signal. In one embodiment, a context manager includes: allocation logic configured to arbitrate between allocation requests from virtual channels and to allocate physical channels to selected virtual channels; and routing logic configured to route a flow control signal from the selected virtual channel to the allocated physical channel, and to route a status signal between the allocated physical channel and the selected virtual channel.

The invention relates to the technical field of data processing, in particular to a remote management system for experimental detection data of a traffic road section, which comprises a state acquisition and occupancy calculation module, a time sequence storage structure, a state acquisition and occupancy calculation module and a state acquisition and occupancy calculation module, the fluctuation characteristic gradient analysis module calculates the difference between the current occupancy rate and the historical occupancy rate to generate a fluctuation degree value, the sampling period dynamic decision module compares the fluctuation value with a threshold value to generate a target sampling interval, and the hardware servo and data packaging module adjusts the scanning frequency and generates a detection data packet. According to the method, a time sequence storage structure is constructed, the traffic flow fluctuation degree is quantified, the sampling interval is intelligently decided according to the fluctuation numerical value, the scanning frequency is adjusted in real time, the frequency is reduced to reduce redundancy when the traffic flow is stable, sampling is encrypted to capture features when fluctuation is violent, the data integrity is guaranteed, and the storage and transmission pressure is reduced. And efficient utilization of monitoring resources is realized.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

The invention provides a reasoning method, system and device for a generative model and a medium. The method comprises the following steps: acquiring to-be-processed data, and inputting the to-be-processed data into a large language model; for each attention layer, performing the following reasoning: generating a query vector, a key vector and a value vector based on data input to the attention layer, and combining the generated key vector and value vector into a cache block; monitoring cache blocks stored in the cache queue, and when the cache blocks exceed the upper limit of the capacity of the cache space, performing screening based on the correlation score of the query vector and the cache blocks so as to update the cache queue; obtaining an intermediate reasoning result according to the query vector and each cache block in the updated cache queue, and inputting the intermediate reasoning result into the next attention layer for reasoning until a reasoning result generated by the last attention layer of the large language model is obtained and stored; and finally obtaining a generation result of the to-be-processed data. According to the method, the aim of efficiently supporting the infinitely long context can be fulfilled under the condition of limited computing resources.

Certain aspects of the present disclosure provide techniques and apparatus for efficiently performing operations using data compression. An example method generally includes identifying, for a block of data samples, a number of leading bits to remove from each data sample in the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits from each data sample in the block of data samples. A bitstream including the block of compressed data samples and an indication of a type of compression applied to the block of data samples is generated and output for further processing.

The present application relates to the field of accelerators, and discloses an accelerator architecture for near IO pipeline computing, and an AI acceleration system. A multi-channel direct access module comprises N DRAM controllers, and the N DRAM controllers are connected to DRAMs in a one-to-one correspondence; each DRAM controller is at least connected to k DMA controllers, and is connected to a corresponding core group cluster by means of the DMA controllers; a pipeline synchronization ring is connected to N core group clusters and comprises M cascaded forward transmission blocks and M cascaded backward transmission blocks, and the head-end forward transmission block and the tail-end forward transmission block are respectively connected to a data receiving module and a data transmitting module; the output of the tail-end forward transmission block is cascaded to the first backward transmission block; the ith forward transmission block and the (M-i)th backward transmission block correspond to each other in a front-rear direction, and are jointly connected to at least one computing core group. The accelerator of the architecture replaces a traditional multi-level cache structure, reduces the time delay caused multi-layer search, and accelerates the computing rate between the interior of the accelerator and the accelerator.

To provide native hardware support for complex operations such as a beam search operation, an integrated circuit device can be implemented with multiple computational circuit blocks coupled in series to form a pipeline. Each computational circuit block includes an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, a primary result output, and a secondary output. The ALU circuit is programmable to perform an arithmetic operation on the first numeric input and the second numeric input to generate the primary result output, and provide one of the first numeric input or the second numeric input to the secondary output, which is fed back to the ALU circuit.

The invention relates to a processing device and a quantization method for quantization and inverse quantization of numeric data. In one or more aspects, a processing apparatus for numeric data quantization includes processing circuitry to determine a maximum exponent from a set of exponents of a set of digit representations of a set of digits, obtain a set of scaled exponents based on the maximum exponent, and quantize the scaled exponents based on the set of scaled exponents. And one of (i) obtaining a set of quantized significant numbers based on the set of digit representations and a set of mantissas of the set of scaled exponents, or (ii) obtaining a set of quantized mantissas based on the set of mantissas. The processing circuitry is configured to output a set of quantized digit representations of the set of digits based on the set of quantized significant numbers or based on the set of quantized mantissas and the set of scaled exponents; and outputting an offset exponential scaling factor based on the maximum exponent.

Disclosed herein are various techniques for converting a vector from a high precision floating point format to a microscaling (MX) format. An example of a precision floating point format is the FP32 format described above, however, the initial format may be another type of standard floating point format as well (reference to the FP32 number format hereinafter is merely for exemplary purposes and not intended to be limiting). The techniques for converting to the MX-compliant format are improvements over the standard technique suggested in the MX specification by at least accounting for the amount of data in the mantissa of the original precision floating point format to mitigate the amount of data that is lost during the conversion. Therefore, the benefits of representing multiple data points of a vector in the single MX format representation without sacrificing as much of the data contained in the original high precision format that may occur following the standard technique described in the MX specification (portions of which are described below).

The invention provides a logic analyzer trigger point accurate backtracking control method based on hotspot scoring and boundary learning, and the method comprises the steps: carrying out the popularity scoring according to the ratio of the number of channel compression units in each message segment to the length of an occupied byte, and screening out a hotspot candidate set; analyzing the structure of the hot area message segment and decoding, and realizing time alignment of a multi-channel sampling sequence in combination with the position offset adjusting quantity to form a synchronous sampling matrix; calculating local change intensity based on the matrix, introducing an inter-channel jump consistency constraint to construct a jump probability score, and accurately positioning a trigger point time index and a message segment where the trigger point time index is located; and finally, mapping a logic time position into a physical storage address in combination with a compression structure non-balance compensation parameter, so as to realize efficient reverse reading. According to the method, a mark or an additional address table does not need to be inserted, and high-precision backtracking control of the trigger point can be realized under the conditions of high compression ratio and multiple channels.

A method for adjusting audio frequency includes steps of: obtaining initial frequency and temporary data storage of audio data input to a buffering unit; performing a first adjustment procedure on initial frequency to obtain a first variation of temporary data storage corresponding to a first change of initial frequency; calculating a first frequency correction amount according to first variation and a first period of first adjustment procedure; adjusting initial frequency into first frequency according to first frequency correction amount; inputting first frequency into buffering unit; performing a second adjustment procedure on first frequency to obtain a second variation of temporary data storage corresponding to a second change of first frequency; calculating a second frequency correction amount according to second variation and a second period of second adjustment procedure, which first period is less than second period; and adjusting first frequency into target frequency according to second frequency correction amount.

The invention discloses an unmanned aerial vehicle small sample target identification method based on a dynamic graph relation network, and the method comprises the steps: synchronously collecting visible light and infrared images through a multi-modal sensor, carrying out the feature extraction, and generating a unified multi-modal feature through cross-modal attention fusion, and taking the unified multi-modal feature as a support set and query set core feature; constructing a dynamic graph by taking the support set features as nodes, inputting graph convolutional network inference refining features, and generating a category enhancement prototype based on similar refining features; the query set features are matched with the prototypes, and the similarity is calculated through a relation module to complete preliminary recognition; a high-confidence query sample is stored in a circular buffer area, lightweight fine adjustment based on prototype consistency constraint is performed on a related network module in combination with an original training set old sample after verification, online incremental learning of the model is realized, and compared with the prior art, the robustness and precision of unmanned aerial vehicle small sample target recognition can be obviously improved, and the accuracy of target recognition is improved. The problem of catastrophic forgetting in incremental learning is solved, edge computing resource constraints are adapted, and real-time requirements are met.

Disclosed are an image encoding method, an image decoding method, an encoder, a decoder, and a storage medium. Before encoding in accordance with MIP modes, an encoder uniformly modifies initial right shift parameters corresponding to different sizes and different MIP mode numbers according to offset parameters, wherein the offset parameters are used for indicating the right shift digits of predicted values; and during encoding in accordance with MIP modes, performs encoding in accordance with the offset parameters. Before decoding in accordance with MIP modes, a decoder uniformly modifies initial right shift parameters corresponding to different sizes and different MIP mode numbers according to offset parameters, wherein the offset parameters are used for indicating the right shift digits of predicted values; and during decoding in accordance with the MIP modes, performs decoding in accordance with the offset parameters.

The application belongs to the technical field of power line carrier communication, and particularly relates to a baseband chip cache structure read-write control method and a baseband chip cache structure, which comprises the following steps: receiving communication message data and caching the communication message data to multiple bank cache units; if the communication message data is leading data, reading the leading data from the multiple bank cache units until the leading data is read completely; according to the bank sequence number where the read-write pointer of the current multiple bank cache unit accessed is located, dividing the multiple bank cache units into a shared cache module and a circular cache module containing unread communication message data; the circular cache module is used for circularly storing subsequent communication message data; the shared cache module is used for read-write access by external modules; and the shared cache module and the circular cache module are controlled to be read-write accessed respectively. Thus, the application solves the problems of large baseband chip cache memory, large power consumption and poor performance.

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

A neural processing unit for performing inference operations of a large-scale language model based on an artificial neural network is disclosed. The neural processing unit according to the present disclosure includes a processing element core configured to perform an attention mechanism-based operation based on input data in vector format to output an operation result, a special function unit comprising a plurality of arithmetic circuits including at least one vector-dedicated arithmetic circuit that exclusively performs vector operations and at least one mixed arithmetic circuit capable of performing both vector and scalar operations, and configured to perform a special function operation on the operation result, and a controller configured to, upon receiving an RMS normalization operation execution command, activate at least one of the plurality of arithmetic circuits to control the special function unit to perform an operation of converting at least one of the operation result or the input data into a normalized vector whose magnitude is adjusted based on a root mean square (RMS), wherein the operation result may include an attention score for the input data.

The computer-implemented method includes receiving, by a processing unit, an instruction to perform a masked shift-and-add operation with a set of operands. A logical AND operation is performed on a first pair of operands in the set of operands to obtain a first intermediate result. The first intermediate result is shifted by a first shift amount based on a first operand of the first pair of operands. A logical AND operation is performed on a second pair of operands in the set of operands to obtain a second intermediate result. The second intermediate result is shifted by a second shift amount based on the first operand of the second pair of operands. The shifted first intermediate result is added to the shifted second intermediate result. The method further includes outputting an output of the addition as a result of the masked shift-and-add operation.

The invention provides a low-delay real-time analysis architecture and analysis method of a PCIe protocol, belongs to the technical field of integrated circuit chip design, and aims at solving the problems that a traditional software analysis scheme is low in throughput and high in delay, and a special protocol analyzer is high in cost and poor in integration level. The analysis architecture comprises a data preprocessing module, a parallel 8b / 10b decoding module, a parallel descrambling module and an analysis state machine. The analysis method comprises the following steps: S1, data preprocessing; s2, decoding the data in parallel; s3, descrambling the data in parallel; s4, data clock synchronization; and S5, data analysis. According to the method, PCIe 2.0 full protocol stack analysis can be realized, real-time analysis of 5GT / s physical layer, data link layer and transaction layer data is supported, the end-to-end processing delay is only 70 ns, the low delay characteristic enables engineers to observe protocol behaviors in real time and locate data packet errors in time in the debugging process, and the debugging efficiency and accuracy are greatly improved.

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

The invention discloses a hardware architecture of a multi-port memory, and belongs to the technical field of computer memory hardware circuit design. The core comprises a plurality of input ports, a plurality of output ports, a plurality of linked list FIFOs (First In First Out), an input switch internet, a plurality of block memory units, a plurality of reordering queues and an output switch internet, wherein the input port is connected with the block memory unit through the linked list FIFO and the input switch internet, and the block memory unit is connected with the output port through the output switch internet and the reordering queue. By introducing an innovative hardware architecture and a network interconnection architecture, resource consumption is effectively reduced while efficient and large-scale ports are realized, and memory access efficiency and parallel processing capability are improved; the method can be widely applied to high-performance computing, heterogeneous computing, data center acceleration and other application scenes needing high concurrent access and high throughput of a large number of ports, and stable operation of the system can be ensured under the condition of high load.

This invention proposes a superconducting single-flux quantum cross-clock domain communication method and system based on asynchronous FIFO, comprising: initializing the FIFO; an external write circuit inputting a write signal to the FIFO; the FIFO generating a write address and a write flag based on the write signal, and comparing them with the read address and read flag; if the read address and write address are equal, but the write flag and read flag are opposite, the system waits for the external read circuit to read data and generate a new read flag and read address, and then writes the data to be written to the FIFO according to the write address; otherwise, the system writes the data to be written to the FIFO according to the write address. The external read circuit inputs a read signal to the FIFO and generates a read address and read flag, comparing them with the write address and write flag; if the read address and write address are the same, and the read flag and write flag are also the same, the system waits for the external write circuit to write data and generate a new write address and write flag, and then reads the data according to the read address and returns to the external read circuit; otherwise, the system reads the data according to the read address and returns to the external read circuit.

A latency first-in-first-out (FIFO) circuit having a low power dissipation mechanism is provided that includes a counting circuit, FIFO buffers, an input circuit and an output circuit. The counting circuit in turn generates a counting value corresponding to one of reference values in a circular manner. Each of the FIFO buffers corresponds to a corresponding one of the reference values and includes stored data. The input circuit receives and writes the input data to one of the FIFO buffers according to the counting value. The output circuit selects the stored data of one of the FIFO buffers according to the counting value to be outputted as delayed data.

The embodiment of the invention relates to a sound output device and an audio data interruption protection method of the sound output device, which are used for driving loudspeaker equipment. The sound output device comprises a first-in first-out buffer used for receiving and outputting audio data; the buffer circuit is used for temporarily storing the received audio data; and an explosion-proof sound protection device. During normal operation, the explosion-proof sound protection device receives audio data from the buffer circuit and drives loudspeaker equipment. When an underflow notification of the first-in first-out buffer is received, the first-in first-out buffer acquires the last audio data from the buffer circuit and gradually reduces the volume of the audio data so as to avoid the generation of sonic boom. The design can effectively prevent sudden sonic boom caused by audio data interruption, and protect loudspeaking equipment and hearing of a user.