1623results about "Data conversion" patented technology

Systems and methods for efficient convolution based on matrix multiply and add (MMA) are described. An example processor having a plurality of processing lanes is configured to perform convolution of a matrix of activation elements and a filter matrix in accordance with a configurable series of instructions including a plurality of MMA instructions and shift instructions while reusing activation elements already loaded to the datapath or associated memory over a plurality of MMA operations. Associated methods are also described.

The invention provides an in-memory computing AI accelerator design architecture based on an RISC-V architecture and a control method. The architecture comprises an RISC-V processor used for executing a general-purpose computing task and a control instruction; the in-memory computing accelerator is used for executing a computing task in an AI algorithm, is connected with the RISC-V processor and comprises a tensor processing unit and a vector processing unit; the in-memory computing accelerator further comprises a data rearrangement unit which is used for carrying out format conversion and rearrangement on the data before the data are transmitted to the tensor processing unit or the vector processing unit. And the data format management unit is used for defining and managing a unified data format in the in-memory computing accelerator. According to the invention, the calculation performance and the resource utilization rate of the AI algorithm can be improved, and meanwhile, the accuracy of data transmission and the parallelism of processing are ensured.

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

Provided is a direct memory access architecture, including: a direct memory access control component, a read data moving component, a write data moving component and a data storage component; wherein the direct memory access control component includes a control register, a read descriptor storage component, a write descriptor storage component, a read command transfer component and a write command transfer component; the control register is configured to obtain descriptor address information; the read descriptor storage component is configured to store a read descriptor obtained by using the control register; the write descriptor storage component is configured to store a write descriptor obtained by using the control register; the read command transfer component is configured to send, to the read data moving component, a read command; the write command transfer component is configured to send, to the write data moving component, a write command.

The invention discloses a multifunctional analog instrument acquisition card based on a ZYNQ-7000 chip and a data processing method. The acquisition card takes a ZYNQ-7000 series main control chip as a core, a PS end is responsible for data storage and network transmission, and a PL end covers a data acquisition module, a data output module, a data cache module and the like. A four-channel single-channel ADC circuit is adopted for data acquisition, and the data is cached and converted by FIFO and then transmitted to a PS end by DMA; the signal output module generates an analog signal according to an instruction of the upper computer; high-speed and stable data transmission is realized by means of multi-channel DMA; the Ethernet module guarantees communication with an upper computer. By utilizing the unique architecture of the ZYNQ chip and combining the cooperative operation of each functional module, the system has the advantages of modularization, high precision, high-speed processing, expandability and the like, effectively solves many defects of an existing data acquisition system, can be widely applied to analog signal acquisition and processing in multiple fields, improves the efficiency and precision of data acquisition and processing, and has a great market application prospect.

The present application relates to the technical field of integrated circuits, relates to a computing-in-memory circuit based on BNN algorithm acceleration, and solves the problems in the prior art of a large circuit area, high energy consumption, and low energy efficiency of computing-in-memory. The circuit comprises: selecting a first algorithm network and a second algorithm network from a flexible RRAM storage array; inputting a plurality of rows of data into the first algorithm network and a multiply-accumulate module to obtain a multiply-accumulate result, and inputting the multiply-accumulate result into a shifter; the shifter shifting the multiply-accumulate result, outputting the shifting result to an adder-subtractor to obtain a sum-calculation result and outputting the sum-calculation result to a comparator; the comparator performing binarization on the sum-calculation result, outputting the binarized sum-calculation result to a second algorithm network, performing recalculation to output a column accumulate current, and sending the column accumulate current to a maximum value comparator output module; and the maximum value comparator output module determining a column having the maximum column sum as a classification result. While keeping the original network precision, the required circuit area is greatly reduced, the energy consumption is reduced, and the energy efficiency of the entire computing-in-memory circuit is improved.

The invention discloses an asynchronous micro-pipeline structure based on a'sending-relaying-receiving 'structure, which comprises an asynchronous control component, the asynchronous control component comprises one or more of a sender (Sender), a relay (Relay), a receiver (Receiver) or a relay permission (PmtRelay), and the Sender comprises a trigger, a phase inverter and a delay module; the Relay is composed of an exclusive-OR gate, an XNOR gate, an AND gate, a D trigger, an inverter and a delay module, and is realized based on a Click asynchronous controller; the Receiver comprises a trigger; according to the PmtRelay, a pmt control mechanism is added in a Click controller; the asynchronous control assembly is one of a Fifo, a PmtFifo, a Selector, a Splitter, a WaitMerge and a MutexMerge, and an asynchronous micro pipeline structure is constructed by one or more of the asynchronous control assemblies. According to the asynchronous micro-pipeline structure, fine-grained control is provided, event flow is used for driving control, a unified control chain template is adopted, the design is more direct and simple, the structure pays more attention to delay and generation conditions of event signals, and the design process is more flexible and efficient.

The provided is a stream processing-based non-blocking oriented FAST and rotated BRIEF (ORB) feature extraction accelerator implemented by a field programmable gate array (FPGA), which mainly includes two innovations: A stream processing-based non-blocking hardware architecture and a cache management algorithm are provided. The accelerator precisely controls and buffers each column of an rBRIEF descriptor computation window by using an algorithm, allowing to receive a new input pixel stream while computing a descriptor, thereby achieving non-blocking processing. An efficient hardware sorting design embedded in an accelerator is provided. Based on a count sorting algorithm, minimal resources are used to implement rBRIEF sorting on hardware, and the rBRIEF sorting is embedded in the accelerator. The accelerator ensures quality of a feature point while achieving high-speed feature point extraction, without significantly reducing accuracy of ORB_SLAM and other algorithms.

A disclosed approximate tensor processing unit (APTPU) includes two main components: (1) approximate processing elements (APEs) consisting of a low-precision multiplier and an approximate adder, and (2) pre-approximate units (PAUs) which are shared among the APEs in the APTPU's systolic array, functioning as the steering logic to pre-process the operands and feed them to the APEs. Performance of the disclosed APTPU across various configurations and various workloads shows that the disclosed APTPU's systolic array achieves delay, area, and power reductions, while realizing comparable accuracy to previous designs.

The invention discloses a chip internal signal observation circuit and system, and the observation circuit comprises a signal selection module which is connected with a plurality of to-be-tested modules disposed in a target chip, and is used for selecting signals of to-be-observed modules in the plurality of to-be-tested modules, and synthesizing and outputting the signals; the sampling module is connected with the signal selection module and is used for sampling the signal synthesized and output by the signal selection module and writing the signal into an FIFO cache module; the FIFO cache module is used for caching the signals sampled by the sampling module; and the main equipment module is connected with the FIFO cache module, is connected with each memory through a bus, and is used for reading the sampled signals from the FIFO cache module and writing the sampled signals into the corresponding memories for signal observation.

Techniques for noise and bound management for DNN training on RPU crossbar arrays using a scaling factor based on a worst-case scenario are provided. In one aspect, a method for noise and bound management includes: obtaining input vector values x for an analog crossbar array of RPU devices, wherein a weight matrix is mapped to the analog crossbar array of RPU devices; and scaling the input vector values x based on a worst-case scenario to provide scaled input vector values x′ to use as input to the analog crossbar array of RPU devices, wherein the worst-case scenario includes an assumed maximal weight of the weight matrix multiplied by a sum of absolute values from the input vector values x.

A communication interface circuit supporting a communication link change and a method of operating the same, the communication interface circuit including: a protocol layer circuit generating packet data based on input data; and a physical layer circuit that encodes the packet data to output a transmission state, and drives a data channel including a plurality of three-phase line links based on the transmission state, where the physical layer circuit may include an encoder that encodes the packet data to output the transmission state. The encoder calculates a transmission state based on a preorder state output from the encoder within a previous unit interval, a symbol mapped to the packet data, and a control code, and wherein the control code indicates a coding change based on a coupling relationship of the plurality of three-phase line links. A communication interface circuit stably transmits data.

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

The invention relates to a data transmission method and system, electronic equipment and a storage medium, the method is applied to a master node, the master node corresponds to a plurality of slave nodes, the master node comprises a counter corresponding to each slave node, and a numerical value in the counter corresponding to each slave node is used for indicating the data receiving capability of the slave node; the method comprises the following steps: for any slave node, under the conditions that a numerical value in a counter corresponding to the slave node is not 0 and data needing to be sent to the slave node is prepared, determining the slave node as a first slave node, and generating an effective signal corresponding to the first slave node; under the condition that the plurality of first slave nodes exist, selecting one of the plurality of first slave nodes to be determined as a second slave node; and sending data to the second slave node. According to the embodiment of the invention, the condition that the slave node without the data receiving capability blocks the pipeline channel can be effectively avoided.

The invention relates to the technical field of natural language processing and deep learning, and relates to a self-speculation decoding method and system based on layered quantization KV cache. The method comprises the following steps: performing hierarchical quantization processing on KV cache of a target model, and decomposing original cache data into a high-bit quantization part and a low-bit quantization part; the draft model generates a candidate token sequence based on the KV cache of the high-order quantization part, and stores the candidate token sequence into an asynchronous queue; the target model obtains a candidate token sequence, combines the high-order quantization part and the low-order quantization part into a full-precision cache, and performs parallel verification on the candidate token sequence; and receiving the valid candidate token or regenerating a replacement token by the target model, and updating the hierarchical quantization KV cache. By optimizing the management and quantification strategy of the KV cache, the reasoning process of the large-scale language model is remarkably accelerated, and meanwhile the generation quality is kept.

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Methods and apparatus employ an asynchronous first-in-first-out buffer (FIFO), that includes a plurality of entries. Control logic determines a timing separation between a write header valid signal and corresponding write data valid signal for a write operation to an entry in the first-in-first-out buffer (FIFO) and performs a read of the corresponding data from the entry in the FIFO in the second clock domain, based on the determined timing separation of the write header valid signal and corresponding write data valid signal, and based on a clock frequency ratio between the first and second clock domains.

The invention relates to the technical field of chip verification, in particular to a chip joint simulation method and device based on a multi-processing-module interface and a medium, and the method comprises the steps: S1, inputting the same test case to a to-be-tested chip design and simulation model at the same time; s2, determining an output sequence Yi of a multi-processing module of Di through arbitration in the design of the chip to be tested, and transmitting the output sequence Yi to Ci; s3, the simulation model outputs data from the Ci according to the Yi, and the data are sequentially stored in the Qi; s4, the chip design to be tested outputs data from the Di according to the Yi, the data DAi output by the Di is obtained in real time, and the CAi is read from the Qi; and S5, comparing the DAi with the CAi, if all the DAi is equal to the CAi, circularly executing the steps S1 to S5, and if the DAi is not equal to the CAi, ending joint simulation and generating chip verification failure prompt information. The chip verification efficiency is improved, and the chip verification cost is reduced.

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

The invention discloses an SATA (Serial Advanced Technology Attachment) bus system based on an FPGA (Field Programmable Gate Array) and an implementation method thereof, and the SATA bus system comprises a hierarchical protocol processing unit which is used for realizing command analysis, data encapsulation, channel coding and signal conversion functions; the control module is used for receiving a read-write command and read-write parameters sent by the host, and then controlling the hierarchical protocol processing unit to read target data of the storage device according to the read-write command and the read-write parameters, or controlling the hierarchical protocol processing unit to write the target data into the storage device; the command and data processing module is used for caching read-write commands, read-write parameters and upper computer data in FIFO (First In First Out) in a layered manner; and the test data processing module is used for testing whether the storage equipment reads and writes the data normally to obtain a test result. According to the method, the interface design is simple and clear, the delay is low, the data reading and writing function of the storage medium can be tested without intervention of a host or a CPU, and the method can be widely applied to the technical field of serial advanced technology accessory interface control.

The embodiment of the invention provides a number-theory transformation processing device based on a post-quantum encryption algorithm. The device comprises a control unit, a ping-pong storage unit, a butterfly unit and a nonvolatile storage unit, the control unit is used for receiving the polynomial of the post-quantum encryption algorithm, splitting the polynomial into coefficients and writing the coefficients into the ping-pong storage unit; writing a preset twiddle factor into the nonvolatile storage unit; and calling the ping-pong storage unit and the nonvolatile storage unit to read and write data according to a preset processing flow of the post-quantum encryption algorithm, and calling the butterfly unit to calculate. According to the embodiment of the invention, the polynomial is split into coefficients through the control unit, the ping-pong storage unit and the nonvolatile storage unit are called to read and write data according to the preset processing flow of the post-quantum encryption algorithm, and the butterfly unit is called to calculate, so that the running speed of the algorithm on hardware is optimized; and meanwhile, the performance of the post-quantum encryption algorithm can be greatly improved.

The embodiment of the invention discloses an image encoding and decoding method, an encoder, a decoder and a storage medium, and the method comprises the steps: carrying out the unified modification of initial right shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter before the encoder carries out the encoding processing according to an MIP mode; wherein the offset parameter is used for indicating the right shift number of the predicted value; and when coding processing is carried out according to the MIP mode, coding processing is carried out according to the offset parameter. Before the decoder carries out decoding processing according to the MIP mode, initial right shift parameters corresponding to different sizes and different MIP mode numbers are subjected to unified modification according to the offset parameters; wherein the offset parameter is used for indicating the right shift number of the predicted value; and when decoding processing is carried out according to the MIP mode, decoding processing is carried out according to the offset parameter.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the second cyclic buffer will survive and be accessible.

The invention discloses an energy storage system and a data storage method, and relates to the technical field of energy storage. The energy storage system comprises a battery pack, a data collector, a memory and a controller. The data collector is connected with a plurality of batteries in the battery pack through a bus, the data collector is used for collecting operation data of the battery pack, the operation data comprises data streams of M dimensions, and M is a positive integer. The memory includes a volatile memory device and a non-volatile memory device, the volatile memory device including a cache and M first-in first-out buffers. The controller is electrically connected with the data acquisition unit and the memory, and is used for acquiring data streams of M dimensions, writing the data streams of M dimensions into the M first-in first-out buffers frame by frame, reading target data streams stored in the first-in first-out buffers to the cache when the data streams stored in the first-in first-out buffers meet storage conditions, and storing the target data streams in the memory. And writing the target data set stored in the cache into the nonvolatile memory device.

An integrated circuit including a multiplier-accumulator circuit pipeline including a plurality of MAC circuits. Each MAC circuit includes: (A) a multiplier circuit to multiply first input data and filter weight data to generate and output first product data having a floating point data format, and (B) a coarse floating point accumulator circuit including: (1) an alignment shift circuit to shift at least one field of the first product data and generate shifted first product data, and (2) fixed point addition circuitry, coupled to the alignment shift circuit, to add second input data and the shifted first product data using the fixed point addition circuitry. The plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline, in operation, each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.

At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.

The invention provides a multi-channel DMA data processing method and electronic equipment, and the method comprises the steps: distributing a plurality of channels of DMA to a domain of a multi-core heterogeneous system according to a preset distribution principle, and carrying out the configuration of the plurality of channels; configuring a first parameter corresponding to each domain for each domain, and mapping the authority of each domain to the external access of the DMA through the respective first parameter; updating the first data information of the DMA in response to the requirement of the DMA for realizing function change; and based on the updated first data information, the computer processor transmits the to-be-transmitted data according to a corresponding channel through a simplified instruction of the DMA. The scheme that multiple domains share the DMA in one chip is achieved, and consistent authority control is guaranteed. According to the method, the configuration information of the DMA is updated according to the change of the functions required to be realized by the DMA, so that the external functions of the DMA are upgraded while the DMA can flexibly and quickly complete the unloading function.