807results about "Data conversion" patented technology

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

A fused dot-product multiply-accumulate (MAC) circuit may support variable precision of floating-point data elements to perform computations in deep learning operations (e.g., MAC operations). The operating mode of the circuit may be selected based on the accuracy of the input element. The mode of operation may be an FP16 mode or an FP8 mode. In the FP8 mode, a product index may be calculated based on an index of a floating point input element. A maximum index may be selected from the one or more product indexes. A global maximum index may be selected from a plurality of maximum indexes. A product mantissa may be calculated based on a difference between the global maximum exponent and a corresponding maximum exponent and aligned with another product mantissa. The adder tree may accumulate the aligned product mantissas and compute the partial and mantissas. The portions and mantissas may be normalized using a global maximum index.

The invention discloses an SATA (Serial Advanced Technology Attachment) bus system based on an FPGA (Field Programmable Gate Array) and an implementation method thereof, and the SATA bus system comprises a hierarchical protocol processing unit which is used for realizing command analysis, data encapsulation, channel coding and signal conversion functions; the control module is used for receiving a read-write command and read-write parameters sent by the host, and then controlling the hierarchical protocol processing unit to read target data of the storage device according to the read-write command and the read-write parameters, or controlling the hierarchical protocol processing unit to write the target data into the storage device; the command and data processing module is used for caching read-write commands, read-write parameters and upper computer data in FIFO (First In First Out) in a layered manner; and the test data processing module is used for testing whether the storage equipment reads and writes the data normally to obtain a test result. According to the method, the interface design is simple and clear, the delay is low, the data reading and writing function of the storage medium can be tested without intervention of a host or a CPU, and the method can be widely applied to the technical field of serial advanced technology accessory interface control.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

A system may receive, from a client device, a query requesting quality information of a target device. The system may access a set of data records associated with the target device, pre-process the set of data records for extracting raw data associated with the target device from the set of data records, and convert the pre-processed data to normalized data using a first large language model (LLM). The system may apply a second LLM to the normalized data for generating an output result, which includes the requested quality information of the target device. Applying the second LLM may include: retrieving contextual information related to the target device; generating a prompt to the second LLM, the prompt comprising at least the normalized data, the retrieved contextual information, and the query requesting quality information of the target device; and providing the generated prompt to the second LLM to receive the output result.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

Methods, systems, and apparatus for verified quantum phase estimation. In one aspect, a method includes repeatedly performing a experiment. Performing one repetition of the experiment includes: applying a second unitary to a system register of N qubits prepared in a target computational basis state; applying, conditioned on a state of a control qubit, a first unitary to the system register; applying an inverse of the second unitary to the system register and measuring each qubit to determine an output state of the system register; measuring the control qubit to obtain a corresponding measurement result m; and post-selecting on the target computational basis state by, in response to determining that the output state indicates that each qubit was in the target computational basis state prior to measurement, incrementing a first or second classical variable by (−1)m. Phases or expectation values of the first unitary are estimated based on the classical variables.

The PIO communication device comprises a protocol conversion module and a PIO transaction processing module, the protocol conversion module and the PIO transaction processing module are connected with each other, the protocol conversion module is connected with a computing component connected to a network-on-chip NoC through an AXI interface, and when the computing component initiates a PIO read-write request, the PIO transaction processing module sends the PIO read-write request to the computing component; the protocol conversion module performs conversion of read-write requests between an AXI protocol and a PIO protocol and mapping of response states, and the PIO transaction processing module initiates register access and descriptor writing operation to the network protocol processing component by analyzing the converted PIO read-write requests and receives register read response data returned by the network protocol processing component. According to the invention, a decoupling design of an address channel, a data channel and a response channel is adopted, conversion of a PIO read-write transaction between an AXI interface and a network protocol interface is completed, and high-bandwidth and low-delay non-blocking PIO data transmission and processing are realized.

The invention discloses a fault diagnosis method, system and device based on a first-in first-out strategy and a medium. The method comprises the following steps: dynamically caching cache data of a preset duration according to the first-in first-out strategy through a circular queue; performing wavelet hierarchical compression processing on the cached data to obtain fundamental wave layer data and high-frequency layer data; if the cache data meets a preset condition, feature extraction is carried out on the fundamental wave layer data and the high-frequency layer data, and overload detection features and short circuit detection features are obtained; and inputting the overload detection characteristics and the short circuit detection characteristics into a preset diagnosis model to determine confidence corresponding to each fault type, determining a switch life state based on the switch opening driving signal, and determining a fault diagnosis result based on the confidence corresponding to each fault type and the switch life state. According to the invention, the identification accuracy and efficiency of the transient fault can be improved.

To reduce programming noise for matrix values stored in a memory array for use in an in-array vector-matrix multiplication, such as for a neural network, the matrix is partitioned into a linear combination of matrices that will preserve the output after the combination, with the small value component matrices being normalize to the lager, full range of values before being programmed into the memory arrays. After multiplying each matrix of the combination with the vector by applying a set of bias values, the outputs are rescaled to undo the normalization before adding the individual outputs back together for the final output. This re-scaling causes the effective noise of small weights to be reduced, providing large noise tolerance for these small weight values.

A direct memory access controller (DMAC) includes a virtual channel, a physical channel, and a context manager. The virtual channel is configured to generate a flow control signal for executing a direct memory access (DMA) command. The physical channel includes read and write control logic to initiate data transmission from the source device to the destination device in accordance with the DMA command in response to the flow control signal. In one embodiment, a context manager includes: allocation logic configured to arbitrate between allocation requests from virtual channels and to allocate physical channels to selected virtual channels; and routing logic configured to route a flow control signal from the selected virtual channel to the allocated physical channel, and to route a status signal between the allocated physical channel and the selected virtual channel.

The invention relates to the technical field of data processing, in particular to a remote management system for experimental detection data of a traffic road section, which comprises a state acquisition and occupancy calculation module, a time sequence storage structure, a state acquisition and occupancy calculation module and a state acquisition and occupancy calculation module, the fluctuation characteristic gradient analysis module calculates the difference between the current occupancy rate and the historical occupancy rate to generate a fluctuation degree value, the sampling period dynamic decision module compares the fluctuation value with a threshold value to generate a target sampling interval, and the hardware servo and data packaging module adjusts the scanning frequency and generates a detection data packet. According to the method, a time sequence storage structure is constructed, the traffic flow fluctuation degree is quantified, the sampling interval is intelligently decided according to the fluctuation numerical value, the scanning frequency is adjusted in real time, the frequency is reduced to reduce redundancy when the traffic flow is stable, sampling is encrypted to capture features when fluctuation is violent, the data integrity is guaranteed, and the storage and transmission pressure is reduced. And efficient utilization of monitoring resources is realized.

The invention discloses a floating-point in-memory calculation method and device for simultaneous processing of indexes and mantissas and a storage medium, and belongs to the technical field of in-memory calculation, and the method comprises the steps: obtaining a shared index of a floating-point number in an index calculation array according to sorted index data; according to the sorted mantissa data, mantissa products of the floating-point number in each row of the mantissa calculation array in each calculation period are obtained, and the calculation period number is consistent with the digit of the input mantissa of the floating-point number; respectively shifting each row of mantissa product in each calculation period based on the sharing index; the sum of multiple rows of shift mantissa products under each shift period is obtained, and the shift period number is consistent with the calculation period number; the product accumulation operation result of the floating-point number is obtained according to the sum of multiple rows of shift mantissa products in each shift period, a preprocessing unit for aligning mantissa in advance is reduced, and high efficiency and low communication overhead are realized in a floating-point number MAC task through parallel index addition and mantissa multiplication steps.

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

To provide an image codec method, an image decode method and a decoder for effectively improving the efficiency of a codec.SOLUTION: Before performing the coding processing according to the MIP mode, the encoder performs a correction to unify initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to an offset parameter for indicating the number of right-shift bits of the predicted value, and when performing the coding processing according to the MIP mode, the encoder performs the coding processing according to the offset parameter. The decoder may perform a correction to unify the initial right-shift parameters corresponding to different sizes and different MIP mode numbers according to the offset parameter before performing the decoding process according to the MIP mode, and perform the decoding process according to the offset parameter when performing the decoding process according to the MIP mode.SELECTED DRAWING: Figure 7

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

A matrix multiplier includes an input vector scaler configured to generate a scaled input matrix based on a first input matrix and a plurality of scaling factors; a first data type converter configured to convert a data type of the scaled input matrix into a fixed point and generate a fixed point input matrix; a multiply-accumulate operator array configured to receive the fixed-point input matrix and the plurality of binary vectors, generate a fixed-point output matrix based on the fixed-point input matrix and the plurality of binary vectors, generate a first input matrix and a second input matrix, and generate a first output matrix based on the first input matrix and the second input matrix; and a second data type converter configured to convert a data type of the fixed point output matrix into a floating point and generate a second output matrix.

In accordance with the present disclosure, an apparatus is provided. The apparatus includes: a first memory having a first capacity configured to store a first generative neural network model including a first parameter; and a first neural processing unit configured to generate a response corresponding to the input query using the first generative neural network model stored in the first memory; and wherein the first neural processing unit may be configured to store first execution code of the first generative neural network model, the first execution code being compiled to process the speculative decoding.

The invention provides a reasoning method, system and device for a generative model and a medium. The method comprises the following steps: acquiring to-be-processed data, and inputting the to-be-processed data into a large language model; for each attention layer, performing the following reasoning: generating a query vector, a key vector and a value vector based on data input to the attention layer, and combining the generated key vector and value vector into a cache block; monitoring cache blocks stored in the cache queue, and when the cache blocks exceed the upper limit of the capacity of the cache space, performing screening based on the correlation score of the query vector and the cache blocks so as to update the cache queue; obtaining an intermediate reasoning result according to the query vector and each cache block in the updated cache queue, and inputting the intermediate reasoning result into the next attention layer for reasoning until a reasoning result generated by the last attention layer of the large language model is obtained and stored; and finally obtaining a generation result of the to-be-processed data. According to the method, the aim of efficiently supporting the infinitely long context can be fulfilled under the condition of limited computing resources.

Certain aspects of the present disclosure provide techniques and apparatus for efficiently performing operations using data compression. An example method generally includes identifying, for a block of data samples, a number of leading bits to remove from each data sample in the block of data samples. A block of compressed data samples is generated based on the identified number of leading bits and truncation of a number of least significant bits from each data sample in the block of data samples. A bitstream including the block of compressed data samples and an indication of a type of compression applied to the block of data samples is generated and output for further processing.

The present application relates to the field of accelerators, and discloses an accelerator architecture for near IO pipeline computing, and an AI acceleration system. A multi-channel direct access module comprises N DRAM controllers, and the N DRAM controllers are connected to DRAMs in a one-to-one correspondence; each DRAM controller is at least connected to k DMA controllers, and is connected to a corresponding core group cluster by means of the DMA controllers; a pipeline synchronization ring is connected to N core group clusters and comprises M cascaded forward transmission blocks and M cascaded backward transmission blocks, and the head-end forward transmission block and the tail-end forward transmission block are respectively connected to a data receiving module and a data transmitting module; the output of the tail-end forward transmission block is cascaded to the first backward transmission block; the ith forward transmission block and the (M-i)th backward transmission block correspond to each other in a front-rear direction, and are jointly connected to at least one computing core group. The accelerator of the architecture replaces a traditional multi-level cache structure, reduces the time delay caused multi-layer search, and accelerates the computing rate between the interior of the accelerator and the accelerator.

The invention discloses a data transmission system and host equipment, and relates to the technical field of communication, and the system comprises a direct storage access module and a preset first-in first-out queue; wherein the direct storage access module is connected with a preset communication bus through the preset first-in first-out queue; the direct storage access module is used for receiving a read-write control command of the central processing unit; performing security detection on the read-write control command to obtain a security detection result; if the security detection result is that the detection is passed, interacting with the preset communication bus by utilizing a target queue in a preset first-in first-out queue, and processing the read-write control command; according to the invention, DMA data transmission between the CPU and the preset communication bus can be realized, the data transmission speed of the host equipment through the communication bus is accelerated, the working efficiency of the CPU is improved, the overall performance of the system is further improved, and the transmission stability of the system is ensured.

The invention discloses a system-on-chip supporting data communication and a data communication method and equipment, and relates to the technical field of controller local area networks. The system comprises a data buffer, a direct memory access controller and a processor; the data buffer is used for generating a starting signal in response to the received first data frame; the direct memory access controller is used for reading a current descriptor in a plurality of descriptors from a descriptor memory area of the memory in response to the starting signal; reading the first data frame from the data buffer area according to the current descriptor, and writing the first data frame into the data buffer area of the memory; in response to the fact that the first interrupt is in the enabled state, generating a first interrupt signal after the first data frame is written into the data buffer area; and the processor is used for reading the first data frame from the data buffer area in response to the first interrupt signal. The system can solve the overflow problem of the data buffer in a high-load scene, reduces the risk of data frame loss, and improves the real-time performance and reliability of the system.

The invention discloses a design method, device and equipment of a many-core processor architecture and a storage medium, and relates to the technical field of distributed computing. Comprising the steps of 1, dividing all cores into groups, 2, integrating a CPU assembly line, an intra-core private memory, a hardware FIFO queue and a DMA engine in each core, 3, labeling the cores in each group according to coordinates, storing shared data of processors in the group by using an intra-group shared memory, and storing the shared data of the processors in the group. The method comprises the following steps: step 1, transmitting and receiving an NoC data packet through an intra-group main core control inter-group communication interface for intra-group communication, and step 4, planning an inter-group optimal transmission path for inter-group communication according to the transmitted core coordinates of a source processor group and a target processor group. According to the method, the shortest path between the groups is automatically calculated, and NoC transmission is dynamically optimized; hardware FIFO and a DMA engine are adopted to realize low-delay data transmission, and a main core efficiently exchanges data among groups through an NoC to realize response.

The invention provides an FIFO (First In First Out) data reading method, device, system, equipment and medium, the method comprises the following steps: when a data reading request is triggered, calculating a read address according to a data reading address carried in the data reading request; the read address is used for representing a value when the read address register is about to be updated in the previous clock period; selecting target data from the next beat of data of the register file or the beat-to-write data through the multiplexer according to the beat-to-read address; the next beat of data of the register file refers to data stored in the register file in the next clock period; the current data are data which are currently written into a first-in first-out (FIFO) queue; and performing a beating operation on the target data through a register, and performing a reading operation through a data reading interface of the FIFO queue. According to the scheme, the overall delay of data reading is reduced, the running speed and performance of the whole system are improved, and then the running speed of a chip is increased.

Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units. The multicore processor also includes a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network-on-chip layer.

Picture coding and decoding methods, an encoder, a decoder and a storage medium are provided. The encoder, before performing coding processing according to a matrix-based intra prediction (MIP) mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing coding processing according to the MIP mode, performs coding processing according to the offset parameter. The decoder, before performing decoding processing according to an MIP mode, sets initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, the offset parameter indicating a number of right shifting bits of a predicted value, and when performing decoding processing according to the MIP mode, performs decoding processing according to the offset parameter.

According to the present disclosure, a device is provided. The device includes a first memory of a first capacity configured to store a first generative neural network model comprising a first parameters, and a first neural processing unit configured to generate a response corresponding to an input query utilizing the first generative neural network model stored in the first memory, and wherein the first neural processing unit may be configured to store a first execution code of the first generative neural network model compiled to process speculative decoding.

To provide native hardware support for complex operations such as a beam search operation, an integrated circuit device can be implemented with multiple computational circuit blocks coupled in series to form a pipeline. Each computational circuit block includes an arithmetic logic unit (ALU) circuit having a first numeric input, a second numeric input, a primary result output, and a secondary output. The ALU circuit is programmable to perform an arithmetic operation on the first numeric input and the second numeric input to generate the primary result output, and provide one of the first numeric input or the second numeric input to the secondary output, which is fed back to the ALU circuit.