52 results about "Instruction buffer" patented technology

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux to disconnect an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

A single-instruction multi-thread processor micro-architecture device oriented to neural network parallel scheduling comprises a front-end instruction fetching module, an instruction cache module, a decoding module, an arithmetic logic operation unit, a multiplication and division module, a memory access unit and a data cache module, and the micro-architecture device allocates a unique thread number for each thread. Threads are organized into thread groups, and in each period, the fair alternate arbiter selects an instruction from an instruction buffer of the thread group and sends the instruction to a subsequent decoding stage. The micro-architecture not only solves challenges faced by end-side equipment when processing high-performance calculation requirements such as neural network reasoning, but also provides an effective solution capable of reducing energy consumption and improving calculation efficiency through an innovative architecture design. The method is of great significance in promoting development of end-side AI application.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

The invention belongs to the technical field of chip testing, and discloses a testing device and method for an RISC-V chip instruction cache, and the device comprises a CPU core, a cache controller, a user-defined instruction execution module, and an instruction cache. The CPU core is used for receiving a test starting address and a test ending address; sending a clearing instruction to the instruction buffer; and executing a test step: generating an instruction reading address according to the test starting address, sending the instruction reading address to the cache controller until a test ending address, receiving a test instruction of the cache controller, judging whether the test instruction is a self-defined instruction, and if so, sending the test instruction to a self-defined instruction execution module to obtain an instruction execution result; and executing the test step again, and obtaining an instruction cache test result according to an obtained instruction execution result. The RISC-V chip instruction buffer test method and the RISC-V chip instruction buffer test device can realize comprehensive test of the RISC-V chip instruction buffer under the condition of avoiding increasing a large amount of chip cost area.

Embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and related devices and methods. The present solution is applicable to various chips including CISC instruction set, RISC reduced instruction set (especially RISC-V instruction set), or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips, etc. The instruction retirement unit includes a receiving subunit configured to receive a completion request signal; an arbitration subunit configured to, after determining that a to-be-completed instruction can be completed, send a completion permission signal to an instruction execution unit, and store instruction completion information of the to-be-completed instruction into an instruction buffer table item in a buffer; and a retirement subunit configured to, according to the instruction completion information stored in each instruction buffer table item, perform retirement processing on a to-be-retired instruction which has been completed but not retired, and delete the instruction completion information of the retired instruction from the instruction buffer table item. The present solution can reduce the hardware resource consumption of the processing unit for the instruction reordering part.

The invention discloses an immersive off-road mode switching mode, and relates to the field of vehicle electronic technology and intelligent cabin man-machine interaction, and the method comprises the steps: responding to a switching instruction, and controlling a virtual camera to move towards an off-road scene along a planned path while preloading resources. The system divides a control state according to a transition progress: in a pre-interaction state that resources are ready but transition is not completed, the off-road instrument assembly is controlled to fade in display and open input, a user pre-operation instruction is temporarily stored in an instruction buffer queue through de-duplication logic, and a physical signal is temporarily not issued through a vehicle bus interface; and when the transition time is over and a fully activated state is entered, the queue is locked, and an instruction is converted into a standard protocol data unit to be sent to a chassis electronic control unit. Through the staged state machine and instruction buffer logic, three-dimensional visual rendering and a bottom layer control time sequence are decoupled, and continuity of interactive operation and deterministic transmission of a control instruction are realized while scene switching smoothness is ensured.

The present application relates to an instruction buffer for a nested loop, and a processor. The processor comprises an instruction dispatch unit, a control status register, and a processing engine. The instruction buffer for a nested loop is configured to: acquire an instruction from the instruction dispatch unit; decode the instruction to acquire one or more total loop count indices respectively associated with one or more nested loops in the instruction; acquire from the control status register one or more total loop counts respectively associated with the one or more total loop count indices; and on the basis of the one or more total loop counts respectively associated with the one or more total loop count indices, send the one or more nested loops to the processing engine.

Systems and methods related to a branch status table and control instruction buffer for processor instruction pipeline are disclosed herein. A processor may include a branch status table and a control instruction buffer. The branch status table may be formed by a set of registers and may store a set of pointers that correspond with a set of branches. The control instruction buffer may store a set of instruction pipeline control data entries in a set of addresses. The pointers may identify addresses which store the most recent instruction pipeline control data entries which proceed the branches that correspond with the pointers. Beneficially, when a branch misprediction occurs, the data structure can effectively be rewound to a point just before the misprediction with minimal overhead.

Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

This disclosure relates to an instruction scheduling device, processor, chip, and electronic device. The instruction scheduling device includes an instruction splitting module, a control buffer, an instruction buffer, an instruction cache, and a scheduler. The instruction splitting module splits the acquired instructions to be processed, sending the instruction control information carried by the instructions to be processed into the control buffer and the instruction execution information carried by the instructions to be processed into the instruction cache. The instruction buffer reads the instruction control information from the control buffer. The scheduler reads the instruction execution information corresponding to the instruction control information from the instruction cache based on the instruction control information from the instruction buffer. The instruction scheduling device of this disclosure can effectively reduce the implementation area of ​​the instruction buffer and save implementation resources.

Disclosed are a system-on-chip, method and device supporting data acquisition and a storage medium, the system comprising: a second DMA controller for starting according to a preset period in response to an enable signal transmitted by a first DMA controller; reading the data acquisition instruction from the instruction buffer area in response to a first starting signal transmitted by the communication controller, and writing the data acquisition instruction into a first data buffer; the communication controller is used for reading the data acquisition instruction from the first data buffer and sending the data acquisition instruction to the target sensor; in response to the to-be-transmitted data transmitted by the target sensor and received by the second data buffer, generating a second starting signal; and the third DMA controller is used for reading the to-be-transmitted data from the second data buffer in response to the second starting signal, and writing the to-be-transmitted data into the data buffer. The system can realize hardware-level real-time acquisition of target sensor data acquisition.

The application discloses an implementation method of a particle filtering algorithm, and comprises the following steps: decomposing the particle filtering algorithm to obtain a plurality of mathematical calculation steps, designing a plurality of hardware calculation units and a plurality of extensible instructions based on the mathematical calculation steps; embedding the plurality of hardware calculation units into an execution layer in a pipeline manner, and sequentially mapping the plurality of extensible instructions to an instruction buffer memory; obtaining an address value in an instruction counter, and obtaining a corresponding extensible instruction from the instruction buffer memory based on the address value; sending an activation signal to a corresponding hardware calculation unit in the execution layer based on the corresponding extensible instruction, so as to perform a calculation operation of the corresponding hardware calculation unit, and storing a calculation result obtained in a corresponding register; and processing the calculation result in all registers based on a load storage unit to obtain an optimal solution of the particle filtering algorithm. The application further discloses an implementation device of the particle filtering algorithm, a computer device and a readable storage medium.

The invention discloses a high-speed communication method based on an embedded instrument. The high-speed communication method comprises the following steps that S1, the instrument receives protocol data; s2, analyzing the protocol data, and extracting effective instructions in the protocol data; s3, setting an instruction buffer pool, and storing the effective instruction into the instruction buffer pool; s4, sending a protocol data receiving response to the test system; and S5, the instrument analyzes and responds to the effective instruction in the instruction buffer pool when the resource is idle, and then waits for receiving the instruction next time. According to the method, the cache thread is additionally arranged, so that temporary storage of the ASCII instruction after the instrument equipment completes VXI-11 unpacking is realized, and resource scheduling is facilitated to complete analysis and response of the ASCII instruction when the instrument is idle. Through the method, the instrument responds to the message when the resource is idle, and message blocking or instruction response failure caused by a high-priority task is avoided. The problems of instruction failure and error response during rapid receiving of instrument equipment during high-speed VXI-11 communication are effectively solved.

The present invention provides an instruction scheduling optimization method based on a directed acyclic graph, comprising: initializing a directed acyclic graph, building a dependency relationship between instructions, and creating a node for each instruction; defining an instruction compounding strategy, using an instruction buffer to sequentially store instructions on the directed acyclic graph, and extracting each instruction type, selecting compoundable instructions in the instruction buffer as candidate instructions according to the defined instruction compounding strategy; performing instruction compounding on the selected candidate instructions, creating a new node for the compound instruction, deleting the predecessor instruction node, updating the directed edges on which the compound instruction has dependencies, and constructing a new directed acyclic graph; based on the updated directed acyclic graph, prioritizing scheduling of instructions on the critical path, and executing the instructions simultaneously. The present invention also provides an instruction scheduling optimization device and compilation method based on a directed acyclic graph, which are used in conjunction with the instruction scheduling optimization method.

The present application relates to the technical field of data cleaning, and more particularly to a stream data cleaning accelerator based on FPGA, which comprises a coarse-grained reconfigurable array cleaning pipeline arranged in a programmable logic region of an FPGA chip and comprising a plurality of processing units; each processing unit is internally provided with an arithmetic logic operation core, a local register stack, a crossbar router and an instruction buffer; a configuration controller is used to issue function configuration instructions to each processing unit in the coarse-grained reconfigurable array cleaning pipeline; a quantitative perception stream neighbor interpolation engine; an interpolation value generation module is used to generate interpolation values according to a precise neighbor set; and a data interface is used to receive original data streams to be cleaned and output cleaned data records. The problems of insufficient throughput of traditional data cleaning schemes and excessively high computational complexity of K-neighbor interpolation methods are effectively solved.

The invention discloses a branch prediction system and method, and the system comprises a main branch predictor, a decoupling queue, and a branch instruction stream processing unit, and the main branch predictor comprises a branch jump target buffer zone subsystem and a branch jump direction prediction subsystem. The decoupling queue generates entries including a PC list and branch data, and the branch instruction stream information processing unit includes a difficult-to-predict branch instruction buffer area and a branch instruction stream information buffer area; the main branch predictor predicts a branch instruction, and a generated prediction result is input into the decoupling queue; and the branch instruction stream processing unit receives the branch analysis information, performs identification and instruction stream analysis on the branch difficult to predict, and feeds back an analysis result to the main branch predictor. According to the method, the problems that the delay of the branch in the speculative execution dependency chain analysis method is difficult to predict, the accuracy is insufficient and the hardware resource overhead is large are solved.

This invention provides a processor instruction fetch control method, system, and electronic device, relating to the field of chip instruction control. This solution additionally sets up an instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached at a specific location in the instruction buffer. Before outputting to the decoding unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that from the external logic perspective, execution is still in sequence. This solves the problem of global blocking caused by instruction fetch failures in existing technologies, and fully leverages the performance advantages of wide-issue CPUs.

The application discloses a toy remote interaction delay alignment method and system based on a software development kit, relates to the technical field of remote interaction control, and comprises the following steps: establishing an inter-user media session among a plurality of control terminals and establishing a control session between the control terminal and the toy; the software development kit collects a control instruction sending timestamp and a toy execution timestamp to calculate a control link delay, and acquires a media link delay of the inter-user media session; a compensation amount is calculated according to a delay difference value, a virtual time axis and a control instruction buffer queue are established, and the sending is dispatched according to the generation time plus the compensation amount; in a multi-user scenario, a collaborative time track containing the expected effective time of each control behavior is constructed, and a recommended collaborative control time window is given. The fine-grained alignment of the control link and the media link is realized, the delay fluctuation is inhibited, and the synchronicity and the sense of immersion of the multi-user remote interaction toy are enhanced.

Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.

The invention discloses an instruction buffer circuit, an instruction buffer method, a chip and electronic equipment, and relates to the technical field of integrated circuits. The circuit comprises a cycle detection circuit, a write-in circuit and a buffer. The cycle detection circuit is used for acquiring the type of the instruction and sending the type of the instruction to the write-in circuit; the writing circuit is used for writing the instruction into the buffer or transmitting the instruction to the instruction execution circuit on the basis of the acquired instruction number, the instruction number stored in the buffer and the instruction number required by the instruction execution circuit under the condition that the type of the instruction indicates that the instruction is a universal instruction; when the type of the instruction indicates that the instruction is an instruction of a loop body, writing the instruction into a buffer; and the buffer is used for sharing the storage space by the general instruction and the instruction of the loop body. According to the scheme, it can be avoided that ibuf and lbuf are designed respectively, the chip area is saved, and the timeliness of instruction execution is improved.

The invention provides an instruction bypass method and device and a storage medium, the method is suitable for a CPU, and the method comprises the steps that in the process that the CPU executes a target program in a user mode, if an exception occurs, the CPU is converted into a kernel mode; the CPU determines a bypass instruction sequence corresponding to the target instruction causing the exception in a kernel mode; after the CPU writes the bypass instruction sequence into the pilot instruction buffer area in the kernel mode, the CPU is restored to the user mode; the pilot instruction buffer area is a preset buffer area; after the CPU executes the bypass instruction sequence in the user mode, the target program continues to be executed. By the adoption of the method, the CPU can complete instruction bypass only by entering the kernel mode once, the dwell time of the CPU in the kernel mode is shortened, and the probability of system jamming of the CPU is reduced.

The application discloses a GPU drawing instruction buffer design method based on frame synchronization, which comprises a FIRST_BRAM memory, a SECOND_BRAM memory, a THIRD_BRAM memory and a read-write controller, adopts a three-level cache architecture, solves the problem of disorder of a frame of drawing instruction caused by the inconsistency of the sending rate of CPU sending drawing instruction and the reading rate of GPU reading drawing instruction, and guarantees the integrity of each frame of drawing instruction; the read-write controller is used to generate the read-write address signals and control signals of the FIRST_BRAM memory, the SECOND_BRAM memory and the THIRD_BRAM memory; and the application can output the graphic primitive drawing instruction and the character drawing instruction in parallel, thereby improving the GPU drawing efficiency.

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux disconnects an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

Systems and methods related to a branch status table and control instruction buffer for processor instruction pipeline are disclosed herein. A processor may include a branch status table and a control instruction buffer. The branch status table may be formed by a set of registers and may store a set of pointers that correspond with a set of branches. The control instruction buffer may store a set of instruction pipeline control data entries in a set of addresses. The pointers may identify addresses which store the most recent instruction pipeline control data entries which proceed the branches that correspond with the pointers. Beneficially, when a branch misprediction occurs, the data structure can effectively be rewound to a point just before the misprediction with minimal overhead.

The invention provides an instruction bypass method, which is suitable for a CPU (Central Processing Unit) and comprises the following steps that: in the process that the CPU executes a target program in a user mode, if an exception occurs, the CPU is converted into a kernel mode; the CPU determines a bypass instruction sequence corresponding to the target instruction causing the exception in a kernel mode; after the CPU writes the bypass instruction sequence into the pilot instruction buffer area in the kernel mode, the CPU is restored to the user mode; the bypass instruction sequence comprises instructions in a delay slot of the target instruction; the CPU executes the bypass instruction sequence in the user mode and continues to execute the target program after the bypass instruction sequence is executed. By the adoption of the method, the CPU can complete instruction bypass only by entering the kernel mode once, the dwell time of the CPU in the kernel mode is shortened, and the probability of system jamming of the CPU is reduced.

To describe techniques for reducing overhead controls.SOLUTION: A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.SELECTED DRAWING: Figure 14

The invention provides a processor instruction reading control method and system and electronic equipment, and relates to the field of chip instruction control, in the scheme, an instruction buffer area is additionally arranged between an instruction fetch queue unit and a decoding unit, and a subsequently hit instruction fetch block is allowed to be read in advance and cached to a specific position in the instruction buffer area. Before the instruction data are output to the decoding unit, the instruction data are rearranged according to the sequence of the instruction fetching blocks, it is ensured that the instruction data are still executed in sequence from external logic, global blocking caused by failure of the instruction fetching process in the prior art is solved, and the performance advantage of a wide-emission CPU can be fully exerted.

The invention provides a memory access processing circuit and method, a medium, equipment and a system on chip, and the circuit comprises an instruction buffer which is configured to buffer a memory access instruction; the memory access controller is configured to respond to the acquired first memory access instruction, write the first memory access instruction into the instruction cache, determine a second memory access instruction depended by the first memory access instruction from the memory access instructions cached in the instruction cache based on the first memory access instruction, and send the determined second memory access instruction to the instruction cache; updating depended information corresponding to the second memory access instruction into an instruction identifier of the first memory access instruction; executing the second memory access instruction in response to the fact that the dependency release indication information corresponding to the second memory access instruction is the first indication information indicating that the dependency relationship is released; and in response to the completion of the execution of the second memory access instruction, updating the dependency release indication information corresponding to the first memory access instruction into the first indication information based on the depended information corresponding to the second memory access instruction, thereby reducing the overhead of storage and comparison processes and improving the memory access efficiency.

The present application relates to a robot control method and device, a robot, a storage medium, and a program product. The method comprises: receiving a first target instruction sent by a client; if the number of instructions stored in the instruction buffer does not reach a preset first threshold, then receiving a push instruction request from the client in a preset communication mode; in response to the push instruction request, sequentially pushing the first target instruction into the instruction buffer, and sequentially performing forward processing on the first target instructions in the instruction buffer; if the number of first target instructions after forward processing reaches a preset second threshold, then receiving a start motion request from the client in a communication mode; in response to the start motion request, sequentially executing the target motion according to the first target instruction after forward processing. The use of this method can improve the efficiency of remote communication control of the robot and make the remote communication control process simpler.