32 results about "Instruction buffer" patented technology

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

Embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and related devices and methods. The present solution is applicable to various chips including CISC instruction set, RISC reduced instruction set (especially RISC-V instruction set), or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips, etc. The instruction retirement unit includes a receiving subunit configured to receive a completion request signal; an arbitration subunit configured to, after determining that a to-be-completed instruction can be completed, send a completion permission signal to an instruction execution unit, and store instruction completion information of the to-be-completed instruction into an instruction buffer table item in a buffer; and a retirement subunit configured to, according to the instruction completion information stored in each instruction buffer table item, perform retirement processing on a to-be-retired instruction which has been completed but not retired, and delete the instruction completion information of the retired instruction from the instruction buffer table item. The present solution can reduce the hardware resource consumption of the processing unit for the instruction reordering part.

The invention discloses an immersive off-road mode switching mode, and relates to the field of vehicle electronic technology and intelligent cabin man-machine interaction, and the method comprises the steps: responding to a switching instruction, and controlling a virtual camera to move towards an off-road scene along a planned path while preloading resources. The system divides a control state according to a transition progress: in a pre-interaction state that resources are ready but transition is not completed, the off-road instrument assembly is controlled to fade in display and open input, a user pre-operation instruction is temporarily stored in an instruction buffer queue through de-duplication logic, and a physical signal is temporarily not issued through a vehicle bus interface; and when the transition time is over and a fully activated state is entered, the queue is locked, and an instruction is converted into a standard protocol data unit to be sent to a chassis electronic control unit. Through the staged state machine and instruction buffer logic, three-dimensional visual rendering and a bottom layer control time sequence are decoupled, and continuity of interactive operation and deterministic transmission of a control instruction are realized while scene switching smoothness is ensured.

The present application relates to an instruction buffer for a nested loop, and a processor. The processor comprises an instruction dispatch unit, a control status register, and a processing engine. The instruction buffer for a nested loop is configured to: acquire an instruction from the instruction dispatch unit; decode the instruction to acquire one or more total loop count indices respectively associated with one or more nested loops in the instruction; acquire from the control status register one or more total loop counts respectively associated with the one or more total loop count indices; and on the basis of the one or more total loop counts respectively associated with the one or more total loop count indices, send the one or more nested loops to the processing engine.

Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and / or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

Disclosed are a system-on-chip, method and device supporting data acquisition and a storage medium, the system comprising: a second DMA controller for starting according to a preset period in response to an enable signal transmitted by a first DMA controller; reading the data acquisition instruction from the instruction buffer area in response to a first starting signal transmitted by the communication controller, and writing the data acquisition instruction into a first data buffer; the communication controller is used for reading the data acquisition instruction from the first data buffer and sending the data acquisition instruction to the target sensor; in response to the to-be-transmitted data transmitted by the target sensor and received by the second data buffer, generating a second starting signal; and the third DMA controller is used for reading the to-be-transmitted data from the second data buffer in response to the second starting signal, and writing the to-be-transmitted data into the data buffer. The system can realize hardware-level real-time acquisition of target sensor data acquisition.

The invention discloses a high-speed communication method based on an embedded instrument. The high-speed communication method comprises the following steps that S1, the instrument receives protocol data; s2, analyzing the protocol data, and extracting effective instructions in the protocol data; s3, setting an instruction buffer pool, and storing the effective instruction into the instruction buffer pool; s4, sending a protocol data receiving response to the test system; and S5, the instrument analyzes and responds to the effective instruction in the instruction buffer pool when the resource is idle, and then waits for receiving the instruction next time. According to the method, the cache thread is additionally arranged, so that temporary storage of the ASCII instruction after the instrument equipment completes VXI-11 unpacking is realized, and resource scheduling is facilitated to complete analysis and response of the ASCII instruction when the instrument is idle. Through the method, the instrument responds to the message when the resource is idle, and message blocking or instruction response failure caused by a high-priority task is avoided. The problems of instruction failure and error response during rapid receiving of instrument equipment during high-speed VXI-11 communication are effectively solved.

The present application relates to the technical field of data cleaning, and more particularly to a stream data cleaning accelerator based on FPGA, which comprises a coarse-grained reconfigurable array cleaning pipeline arranged in a programmable logic region of an FPGA chip and comprising a plurality of processing units; each processing unit is internally provided with an arithmetic logic operation core, a local register stack, a crossbar router and an instruction buffer; a configuration controller is used to issue function configuration instructions to each processing unit in the coarse-grained reconfigurable array cleaning pipeline; a quantitative perception stream neighbor interpolation engine; an interpolation value generation module is used to generate interpolation values according to a precise neighbor set; and a data interface is used to receive original data streams to be cleaned and output cleaned data records. The problems of insufficient throughput of traditional data cleaning schemes and excessively high computational complexity of K-neighbor interpolation methods are effectively solved.

The invention discloses a branch prediction system and method, and the system comprises a main branch predictor, a decoupling queue, and a branch instruction stream processing unit, and the main branch predictor comprises a branch jump target buffer zone subsystem and a branch jump direction prediction subsystem. The decoupling queue generates entries including a PC list and branch data, and the branch instruction stream information processing unit includes a difficult-to-predict branch instruction buffer area and a branch instruction stream information buffer area; the main branch predictor predicts a branch instruction, and a generated prediction result is input into the decoupling queue; and the branch instruction stream processing unit receives the branch analysis information, performs identification and instruction stream analysis on the branch difficult to predict, and feeds back an analysis result to the main branch predictor. According to the method, the problems that the delay of the branch in the speculative execution dependency chain analysis method is difficult to predict, the accuracy is insufficient and the hardware resource overhead is large are solved.

This invention provides a processor instruction fetch control method, system, and electronic device, relating to the field of chip instruction control. This solution additionally sets up an instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached at a specific location in the instruction buffer. Before outputting to the decoding unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that from the external logic perspective, execution is still in sequence. This solves the problem of global blocking caused by instruction fetch failures in existing technologies, and fully leverages the performance advantages of wide-issue CPUs.

The application discloses a toy remote interaction delay alignment method and system based on a software development kit, relates to the technical field of remote interaction control, and comprises the following steps: establishing an inter-user media session among a plurality of control terminals and establishing a control session between the control terminal and the toy; the software development kit collects a control instruction sending timestamp and a toy execution timestamp to calculate a control link delay, and acquires a media link delay of the inter-user media session; a compensation amount is calculated according to a delay difference value, a virtual time axis and a control instruction buffer queue are established, and the sending is dispatched according to the generation time plus the compensation amount; in a multi-user scenario, a collaborative time track containing the expected effective time of each control behavior is constructed, and a recommended collaborative control time window is given. The fine-grained alignment of the control link and the media link is realized, the delay fluctuation is inhibited, and the synchronicity and the sense of immersion of the multi-user remote interaction toy are enhanced.

The application discloses a GPU drawing instruction buffer design method based on frame synchronization, which comprises a FIRST_BRAM memory, a SECOND_BRAM memory, a THIRD_BRAM memory and a read-write controller, adopts a three-level cache architecture, solves the problem of disorder of a frame of drawing instruction caused by the inconsistency of the sending rate of CPU sending drawing instruction and the reading rate of GPU reading drawing instruction, and guarantees the integrity of each frame of drawing instruction; the read-write controller is used to generate the read-write address signals and control signals of the FIRST_BRAM memory, the SECOND_BRAM memory and the THIRD_BRAM memory; and the application can output the graphic primitive drawing instruction and the character drawing instruction in parallel, thereby improving the GPU drawing efficiency.

A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux disconnects an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load / store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

The invention provides an instruction bypass method, which is suitable for a CPU (Central Processing Unit) and comprises the following steps that: in the process that the CPU executes a target program in a user mode, if an exception occurs, the CPU is converted into a kernel mode; the CPU determines a bypass instruction sequence corresponding to the target instruction causing the exception in a kernel mode; after the CPU writes the bypass instruction sequence into the pilot instruction buffer area in the kernel mode, the CPU is restored to the user mode; the bypass instruction sequence comprises instructions in a delay slot of the target instruction; the CPU executes the bypass instruction sequence in the user mode and continues to execute the target program after the bypass instruction sequence is executed. By the adoption of the method, the CPU can complete instruction bypass only by entering the kernel mode once, the dwell time of the CPU in the kernel mode is shortened, and the probability of system jamming of the CPU is reduced.

The invention provides a memory access processing circuit and method, a medium, equipment and a system on chip, and the circuit comprises an instruction buffer which is configured to buffer a memory access instruction; the memory access controller is configured to respond to the acquired first memory access instruction, write the first memory access instruction into the instruction cache, determine a second memory access instruction depended by the first memory access instruction from the memory access instructions cached in the instruction cache based on the first memory access instruction, and send the determined second memory access instruction to the instruction cache; updating depended information corresponding to the second memory access instruction into an instruction identifier of the first memory access instruction; executing the second memory access instruction in response to the fact that the dependency release indication information corresponding to the second memory access instruction is the first indication information indicating that the dependency relationship is released; and in response to the completion of the execution of the second memory access instruction, updating the dependency release indication information corresponding to the first memory access instruction into the first indication information based on the depended information corresponding to the second memory access instruction, thereby reducing the overhead of storage and comparison processes and improving the memory access efficiency.

The invention discloses an industrial communication fault tolerance method and system for collaborative optimization of multiple press lines. The method comprises the steps of collecting multi-dimensional parameters such as communication link quality, an equipment cooperation state and a control instruction buffer state in real time; calculating a system health degree index based on the parameters, and determining a current fault-tolerant level through finite-state machine logic; executing corresponding operation according to the fault-tolerant level, and under the degradation level, increasing the retransmission times of the key data frames and sending redundant copies with consistent serial numbers through a standby communication channel; and under the repair level, switching a communication path and starting a discrete time regulator based on maximum allowable jerk constraint setting of the controlled equipment to carry out online time sequence self-repair. According to the method, graded response and non-inductive recovery under the communication fault are realized, and high availability and continuous and stable operation of the press line are effectively guaranteed.

The invention provides a power-off control method and device for a servo driving system, and the method comprises the steps: responding to a power-off alarm signal of the servo driving system, and executing deceleration braking; determining the braking moments of all servo motor drivers as synchronous rollback triggering moments; based on the synchronous fallback triggering moment, a historical control instruction is called from an instruction cache region, and a fallback operation is executed according to a reverse time sequence of the historical control instruction; wherein the historical control instruction in the instruction cache region is obtained by receiving a real-time control instruction issued by a numerical control system in the servo driving system in real time in the operation process of the servo motor driver and storing the real-time control instruction according to a receiving time sequence. Safety and intelligence of abnormal power failure processing of the servo driving system are improved, workpiece and equipment protection during power failure of the numerical control machine tool is better achieved, and reliability of workpiece and equipment protection during power failure of the numerical control machine tool is improved.

This application relates to an instruction buffer and its control method, a network processor, and a chip. It includes at least a storage module, a read pointer address management module, and a controller. The storage module comprises contiguously addressed memory cells, each storing an entry containing a valid flag, a thread identifier, and instruction data. The controller reads the instruction according to the read pointer address and sends it to the back-end pipeline, simultaneously invalidating the entry flag. The read pointer address management module manages the read pointer. After each read, it searches backward within a preset range from the current address for the first valid flag memory cell. If found, the read pointer is updated to that address; otherwise, it is updated to the address following the end of the range. The instruction buffer of this application only needs to update the read pointer address after reading the instruction, without physically shifting data. Furthermore, the read pointer address can skip invalid instructions, thereby reducing power consumption and minimizing invalid instructions entering the pipeline.

The invention discloses a toy remote interaction delay alignment method and system based on a software development kit, and relates to the technical field of remote interaction control, and the method comprises the steps: building an inter-user media session between a plurality of control terminals, and building a control session between the control terminals and a toy; the software development kit collects a control instruction sending timestamp and a toy execution timestamp to calculate a control link time delay, and obtains a media link time delay of a media session between users; calculating a compensation amount according to the delay difference value, establishing a virtual time axis and a control instruction buffer queue, and scheduling and sending according to the generation time and the compensation amount; and in a multi-user scene, constructing a collaborative time track containing predicted effective time of each control behavior, and giving a recommended collaborative control time window. Fine-grained alignment of a control link and a media link is realized, time delay fluctuation is inhibited, and synchronism and immersion of the multi-user remote interactive toy are enhanced.

The application provides an instruction bypass method, device and storage medium, the method is suitable for a CPU, and the method comprises the following steps: in the process that the CPU executes a target program in a user mode, the CPU is turned into a kernel mode if an exception occurs; the CPU determines a bypass instruction sequence corresponding to a target instruction causing the exception in the kernel mode; the CPU is restored to the user mode after the bypass instruction sequence is written into a leading instruction buffer in the kernel mode; the leading instruction buffer is a preset buffer; and the CPU continues to execute the target program after executing the bypass instruction sequence in the user mode. By using the method, the CPU only needs to enter the kernel mode once to complete the instruction bypass, the residence time of the CPU in the kernel mode is reduced, and the probability of system freezing of the CPU is reduced.

The invention discloses an instruction transmitting module applied to a processor, the processor, equipment and a method, and relates to the technical field of chips. The instruction transmitting module comprises an instruction buffer, a storage unit, a conflict detection unit and an instruction transmitting unit. The instruction buffer is used for storing at least one instruction and respective source register information of the at least one instruction. The storage unit is used for storing respective target register information of at least one uncompleted instruction. The conflict detection unit is used for obtaining a detection result of a first instruction according to respective target register information of the at least one uncompleted instruction and source register information of the first instruction in the at least one instruction, the detection result is used for indicating whether the target register of the at least one uncompleted instruction contains the source register of the first instruction or not. The instruction transmitting unit is used for transmitting a first instruction when the detection result is the first result. According to the scheme, the consumption of storage resources of the processor is reduced by designing the storage unit.

The application provides a reconfigurable instruction fetching system based on a ring queue, which comprises an instruction fetching unit configured to obtain I pieces of instruction information from an external instruction storage, generate a jump instruction hit position vector and a compressed instruction vector; a reconfigurable instruction emission quantity instruction buffer based on a ring queue, configured to receive the I pieces of instruction information, the jump instruction hit position vector and the compressed instruction vector from the instruction fetching unit, and decompose the I pieces of instruction information with a normal instruction length into valid instructions according to the compressed instruction vector and the jump instruction hit position vector; and a decoding unit configured to obtain the valid instructions from the reconfigurable instruction emission quantity instruction buffer based on a ring queue, decode the valid instructions, reconfigure the decoded valid instructions according to preset parameter configurations, adjust the instruction quantity of input and output of the decoding unit according to the reconfigured instruction emission quantity, and further adjust the number of decoding modules in the decoding unit. The application can reduce the complexity of the instruction fetching system.

This invention discloses a low-power single-issue out-of-order execution RISC-V processor, comprising a seven-stage pipeline architecture, namely: an instruction fetch unit, an instruction buffer unit, a decoding unit, a single-instruction issue unit, a physical register file, a parallel out-of-order execution unit, and a retirement unit. The instruction fetch unit serves as the front end of the RISC-V processor; the five-stage pipeline architecture consisting of the decoding unit, the issue unit, the physical register file, the execution unit, and the retirement unit serves as the back end of the RISC-V processor. Through the above technical solution, this invention provides a microarchitecture that is more balanced in performance and power consumption, thereby improving the applicability of the processor core in high-computation-demand and power-sensitive scenarios.

The invention relates to an instruction buffer and a control method thereof, a network processor and a chip, the instruction buffer at least comprises a storage module, a read pointer address management module and a controller, the storage module comprises storage units of continuous addressing, and each unit stores entries containing effective marks, thread identifiers and instruction data; the controller reads out an instruction according to a read pointer address and sends the instruction to a rear-end assembly line, meanwhile, the entry mark is set to be invalid, the read pointer address management module is used for managing a read pointer, after each time of read-out, a first effective mark storage unit is searched forwards within a preset range from the current address, if the first effective mark storage unit is found, the read pointer is updated to the address, and if not, the entry mark is set to be invalid. And if not, updating to the next address of the range end position. According to the instruction buffer, after the instruction is read, only the read pointer address needs to be updated, physical data shifting is not needed, the read pointer address can skip invalid instructions, and therefore power consumption is reduced, and the invalid instructions are prevented from entering an assembly line.

Neural inference chips for computing neural activations are provided. In embodiments, a neural inference chip includes at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a location corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between locations in the instruction buffer. The instruction buffer provides the at least one instruction from an associated location in the instruction buffer to at least one element of the memory array when the memory of the at least one element of the plurality of elements of the memory array contains data associated with the at least one instruction. Each element of the memory array provides a block of data from its memory to its horizontal buffer in response to arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides the block of data to a horizontal buffer of another element of the memory array or to the at least one neural core.

The application discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises: a control unit, which is used for receiving and decoding machine instructions, managing the execution flow of inner and outer loops and microinstruction loops, and generating control signals of each stage of a microinstruction pipeline; a microinstruction buffer, which is used for storing a microinstruction sequence generated in advance by a neural network compiler; a register file, which is used for storing source operands and results of ALU operations; each entry of the register file is composed of a valid bit, a tag bit and a data bit; an ALU calculation core, which adopts a SIMD architecture and comprises multiple parallel arithmetic logic function units; a Load / Store unit, which is used for processing data exchange between the register file and a local buffer; and a data selection interface, which is used for selecting a data source or a target buffer according to a storage tag field of a microinstruction. The application can effectively balance the efficiency and flexibility of the ALU unit in a neural network hardware accelerator.

The invention relates to the technical field of data cleaning, and further relates to an FPGA (Field Programmable Gate Array)-based streaming data cleaning accelerator, which comprises a coarse-grained reconfigurable array cleaning assembly line which is arranged in a programmable logic area of an FPGA chip and comprises a plurality of processing units; an arithmetic logic operation core, a local register file, a crossbar switch router and an instruction buffer area are arranged in each processing unit; the configuration controller is used for issuing a function configuration instruction to each processing unit in the coarseness reconfigurable array cleaning assembly line; a quantitative perception streaming neighbor interpolation engine; the interpolation value generation module is used for generating an interpolation value according to the finely arranged neighbor set; and the data interface is used for receiving the original data stream to be cleaned and outputting the cleaned data record. The problems that a traditional data cleaning scheme is insufficient in throughput and a K neighbor interpolation method is too high in calculation complexity are effectively solved.

The invention provides a method for controlling a view component, a controller and a vehicle, and relates to the technical field of vehicle-mounted equipment control. According to the method, after the target control instruction is received, whether the current state of the target component is the registration state or not is determined, so that the ready opportunity of the target component can be accurately sensed. The target control instruction is stored to an instruction buffer when the target component is not registered (unready), which can ensure that the target control instruction is never lost. And the target control instructions are replayed after the target component is ready, so that complete recovery and synchronization of a correct state can be realized. Namely, according to the method, through a buffering mechanism of the instruction buffering area, the problems that the control instruction is lost due to the fact that the registration sequence is disordered and further the target component is in a false dead state or is abnormal in function can be thoroughly solved, and the control instruction loss is converted into acceptable display delay; and the target component is ensured to present the correct state which is completely the same as the expectation of the vehicle-mounted application.

The invention relates to the technical field of power electronic conversion, and discloses a carrier synchronization and modulation method of a bidirectional three-level chopper, which comprises the following steps: acquiring current at an output end, identifying a polarity switching physical event, acquiring a potential deviation value of a voltage dividing capacitor, and determining a carrier compensation increment; calculating a counting margin of the pulse width modulation controller, and splitting the carrier compensation increment into a first sub-increment and a second sub-increment when the counting margin is judged to be smaller than a register updating safety threshold value; injecting a first sub-increment at the tail end of the current counting period, and pre-loading a second sub-increment into an instruction buffer queue of a shadow register; according to the method, carrier out-of-step caused by hardware heavy load conflicts is eliminated, the neutral-point potential convergence stability is improved, and the time sequence dislocation problem of instruction updating and physical commutation under the high-frequency working condition is solved.